Solid Phase Crystallization poly-Si Research Articles

50-nm Nano-Scaled Vertical-Transistor with NiSi₂ Seed-Induced Vertically Crystallized Poly-Silicon Channel for Very-Large-Scale-Integration.

Vertical-channel MOSFETs are hard to demonstrate a high electrical performance than the planar MOSFETs because of its polycrystalline-silicon (poly-Si) channel for 3-D CMOS ICs. In this paper, we have demonstrated a vertical poly-silicon-channel (VPSC) transistor NiSi2 seed-induced vertical crystallization (SIVC) and compared with the typical SG-VPC MOSFETs with solid-phase crystallization (SPC). The SIVC poly-Si showed large longitudinal grains with low defect trap sites, while the SPC poly-Si showed small spherical grains with large defect trap sites. Therefore, the electrical performance of SG-VPC MOSFETs with SIVC was superior to the SG-VPC MOSFETs with SPC in all aspects.

Identification of geometrically necessary dislocations in solid phase crystallized poly-Si

In this work, the presence of geometrically necessary dislocations (GNDs) in polycrystalline silicon (poly-Si) thin films was detected, suggesting that plastic deformation occurs during the solid phase crystallization (SPC) process of amorphous silicon (a-Si:H). Electron backscatter diffraction was used to characterize dislocations in SPC poly-Si thin films. The elevated temperatures during SPC allow the GNDs to rearrange into arrays, forming low angle grain boundaries. We found that GNDs start forming in poly-Si grains with sizes >∼3 μm, suggesting that larger grains are more defective. GNDs are extra defects in addition to the existing statistically stored dislocations that form during grain growth and hence more care needs to be taken to minimize the formation of GNDs.

Characteristics of Schottky-barrier source/drain metal-oxide-polycrystalline thin-film transistors on glass substrates

Polycrystalline-silicon (poly-Si) Schottky-barrier thin-film transistors (SB-TFTs) with Ptsilicided source/drain junctions were fabricated on glass substrates, and the electrical characteristics were examined. The amorphous silicon films on glass substrates were converted into high-quality poly-Si by using excimer laser annealing (ELA) and solid phase crystallization (SPC) methods. The crystallinity of poly-Si was analyzed by using scanning electron microscopy, transmission electron microscopy, and X-ray diffraction analysis. The silicidation process was optimized by measuring the electrical characteristics of the Pt-silicided Schottky diodes. The performances of Pt-silicided SB-TFTs using poly-Si films on glass substrates and crystallized by using ELA and SPC were demonstrated. The SB-TFTs using the ELA poly-Si film demonstrated better electrical performances such as higher mobility (22.4 cm2/Vs) and on/off current ratio (3 × 106) and lower subthreshold swing value (120 mV/dec) than the SPC poly-Si films.

라만 분석을 통한 비정질 실리콘 박막의 고온 고상 결정화 거동

Solid phase crystallization (SPC) is a simple method in producing a polycrystalline phase by annealing amorphous silicon (a-Si) in a furnace environment. Main motivation of the crystallization technique is to fabricate low temperature polycrystalline silicon thin film transistors (LTPS-TFTs) on a thermally susceptible glass substrate. Studies on SPC have been naturally focused to the low temperature regime. Recently, fabrication of polycrystalline silicon (poly-Si) TFT circuits from a high temperature polycrystalline silicon process on steel foil substrates was reported. Solid phase crystallization of a-Si films proceeds by nucleation and growth. After nucleation polycrystalline phase is propagated via twin mediated growth mechanism. Elliptically shaped grains, therefore, contain intra-granular defects such as micro-twins. Both the intra-granular and the inter-granular defects reflect the crystallinity of SPC poly-Si. Crystallinity and SPC kinetics of high temperatures were compared to those of low temperatures using Raman analysis newly proposed in this study.

Electrochemical and Raman-Scattering Characterizations of Defects in Polycrystalline Silicon Thin Films Formed by Excimer-Laser Annealing, Solid-Phase Crystallization, and Continuous-Wave Laser Lateral Crystallization

We investigated the electronic activity of defects in polycrystalline silicon (poly-Si) thin films grown by excimer-laser annealing (ELA), solid-phase crystallization (SPC), and continuous-wave laser lateral crystallization (CLC). The activity of defects was deduced from the erosion by Secco etching, which is based on enhancement of etching due to electronically active states in the band gap. Hydrogenation protected grain boundaries (GBs) and sub-GBs from etching, which indicates that those defects are originally active and are inactivated by hydrogen. Ingrain defect density was characterized by variation of stress in films with etching, where stress was estimated using Raman spectroscopy. It is shown that ELA poly-Si contains a high density of active defects in grains, while SPC and CLC poly-Si films contain a lower density. That feature of ELA is attributed to freezing of defects in grains during rapid cooling after laser irradiation, which is consistent with the elimination of defects by post-annealing of the ELA film at 1000 °C. For CLC, we deduced that laterally directed growth is effective for decreasing defects.

Characterization of MONOS nonvolatile memory by solid phase crystallization on glass

Solid phase crystallization (SPC) is carried out because of the best uniformity among the various crystallization methods. SPC poly-Si nonvolatile memory (NVM) is expected superior memory property in terms of stable reliability. This paper presents electrical properties of SPC poly-Si NVM on glass.Nonvolatile memory is an ideal portable storage device due to its characteristics of low-power consumption and compact size. Metal/oxide/nitride/oxide/silicon (MONOS) structure memory was fabricated on glass. Silicon oxynitride (SiOxNy) layer grown by nitrous oxide plasma served as a carrier tunnel layer, silicon nitride (SiNx) as charge trap region and silicon dioxide (SiO2) for blocking oxide were deposited to fabricate NVM on SPC poly-Si. SiOxNy, SiNx, and SiO2 films were deposited by using inductively coupled plasma chemical vapor deposition (ICP-CVD). Electrical properties of NVM on glass were analyzed gate voltage–drain current (VG–ID) and charge retention property. We obtained the NVM device with the programming voltage of −12 V, erasing of 11 V, and fast programming/erasing (P/E) time of 1 ms. It has a threshold voltage window memory of about 3.7 V and it still keep a wide threshold voltage window of 2.3 V after 10 years.

多結晶Ｓｉ薄膜トランジスタ製作へのプラズマ技術の応用 超高真空スパッタリング装置を用いた多結晶Ｓｉ膜の形成

Using in ultrahigh-vacuum (UHV) system, we could form polycrystalline silicon films. Polycrystalline silicon (poly-Si) films are formed on glass at substrate temperature below 550°C. We used two methods of crystallization. One is asdeposited polycrystalline Si by an UHV sputtering method and the other is solid-phase crystallization (SPC) of silicon film in UHV conditions. As-deposited poly-Si is oriented to (220) and SPC poly-Si is oriented to (111). The crystallinity is improved by increasing film thickness in as-deposited poly-Si film. Ar atoms, which are used for sputtering, disturb the crystallization. Ar concentration in SPC poly-Si is influenced by annealing pressure and surface conditions of Si film. Oxide layer on Si film disturbs SPC. The field effect mobility, 18 cm2/Vs, was obtained by a SPC poly-Si TFT.

Fabrication of Polycrystalline Si Thin Film for Solar Cells

AbstractThe a-Si/poly-Si thin film tandem solar cell is a promising candidate for low-cost solar cells. We have conducted R&D on poly-Si thin film using the Solid Phase Crystallization (SPC) method from amorphous silicon (a-Si). To improve the film quality of SPC poly-Si, we have developed a new SPC method called the partial doping method. This method features two stacked starting a-Si layers, a P-doped layer and a non-doped layer. Nucleation occurs in the P-doped layer, and the non-doped layer is the crystal growth layer. For the nucleation layer, we developed a Si film with a unique structure, which features relatively large crystallites (-1000A) embedded in a matrix of amorphous tissue. By combining these technologies, a conversion efficiency of 9.2% was obtained for poly-Si thin-film solar cells. For further improvement in the conversion efficiency, based on the concept of “independent control of nucleation and crystal growth”, it is necessary to combine the best fabrication methods for each layer. A high conversion efficiency of more than 12% was found possible by using the CVD method and a new back surface reflection structure.