Solid Phase Crystallization Kinetics Research Articles

Kinetics of solid phase crystallization of amorphous silicon analyzed by Raman spectroscopy

Solid phase crystallization (SPC) of amorphous silicon films grown by low pressure chemical vapor deposition was conducted using a tube furnace in nitrogen ambient at temperatures ranging from 560 °C to 1000 °C. The transformed crystalline fraction shows typical sigmoidal curves as a function of annealing time using Raman analysis adopted in this work. Arrhenius plot of the measured incubation time does not fit to the straight line since SPC kinetics has strong temperature dependence and since the heating rate is slow when using a conventional heating method. The grain size decreases as the annealing temperature increases. It, however, is not sensitive to the annealing temperature beyond 800 °C, since SPC kinetics is complete during the period of heating-up according to Raman spectroscopy. It was observed that doping of impurity atoms affect the crystallization kinetics.

Solid-phase crystallization kinetics and grain structure during thermal annealing of a-Si:H grown by chemical vapor deposition

Abstract Solid-phase crystallization kinetics are examined during thermal annealing of as-deposited hydrogenated amorphous silicon (a-Si:H) thin films deposited by hot-wire chemical vapor deposition (HWCVD) and plasma-enhanced chemical vapor deposition (PECVD). The influence of deposition temperature of HWCVD material on crystallization is also considered. Real-time observation of the crystallization process using in situ transmission electron microscope heating allowed tracking of the crystalline volume fraction and grain number density by image-processing methods. Beyond an initial incubation period, roughly constant grain nucleation rate and growth velocity are observed. Extrapolation from early stages of crystallization allows estimation of the final average grain sizes. PECVD material shows a much lower nucleation rate than does HWCVD material under the same annealing conditions, whereas the grain growth velocities are comparable, leading to dramatically larger grain sizes in PECVD material. X-ray diffraction line widths from PECVD material are broader compared to HWCVD material. The diffraction line broadening is primarily determined by intragranular defect structure, rather than grain size. Low-temperature preannealing reduced the final XRD line widths of HWCVD material, indicating an influence on defect structure or density. Lattice contraction during crystallization of HWCVD material is observed to be independent of the initial hydrogen content.

라만 분석을 통한 비정질 실리콘 박막의 고온 고상 결정화 거동

Solid phase crystallization (SPC) is a simple method in producing a polycrystalline phase by annealing amorphous silicon (a-Si) in a furnace environment. Main motivation of the crystallization technique is to fabricate low temperature polycrystalline silicon thin film transistors (LTPS-TFTs) on a thermally susceptible glass substrate. Studies on SPC have been naturally focused to the low temperature regime. Recently, fabrication of polycrystalline silicon (poly-Si) TFT circuits from a high temperature polycrystalline silicon process on steel foil substrates was reported. Solid phase crystallization of a-Si films proceeds by nucleation and growth. After nucleation polycrystalline phase is propagated via twin mediated growth mechanism. Elliptically shaped grains, therefore, contain intra-granular defects such as micro-twins. Both the intra-granular and the inter-granular defects reflect the crystallinity of SPC poly-Si. Crystallinity and SPC kinetics of high temperatures were compared to those of low temperatures using Raman analysis newly proposed in this study.

Enhancement of Solid-phase Crystallization Kinetics of AmorphousSilicon by Annealing in a High-pressure H$_{2}$O Ambient

Enhancement of Solid-phase Crystallization Kinetics of AmorphousSilicon by Annealing in a High-pressure H$_{2}$O Ambient

Solid Phase Crystallization Kinetics of Amorphous Silicon at High Temperatures

Solid phase crystallization (SPC) of amorphous silicon is usually conducted at around 600°C since it is used In the application of flat panel display using thermally susceptible glass substrate. In this study we conducted SPC experiments at temperatures higher than 600°C using silicon wafers. Crystallization rate becomes dramatically rapid at higher temperatures since SPC kinetics is controlled by nucleation with high value of activation energy. We report SPC kinetics of high temperatures compared to that of low temperatures.

Analysis of the Crystallization Kinetics and Microstructure of Polycrystalline Sige Films by Optical Techniques

AbstractIn this work, two optical techniques, Raman spectroscopy and ultraviolet reflectance, have been used to characterize the solid phase crystallization kinetics and the microstructure of SiGe films deposited by LPCVD on oxidized Si wafers. The results have been compared to those obtained by X-ray diffractometry. The Ge fraction of the films (x) was in the 0−0.38 interval. The samples were crystallized at temperatures ranging from 525 to 600 °C. The crystallization kinetics follows Avrami's model. Two different behaviours have been observed depending on the Ge fraction of the films and the crystallization temperature: a) Either the three experimental techniques yield similar results, or b) the crystallization process, as monitored by UV reflectance and Raman spectroscopy, exhibits a greater incubation time than the one obtained if X-ray diffractometry is used. The results are discussed in terms of the identification of the nucleation sites, taking into account the probe depth of the different techniques and the preferred orientations of the grains. These techniques have also been used to characterize the presence of defects, the overall crystallinity and the surface roughness of the fully crystallized films. The results are correlated to the grain morphology and grain size, obtained by means of transmission electron microscopy.

Crystallization of a‐Si:H on Glass for Active Layers in Thin Film Transistors: Effects of Glass Coating

One hundred nanometer thick a‐Si:H films deposited by plasma‐enhanced chemical vapor deposition from hydrogen diluted silane at temperatures in the range 150–320°C were used as precursor materials for solid‐phase crystallization (SPC) of polycrystalline silicon (poly‐Si) on which n‐channel thin film transistors (TFTs) were fabricated. Furnace annealing at 600°C was used in order to study the SPC kinetics as a function of deposition temperature and substrate coating. The substrates were either bare or silicon nitride coated Corning 7059 glass. The poly‐Si films were characterized by using ultraviolet reflectance spectrophotometry to determine the annealing time for crystallization and by using transmission electron microscopy for grain size measurement and nuclei density analysis. It was found that there is a strong relation between grain size and deposition temperature for films deposited on bare glass substrates. For films deposited on silicon nitride coated glass substrates this correlation is not as strong; however, upon full crystallization, a‐Si:H deposited on nitride coated glass yielded grains that were larger than those in a‐Si:H deposited on bare glass. The presence or absence of a barrier layer between an a‐Si precursor film and substrate glass is observed to greatly affect the SPC process. TFT parameter measurements, on the other hand, have shown that the ‐coating of glass has a significant impact on TFT performance: transistor leakage current is observed to be markedly reduced by coating. This is attributed to the increase in grain size and the decrease in the impurity content of active poly‐Si caused by ‐coating of glass. © 1999 The Electrochemical Society. All rights reserved.

Kinetics of Phase Transitions in Porous Materials

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Approaches to modifying solid phase crystallization kinetics for a-Si films

AbstractThree approaches to modifying the solid phase crystallization kinetics of amorphous silicon thin films are examined with the goal of reducing the thermal budget and improving the poly-Si quality for thin film transistor applications. The three approaches consist of (1) variations in the PECVD a-Si deposition parameters; (2) the application of pre-fumace-anneal surface treatments; and (3) using both rapid thermal annealing and furnace annealing at different temperatures. We also examine the synergism among these approaches.Results reveal that (1) film deposition dilution and dilution/temperature changes do not strongly affect crystallization time, but do affect grain size; (2) pre-anneal surface treatments can dramatically reduce the solid phase crystallization thermal budget for diluted films and act synergistically with deposition dilution or dilution/temperature effects; and (3) rapid thermal annealing leads to different crystallization kinetics from that seen for furnace annealing.

Crystallization study of chemically vapour-deposited amorphous silicon films by in situ x-ray diffraction

The solid phase crystallization kinetics of chemically vapour-deposited amorphous silicon films were studied by in situ X-ray diffraction. We determined the crystalline volume directly from the Bragg peak intensities at various times during isothermal annealing in the temperature range 578 °C < T < 658 °C. From these experiments we deduced that the crystallization was due to nucleation predominantly at the substrate-film interface followed by crystal growth perpendicular to this interface. The crystal growth rate was thermally activated with an activation energy E v of 3.1 eV. A strong 〈111〉 preferred orientation of the growing polycrystal was observed and the grain size remained constant at about 60 nm. Evidence of stresses at the amorphous-crystalline interface during the early stages of crystallization was observed. A comparison with previous conductivity measurements is also carried out.