Solder Thermal Interface Materials Research Articles

Effect of lead-free solder thermal interface material thickness on the reliability of electronic components in a random vibration environment

The reliability of electronic components has persistently posed challenges for engineers. This study addresses the critical need of understanding the impact of random vibration on the reliability of lead-free solder as thermal interface materials (TIM) within electronic components. ANSYS software was deployed to design, develop, and simulate the electronic model, with a focus on the TIM. SAC405 lead-free solder served as the TIM, its thickness was varied between 0.01 to 0.06 mm (at 0.01 mm intervals). The results from this investigation reveal relevant correlations. As the TIM thickness increases, there's a noticeable reduction in stress and strain while the deformation increases. Remarkably, a direct relationship emerges between TIM thickness and fatigue life; thicker TIM correlates with increased fatigue life. In addition, at a TIM thickness of 0.01 mm, the fatigue life measurements were 2.76 x 104, 1.63 x 104, and 0.792 x 104 for Equations 1, 2, and 3, respectively. These findings carry profound implications for engineers, serving as a guiding framework to aid in the selection of optimal TIM thickness for electronic components if lead-free solders are used as TIM. Understanding these trade-offs between stress, strain, deformation, and fatigue life is pivotal, empowering engineers to make informed decisions during electronic system design and development, ultimately enhancing overall reliability. Using lead-free solders as TIM in electronic applications is proposed by this study due to the thermal and reliability benefits presented.

Reliability analysis of SnAgCu lead-free solder thermal interface materials in microelectronics

Purpose In microelectronics industry, the reliability of its components is a major area of concern for engineers. Therefore, it is imperative that such concerns are addressed by using the most reliable materials available. Thermal interface materials (TIMs) are used in electronic devices to bridge the topologies that exists between a heat sink and the flip chip assembly. Therefore, this study aims to investigate the reliability of SAC405 and SAC396 in a microelectronics assembly. Design/methodology/approach In this paper, SnAgCu solder alloys (SAC405 and SAC396) were used as the TIMs. The model, which comprises the chip, TIM and heat sink base, was developed with ANSYS finite element analysis software and simulated under a thermal cycling load of between −40°C and 85°C. Findings The results obtained from this paper were based on the total deformation, stress, strain and fatigue life of the lead-free solder materials. The analyses of the results showed that SAC405 is more reliable than SAC396. This was evident in the fatigue life analysis where it was predicted that it took about 85 days for SAC405 to fail, whereas it took about 13 days for SAC396 to fail. Therefore, SAC405 is recommended as the TIM of choice compared to SAC396 based upon the findings of this investigation. Originality/value This paper is centred on SnAgCu solders used as TIMs. This paper demonstrated that SAC405 is a reliable solder TIM. This can guide manufacturers of electronic products in deciding which SAC solder to apply as TIM during the assembly process.

A computational investigation of the effect of three-dimensional void morphology on the thermal resistance of solder thermal interface materials

Process-induced solder voids have three-dimensional shapes and show spatially random distribution with polydisperse geometric dimensions. There exists no analytical formulation of thermal resistances which incorporates void shapes, distribution and polydispersity variables. This paper uses finite element methods to investigate the effect of realistic void morphology on the thermal resistance of solder thermal interface materials (STIMs). The study has developed two computationally efficient methods for generating voids that show the features of real voids. Cylindrical and spherical void morphologies have been studied. The study is the first attempt, in literature, of characterizing the holistic effects of such realistic three-dimensional void morphologies on the thermal resistance of STIM layers. We have shown a qualitative agreement between our results and simplistic analytical predictions. However, the influence of void shapes, distribution and polydispersity have been shown to contribute to increased thermal resistances. The findings should provide significant insight to electrical/electronics engineers, micro-electronics chips manufacturers and academic research groups working on thermodynamics design of chip scale package (CSP) devices. It is also a framework for investigating objectively, the consequence of voids on the thermo-mechanical response of solder joints.

Numerical assessment of the effect of void morphology on thermo-mechanical performance of solder thermal interface material

The presence of voids in solder thermal interface material (STIM) layers affects the reliability and mechanical performance of formed solder joint. Previous studies suggest that the level of void effect depends not only on the size of the voids but also on the distribution and location of voids. In this work, a void morphology generating algorithm was used to generate representative volume elements (RVEs) depicting the seeming randomness of voids in a given STIM layer. The generated 2D RVEs were converted to 3D RVEs within a finite element modelling (FEM) environment and subsequently incorporated into the chip and heat spreader to complete the geometric model. The maximum damage site in the Sn-3Ag-0.5Cu (SAC305) solder joint as predicted by finite element analysis (FEA) of the geometric model showed a good qualitative agreement with experimental observations elsewhere. Further numerical assessment of the thermo-mechanical performance of SAC305 alloy as STIM layer due to the different generated void morphology was carried out. Results showed that solder voids can either influence the initiation or propagation of damage in the STIM layer, depending on the configuration, size and location of voids. While the small voids around the critical region of the solder joints appeared to enhance stress and strain localisation around the maximum damage site thus facilitating damage initiation; small voids also showed potentials of arresting damage propagation. In addition, results from this study indicated that void located in the surface of the solder joint, particularly voids at the solder/silicon die interface are more detrimental compared to void embedded in the middle of the solder layer. The innovative technique employed in this study to numerically generate realistic solder void morphologies would be beneficial to the solder voids modelling research community.

Fatigue life of lead-free solder thermal interface materials at varying bond line thickness in microelectronics

Microelectronics failure during operation is commonly attributed to ineffective heat management within the system. Hence, reliability of such devices becomes a challenge area. The use of lead-free solders as thermal interface materials to improve the heat conduction between a chip level device and a heat sink is becoming popular due to their promising thermal and mechanical material properties. Finite element modelling was employed in the analysis of the fatigue life of three lead-free solders (SAC105, SAC305, and SAC405) under commercial thermal cycling load (between −40°C and 85°C). This paper presents the results of the simulation work focusing on the effect of varying the solder thermal interface thickness (or bond line thickness) on the reliability of the microelectronic device. The results obtained were based on stress, strain, deformation, and plastic work density. The results showed that the fatigue life of the three solders increases as the solder thermal interface thickness increases. Also, the stresses, strains, and deformation were highest around the edges and vertices of the solder interface. In addition, the optimal solder material of choice based on the criteria of this research is given as SAC405. It has higher operational life span and good reliability capabilities.

Fatigue life analysis of Sn96.5Ag3.0Cu0.5 solder thermal interface material of a chip-heat sink assembly in microelectronic applications

The reliability of microelectronic devices during operation has been a major challenge in recent years. Microelectronics devices will fail if one or more components do not function properly. Thermal interface materials are more likely to fail because of the role they play in heat management. Lead free solders such as SAC305 solder (Sn96.5Ag3.0Cu0.5) have become the thermal materials of interest because of their high thermal conductivity and government legislations on the ban of lead. Ansys finite element software was used for the design and analysis of the microelectronic device studied. The bond line thicknesses of the SAC305 solder thermal interface material were varied from 0.035 mm to 0.175 mm and a thermal load was applied using commercial thermal cycle profile of −40°C to 80°C. The results obtained showed that stresses and strains reduce as the lead free solder thickness increases. The number of cycles to failure and plastic work density increased as the SAC305 solder thickness is increased. This research showed that an increase in SAC305 solder thickness will improve thermal conduction and reliability. However, the solder thickness is limited to the gap between the chip-heat sink surfaces in contact.

Finite element analysis of the effect of silver content for Sn–Ag–Cu alloy compositions on thermal cycling reliability of solder die attach

Thermal performance of a chip-scale packaged power device can be improved by attaching a heat spreader to the backside of the heat generating silicon die via solder thermal interface materials [STIMs]/solder die-attach. Driven by government legislation, electronics industry has advanced to lead (Pb)-free solders due to environmental and health concerns emanating from the use of Pb-based solders. Though solder compositions in the form of Sn–Ag–Cu (SAC) ternary system have been widely accepted and preferred by the electronic industry as replacements for the traditional Pb-based solder alloys, debate continues over the optimal silver content in the Sn–Ag–Cu (SAC) solder alloys. Apparently, the effect of silver (Ag) content on thermo-mechanical reliability of SAC alloy compositions as small area solder joints (flip chip solder bump or ball grid array (BGA)) has been extensively studied but not enough information exist on the effect of Ag percentage in SAC solder alloys when employed as large area solder joint (die-attach application). In this study, non-linear finite element method (FEM) is used for a comparative analysis of the effect of Ag content on the thermal fatigue performance of Sn–3Ag–0.5Cu (SAC305) and Sn–4Ag–0.5Cu (SAC405) when used in die-attach applications under three different thermal cyclic loading cases. The results show that Von-Mises stresses and strain energy in each of the two different SAC solder joints were strong function of the thermal cycle profiles, increasing in the order −55–80°C<−55–125°C<−65–150°C. In addition, this study suggests that the range of stress was relatively greater for the SAC alloy with higher Ag content (SAC405) while the lower Ag content SAC solder (SAC305) experiences a comparatively larger accumulated plastic work under the same thermal cycling condition. Further failure analysis via visual inspection reveals that for all cases of thermal cyclic loading employed in this study, maximum values of strain energy were all located in the corner regions (critical regions) of the solder joints at the side next to the silicon die independent of the Ag content of the solder joints. This paper also highlights the concerns as regards the implementation of conventional thermal fatigue models for accurate life time prediction of large area solder joint.

Numerical study on thermal impacts of different void patterns on performance of chip-scale packaged power device

Chip scale package (CSP) technology offers promising solutions to package power device due to its relatively good thermal performance among other factors. Solder thermal interface materials (STIMs) are often employed at the die bond layer of a chip-scale packaged power device to enhance heat transfer from the chip to the heat spreader. Nonetheless, the presence of voids in the solder die-attach layer impedes heat flow and could lead to an increase in the peak temperature of the chip. Such voids which form easily in the solder joint during reflow soldering process at manufacturing stage are primarily occasioned by out-gassing phenomenon and defective metallisation. Apparently, the thermal consequences of voids have been extensively studied, but not much information exist on precise effects of different patterns of solder die-attach voids on the thermal performance of chip-level packaged power device. In this study, three-dimensional finite element analysis (FEA) is employed to investigate such effects. Numerical studies were carried out to characterise the thermal impacts of various voids configurations, voids depth and voids location on package thermal resistance and chip junction temperature. The results show that for equivalent voiding percentage, thermal resistance increases more for large coalesced void type in comparison to the small distributed voids configuration. In addition, the study suggests that void extending through the entire thickness of solder layer and voids formed very close to the heat generating area of the chip can significantly increase package thermal resistance and chip junction temperature. The findings of this study indicate that void configurations, void depth and void location are vital parameters in evaluating the thermal effects of voids.

Influence of thermal ageing on void content and shear strength for selected lead free solder die-attach

In flip-chip packaging technology, thermal performance can be improved by attaching heat spreader to the backside of the heat generating silicon die via thermal interface material. Solder thermal interface materials (STIMs) are preferred to their polymer-based counterparts because they relatively offer higher thermal conductivities. Unlike lead-based solders which have had a longer application history, lead-free solders are relatively new; thus, the reliability of these lead-free solders are subject of research interest. In this study, lead-free solder preforms with compositions of 96.5Sn3Ag0.5Cu, 99.99In, 97In3Ag and 58Bi42Sn were used for silicon die attachment on copper heat spreader. The void content and shear strength of the soldered joints after thermal ageing at 125°C for 50 hours, 100 hours, 200 hours and 300 hours were evaluated. Generally, the four studied solder joints show decrease in voids with thermal ageing though 96.5Sn3Ag0.5Cu and 58Bi42Sn comparatively manifested more reduction in voids. The shear strengths of 96.5Sn3Ag0.5Cu alloy and 99.99In are shown to be relatively more stable throughout the ageing time. The results also indicate that samples with lower void content comparatively result in higher shear strength and vice versa. These results are especially important for high temperature application environments of Pb-free STIMs like in automotive systems.

Materials Technology for Environmentally Green Micro Electronic Packagin

Intel has been continuously striving to provide environmentally green micro-electronic packaging solutions for high-density interconnect (HDI) product applications. The environmentally green initiative consisted of providing lead-free (Pb-free) packaging materials solutions as well the enabling of halogen-free (HF) substrates technology to eliminate the use of brominated flame retardants. This paper discusses the challenges overcome by Intel to deliver on both aspects of environmentally green packaging. Although Intel’s efforts to enable Pb-free and HF-compliant packaging solutions have been wide-ranging, the scope of this paper is limited to discussing the key technology development challenges faced in transitioning to Pb-free materials in first-level interconnects (FLI), second-level interconnects (2LI), solder thermal interface materials (STIM) applications, and halogen-free (HF) substrate materials. The transition to Pb-free micro-electronic packaging materials and HF substrate technology required a paradigm shift in the industry, needing extensive benchmarking initiatives and sharing cross-technology learnings across the industry and academia. The delivery of Pb-free packaging solutions across FLI, 2LI, and STIM applications as well as HF substrate technology has strongly reinforced Intel’s One Generation Ahead (OGA) philosophy in micro-electronic packaging.