Dip Soldering Research Articles

Rational design and coloration mechanism of soluble intrinsic black polyimide with high comprehensive performance for black flexible copper clad laminates

With the development of flexible printed circuit boards (FPCBs) and photoelectric devices, the demand for black polyimide (BPI) is increasing, but the existing BPIs have some problems, such as poor electrical properties, mechanical performance, masking ability and solubility. To solve these problems, a novel diamine monomer (TPCPOHPDA) containing tetraphenylcyclopentadienone (TPCP) grafted with hydroxyl groups and benzene rings was customized, and then TPCPOHPDA was polymerized with 4,4'-(hexafluoroisopropylidene) diphthalic anhydride (6FDA) to obtain polyimide (TPCPOHPPI). TPCP had a broad UV–visible light absorption range (250–600 nm). Appending benzene rings and auxochrome (hydroxyl groups) on the TPCP skeleton extended the conjugated π-electron system and enhanced the mobility of electrons in the large π bonds, respectively. These structural modifications further extended its light absorption range, and the resulting TPCPOHPPI was dark black with a cutoff wavelength (λcut) of 680 nm and Commission International Eclairage (CIE) lab color parameter L* of 0.7. Simulation calculations indicated that the visible-light absorption that caused the black appearance of TPCPOHPPI was mainly due to the electron transition from HOMO to LUMO occurring within the TPCP-containing diamine moieties, in which the charge mainly transferred from the aryl moieties in positions 2 and 5 to the central cyclopentadienone core. Further investigation showed that TPCPOHPPI had excellent thermal, electrical and mechanical performances and high solubility. The TPCPOHPPI-based two-layer black flexible copper clad laminate (2L-FCCL) possessed good dip soldering resistance and peeling strength. This work provides a new idea for the design and synthesis of soluble intrinsic black polyimide with excellent comprehensive performance.

Experimental and Modeling Study on Delamination Risks for Refinished Electronic Packages Under Hot Solder Dip Loads

For electronic packaging engineers in the high-reliability sectors, such as aerospace, defense, oil & gas, etc., the use of commercial off-the-shelf components offers significant advantages due to their high availability, fast delivery time, and low cost. However, these components pose significant reliability challenges due to the risks associated with tin whisker formation and uncertainty on the long-term reliability of lead-free solders. For addressing these risks, the hot solder dip process is used to refinish the package by replacing lead-free solder finishes with lead-based finishes to meet the stringent packaging and assembly requirements for these sectors, which are exempt from restriction of hazardous substances (RoHS) legislation. But the hot solder dip process is an extra process that exposes the package to an additional thermal load, which will result in thermomechanical stresses that need to be properly understood and controlled. For addressing this challenge, a multidisciplinary methodology combining thermomechanical models with “dip-to-destroy” experiments and scanning acoustic microscopy has been developed to identify the risk of package material delamination for a number of package designs. Results show that the developed models can predict delamination risks for a range of imposed thermal gradients. Electronic package designs with a direct heat path from dipped terminations to the internals of the package show a higher risk of overstress-induced delamination, and this failure is generally driven by the high-temperature excursion above the glass transition point of the molding compound. The novelty and significance of these findings is that the derived methodology can be used by electronic packaging designers to optimize the thermal parameters of the hot-solder-dip process so that subsequent refinished packages can meet the stringent high-reliability requirements for these sectors.

Influence of benzotriazole on electroplated Cu films and interfacial microstructure evolution of solder joints

Benzotriazole (BTA), a nitrogen-containing heterocyclic compound, was employed as a leveler to prepare Cu film. During electroplating, the concentrations of BTA were 0, 10, 20, 50, and 100 ppm. After electroplating, the Cu substrates were soldered by dip soldering with Sn3.0Ag0.5Cu (SAC305) solder at 250 °C for 10 s, then isothermal aging was conducted at 180 °C up to 240 h. The electroplated Cu (EPC) films and solder joints were characterized by scanning electron microscope (SEM), atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), and uniaxial micro-force test system. Experimental results showed that high concentration BTA (≥ 50 ppm) would lead to a reduction in the thickness of the EPC film. The surface roughness of the EPC film increased at first and then decreased with increasing BTA concentration. Additionally, the XPS patterns indicates that the Cu(I)-BTA complex could form on the copper surface. After soldering and thermal aging, for sample with low concentration of BTA (≤ 20 ppm), Cu–Sn intermetallic compound (IMC) was observed between the SAC305 solder and substrate. However, when the BTA concentration increased to 50 and 100 ppm. The Au coating and the Ni coating on the Kovar substrate would participate in interfacial reaction during the dip soldering process, resulting in the formation of single (Ni, Au, Cu)6Sn5 layer. The growth rate of the (Ni, Au, Cu)6Sn5 IMC was significantly lower than that of the Cu–Sn IMCs. Moreover, the incorporated impurities segregated and the doping of Au and Ni resulted in the decrease of shear strength at first and then increase as the BTA concentration increased.

Interfacial IMC Growth and Nanomechanical Characterizations of Solder in Sn-16Sb/Cu Joints during Solid-state Aging

The effects of aging time and temperature on the formation and growth behavior of interfacial intermetallic compound (IMC) of Sn-16Sb/Cu(wt%) solder joints prepared by using dip soldering were investigated. The results show that the major IMCs between Sn-16Sb solder and Cu substrate after thermal aging are Cu3Sn and Cu6Sn5. The thickness of the interfacial IMC in Sn-16Sb/Cu is linearly against the square root of aging time, which indicates that the growth of IMC is mainly controlled by diffusion between Cu and Sn atoms. By using linear regression method, the growth rate constants of interfacial IMC layers are 1.254×10-18, 8.821×10-18 and 1.22×10-17 m2s-1 for Sn-16Sb/Cu joints aged at 120, 150 and 170 °C, respectively. Besides, the activation energy of the interfacial IMC growth was also calculated to be 68.27 kJ/mol. The IMC grain diameters after aging treatment increase with the increasing aging time, with i e, d = 0.492t0.106, d = 0.543t0.143 and d = 0.290t0.263 for aging temperatures of 120, 150 and 170 °C, respectively. Besides, by using nanoindentation, the softening of Sn-16Sb solder was found during aging treatment. Moreover, the U-shape evolution of the values in hardness and Young's moduli was found in this work.

Research on Interfacial Reaction and Growth Behavior of Intermetallic Compound of Dip-Soldered Sn/Ni System

Interfacial reaction and the growth behavior of intermetallic compound (IMC) between Sn solder and Ni substrate by dip soldering under different aging conditions (120 °C, 170 °C and 200 °C) by using scanning electron microscope were investigated. Experimental results showed that the only scallop-shaped Ni3Sn4 IMC layer formed at the interface after aging process and the thickness of IMC layer increased with prolonged aging time. Moreover, the cracks formed in the interface between IMC and solder could be resulted from the residual stress caused by the difference in thermal expansion coefficients. In addition, the spalling behavior of IMC from substrate was caused by cyclic shear stresses and strains induced and the morphological changes in IMC formation. During the aging process, it was found that the thickness of IMC always had a linear relationship with the square root of aging time under different aging temperatures (120 °C, 170 °C and 200 °C). The growth rate constants of IMC layers aged at 120 °C, 170 °C and 200 °C were obtained by using fitting method from the experimental data, which were 4.65 × 10−18 m2 s−1, 9.94 × 10−18 m2 s−1 and 1.76 × 10−16 m2 s−1, respectively. Based on these data, the activation energy of IMC layer was determined to be 63.23 kJ/mol. Likewise, the mean diameter of IMC grains increased with the increase in aging time. It is suggested that the mean diameter of IMC grains was always plotted against the aging time on a double logarithmic scale under different aging temperatures. The time rate constants of IMC grains aged at 120 °C, 170 °C and 200 °C were obtained by using same method, which were 0.10, 0.27 and 0.26, respectively.

Comparative Study on Solid-State and Metastable Liquid-State Aging for SAC305/Cu Joints

In order to study the influence of the physical state of solder on the interfacial reaction of dip-soldered Sn–3.0Ag–0.5Cu/Cu system, two kinds of experiments were designed, including: (1) solid-state aging between the solder and Cu substrate; (2) liquid-state aging between the metastable supercooled liquid-state solder and Cu substrate. The aging times were 30, 60, 120 and 180 min, respectively, and the aging temperature was 8 °C lower than the melting point of the Sn–3.0Ag–0.5Cu (SAC305) alloy (217 °C). The experimental data revealed that the physical state of the solder obviously affected the formation of the intermetallic compound (IMC), and resulted in the difference in the diffusion of atoms on the interface between the SAC305 solder and Cu substrate. The IMC interface after aging for 30 min presents unique characteristics compared with that of the sample after dip soldering. The IMC interface of solid-state aged SAC305/Cu couple is relatively planar, while the IMC interface under metastable supercooled liquid-state aging conditions presents scallop-like shape.

Effects of thermal aging on growth behavior of interfacial intermetallic compound of dip soldered Sn/Cu joints

Intermetallic compounds (IMCs) formations of Sn/Cu reaction couple prepared by dip soldering were studied with isothermal aging at four levels of temperatures (120, 150, 170 and 200 °C, respectively). It is found that an obvious scallop-type layer of Cu6Sn5 IMC formed between the liquid Sn solder and Cu substrates and a planar Cu3Sn IMC layer between Cu6Sn5 IMC layer and Cu substrates appears after solid-state aging treatment. A significant increment of IMC layer thickness is observed with increasing aging time as well as aging temperature. And it is further found that the thickness of IMC layer is linearly related to the square root of aging time during the aging process. The values of growth rate constants for the different solid state aging temperatures (120, 150, 170 and 200 °C) were calculated as 6.578 × 10−18, 1.595 × 10−17, 9.89 × 10−17 and 4.521 × 10−16 m2 s−1, respectively. The apparent activation energy calculated for the growth of the total IMC is 84.43 kJ mol−1. Moreover, The mean diameters of the Cu6Sn5 grains increased linearly with cubic root of aging time.

An Integrated Approach for Via Metallization in Microwave Substrates

Microwave substrates such as glass-reinforced polytetrafluoroethylene (PTFE) are well known for high-speed signal applications due to their inherent properties of low dielectric loss and stable dielectric constant over wide range of frequencies. However, these materials are not as easy as a regular glass epoxy laminate to the process owing to their high chemical inertness, making it difficult to alter the surface topography. This results in low adhesion of seed-layer copper in the drilled vias during metallization process. In order to achieve required surface topography for better adhesion of plated copper, several wet and dry chemical processes are explored. In this paper, the plasma treatment of drilled vias in PTFE laminate using a combination of oxygen and carbon tetrafluoride is studied to achieve required bond strength of the seeded copper layer. It is observed from the experiments that plasma-treated drilled vias followed by immediate seed-layer metallization are free from voids and have higher bond pull strength in both initial and after $3\times $ solder dip tests. The enhanced bond strength of deposited copper to the hole wall barrel is attributed to void-free deposition on the hydrophilic surface created by the plasma process and favorable mechanical interlocking of seed-layer copper inside the highly textured dielectric surface. However, when the metallization was done on plasma-treated vias after 25 h, voids were observed in the deposited seed layer and there was a reduction of bond pull strength by about 1.3% in the initial sample and 2.12% in the $3\times $ solder dip sample than the immediately metallized sample. The presence of voids in the plated through holes and the reduction in the bond pull strength of the plasma-treated sample after 25 h are attributed to limited shelf life of the oxygen-assisted plasma-treated surface. This is due to the atomic-level surface modification generated by plasma process, resulting in self-healing of the thermoplastic fluoropolymer. Hence, the oxygen plasma-treated PTFE surface needs to be interfaced with seed-layer metallization before the deterioration of bondability occurs by the “self-healing” phenomenon.

Similarity approach for reducing qualification tests of electronic components

Qualification analysis and reliability testing of electronic components represent a major activity in the process of development of electronic equipment. Electronics manufacturers have to adopt often costly test programmes to ensure qualification standards and reliability requirements are met. This paper details a novel similarity-based qualification approach for assessing expected reliability of electronic components, and in general electronic products, as an alternative to conventional physical testing. The originality of this work is in the proposed approach which introduces a new way of qualifying electronic components based on similarity with previously assessed and qualified components. This novel approach has the potential to transform in a major way the current operational practices in the industry, demanding at present substantial physical testing, by offering a complementary, “virtual qualification” route for addressing the cost and time challenges associated with qualification tests.A major achievement is the comprehensive and detailed demonstration of the proposed reliability qualification approach. Case studies on qualifying electronic components to the thermal loads induced by a particular post-manufacturing process widely adopted by high-reliability electronics sectors – the robotic hot solder dip (refinishing) process, and associated risks of thermo-mechanical damage are presented and discussed.

ディップはんだ付け工程の熱流動シミュレーション

ディップはんだ付け工程の熱流動シミュレーション

Modelling the impact of refinishing processes on COTS components for use in aerospace applications

Commercial off the shelf components (COTS) are being adopted by electronic equipment manufacturers for use in aerospace applications. To ensure that these components meet the quality and reliability standards, refinishing processes, such as hot solder dip and laser deballing/reballing, are used to replace component lead-free solder terminations with tin–lead solder. These processes provide a risk mitigation strategy against tin whiskers induced short circuit failures. Being an additional step to the subsequent PCB assembly process it is important that this additional process does not impose significant thermo-mechanical stress which can impact subsequent reliability. As part of a major study in collaboration with industry partners, process models have been developed to predict the thermo-mechanical behaviour of components when subjected to the refinishing process. This paper details the techniques used to provide model input data (e.g., process parameters and package geometric/materials data) as well as the development and application of these modelling techniques to the refinishing process.

Interfacial reactions between Cu substrate and Sn–1Ag–0.5Cu solder containing 0.1 wt% Al by dipping method

Effects of 0.1 wt% Al addition to Sn–1Ag–0.5Cu (SAC105) on the structure of solder/copper interface have been studied. The solder/copper joint assembly was prepared by dip soldering process at 250 °C for 10 s and then aged thermally at 150 °C for 500 h for an accelerating aging test. Results show that the addition of Al does not change the type of the reaction product with the Cu substrate. The reaction product is always Cu6Sn5 and Cu3Sn phases formed at the solder/copper interface. However, it is found that the addition of Al retards the interfacial reaction and suppresses the growth of interfacial intermetallic layer(s). Potential mechanisms are proposed to explain the effects of Al addition on the solder/copper interfacial reactions.

A Solder Based Self Assembly Project In An Introductory IC Fabrication Course

Integrated circuit (IC) fabrication principles is an elective course in a senior undergraduate and early graduate student’s curriculum. Over the years, the semiconductor industry relies heavily on students with developed expertise in the area of fabrication techniques, learned in an IC fabrication theory and laboratory course. The theory course gives importance to the physics of manufacturing techniques and is often attached to a subsequent semester laboratory curriculum. The pre-requisite requirement of the theory component for a laboratory course requires students to enroll for two courses in separate semesters and is not an option for all students. Hence, an innovative student project is intended in the theory curriculum to give hands-on experience on the processes. The IC fabrication course is usually associated with high enrollment of students, leading to fewer laboratory experiments. The physics of IC fabrication techniques is important, but few students may perceive the theory as important with no laboratory experience. To improve the course and give students hands-on practice with existing state-of-the-art processing facilities, a tailored project was added to the syllabus. A solder-based self assembly (SBSA) project was introduced in the curriculum for the first time at the University of Alabama in Fall 2011. The student projects were designed in a way to provide an alternative to conventional time-intensive, high cost, and highly tool dependent IC fabrication lab experiments. SBSA forms three dimensional (3D) structures when applied to two dimensional (2D) patterns. The schedule was designed to accommodate theory classes aligned with the fabrication steps and completed by students. The project involved a brainstorming session, a design stage to develop 2D patterns using AutoCAD software, a deposition process, a lithography step, a dip soldering step, a reflow process, scanning electron microscope (SEM) imaging, and a final project presentation. Other processes required to complete the project were performed by the instructor. In general, students showed interest in working in teams, completing the project, and recommended to continuing the SBSA project in future IC fabrication course work. The SBSA project is cost effective and less tool dependent for incorporation in a semester long course. In addition, the project is time effective from both student and instructor perspectives.

The Effects of Humidity on Tin Whisker Growth by Immersion Tin Plating and Tin Solder Dipping Surface Finishes

The drive to replace lead (Pb) from electronics has led to the replacement of tin (Sn) alloys as the terminal plating for electronic devices. However, the deposition of Sn based alloys as the component surface finish tends to induce Sn whisker that causes unintended electric shorts when the conductive whiskers grow across to the adjacent conductor. Internal stress is considered as the driving force that causes the growth of Sn whiskers. In this study, stress type of elevated temperature/ humidity exposure at 55°C/ 85%RH with the storage for up to 24 months was conducted to define the acceleration factor in samples with deposition of immersion Sn plating and Sn solder dipping. The addition of Nickel (Ni) under-layer was also applied to examine the correlation to field conditions. The results showed that the whisker length increased in high humidity irrespective of the deposition methods. It was also shown that pure Sn solder dipping mitigated the whisker growth but does not completely prevent it when alloying Sn with 0.4%wtCu. Additionally, Ni under-layer was indicated to be more efficient in mitigating the growth of whisker by prolonging the incubation time for whisker formation.

J0610201 ディップはんだ付け工程の熱流動シミュレーション : 水平移動する基板による液面変形と温度変動

Dip soldering process with a simple model has been studied using CFD. The horizontal movement of PCB and the variation of temperature field are considered in this study. Open source CFD software OpenFOAM is utilized to simulate two phase thermal-flow of air and solder with moving mesh. Relatively large movement of PCB is reproduced by using two types of mesh and mapping numerical results between two meshes. Natural convection in liquid solder is observed. Moving PCB changes the height of solder surface. The un-equivalent level of solder surface causes flow under the PCB.

Statistical analysis of the impact of refinishing process on leaded components

Refinishing process such as Hot Solder Dip (HSD) process can be used to prevent tin whisker growth in microelectronics components by replacing the lead-free finishes with conventional tin–lead coatings. In some applications, it is also used to ensure reliable solder joints by replacing contaminated finishes and lead-free alloys with tin–lead to result in a homogeneous solder joint with tin–lead paste. In this paper, the impact of a HSD refinishing process on leaded components was statistically studied by comparing the electrical test data of refinished samples with those not-refinished. The likely damage from the component refinishing was thought to be the degradation of package integrity through thermo-mechanical stressing. This might be detectable as a microscopic leakage current if moisture could be encouraged into any open areas. Ten types of leaded components were selected and samples for each type of the component were allocated into 2 lots, one for refinishing and one used as a control. 150 cycles −65/150°C thermal cycling followed by 500h 85%RH/85°C humidity test was applied to all the samples (both refinished and not-refinished) to amplify any incipient failure points and accelerate moisture ingress into the package. Electrical test was then carried out to measure any small changes in current under zero and reverse bias conditions. In the end, a data reduction process in conjunction with a statistical hypothesis test was used to analyze the electrical test data. The results showed that there was no significant difference between the measured currents of refinished and not-refinished post-aged samples. Therefore it was concluded that the refinishing process did not have a significant impact on the tested components. This conclusion was further strengthened by other experimental test results such as CSAM images.

Performance Assessment of a Low Temperature Polymer Conductor for Lead-Free Soldering Processes

An increased interest in low temperature polymer thick film products has become apparent due to the rise of the printed electronics market. The specifications for these products are becoming more demanding with expectations that the low temperature products should perform at a level that is typically reserved for their high temperature counterparts; including solderability with lead free solders, high reliability and strong adhesion. Traditionally, it has only been possible to use leaded solders for soldering to polymer based thick film conductors. Over the last 15 years environmental concerns and legislation have pushed the industry towards a lead free approach. The shift to lead free solders, while beneficial, provides new challenges during processing. The high temperatures required for a lead-free soldering process yield a naturally harsher environment for polymer thick film pastes. In the past these conditions have proven too harsh for the pastes to survive. The polymer thick film discussed in this document aims to address some of these concerns for a highly reliable and easy to process polymer thick film paste. Due to the poor leaching characteristics of polymer thick films, at elevated temperatures, the predecessors of this paste typically soldered at low temperatures with leaded solders. The goal of this paper is to present a low temperature paste that is compatible with a variety of substrates and readily accepts lead-free solder. This paper will discuss a newly formulated low temperature curing (150°C – 200°C) RoHS and REACH compliant paste that shows excellent solderability with SAC305 solder. The paste was evaluated using a dip soldering method at 235°C–250°C on a variety of substrates. The data presented includes solder acceptance, adhesion data, thermal analysis and SEM analysis.

The Effects of Nickel Underlayer and Solder Dipping as Tin Whisker Mitigations in Tin Surface Finishes

Driven by environmental concerns and the enforcement of Restriction of Hazardous Substances Directive (RoHS) to ban the use of lead in electronics, the global electronics industry has migrated toward lead-free electronics. However, the adoption of lead-free tin (Sn) surface finish is known to form whiskers. These whiskers grow spontaneously from the Sn finish layer as a stress-relief over time causing device failures. In the present research, whisker growth is investigated via immersion Sn finishes on Cu substrate. The effects of Sn layer thickness, addition of Ni under-layer and solder dipping on whisker growth are investigated by storing the samples under ambient temperature for up to 24 weeks. The effects of external stresses were also studied using bending test. The results showed that whisker length on immersion Sn increases with time for all the samples either with or without Ni under-layer. Thicker Sn coating showed more whisker growth compared with thinner Sn coating. The longest whisker length of 23μm was observed for Sn coating with 2μm thickness. The addition of Ni as under-layer was found to be more effective in mitigating the whisker growth by extending the incubation time for whisker formation. Compared to immersion Sn, solder dipping in pure Sn showed no whisker growth. However, alloying Sn with 0.4%wtCu resulted in whisker growth indicating the role of Cu in promoting whiskers formation.

Tin oxide coverage on tin whisker surfaces, measurements and implications for electronic circuits

Purpose – This paper aims to evaluate the morphology and thickness of oxides that form on the surfaces of tin whiskers. The problems related to the growth of tin whiskers are stated, and the relevance of oxide layers adhering to whiskers is discussed. Design/methodology/approach – Modern laboratory methods including focused ion beam sectioning, energy dispersive spectroscopy and X-ray photoelectron spectroscopy have been used to characterise the composition of oxides present on the surfaces of 48-year-old whiskers. These very old whiskers had nucleated and grown on electronic equipment stored at ambient temperatures. They were compared to the oxide layers on newly grown 2-week-old whiskers. Findings – A dual oxide film, consisting of stannous and stannic oxides, was found present on both the old and the new whiskers. Measurements of oxide thickness were established for both generations of whiskers and these were noted to be similar to those films present on pure, cleaned bulk tin. Research limitations/implications – Only very new and very old whiskers, and their oxide films, were the focus of this investigation. However, sufficient data were gained to predict the effect both kinds of oxide films would have during whisker bridging between conductors and the risk of short circuits. Thick oxide films (order of 30 nm) may have a greater resistance to shorting, but they will be more difficult to remove during solder dipping (with respect to whisker mitigation). Practical implications – A knowledge of the oxide thickness on growing/gyrating tin whiskers will provide the electronics industry with data useful for establishing the risk of short circuits. It will also be useful during the forensic work associated with component and assembly failure analysis. Originality/value – The data resulting from this study are unique. They are of value to others who may require knowledge of the morphology, composition and thickness of oxides present on tin whiskers of different vintage.

Solder Based Self-Assembled Structures for 3D Integration

A novel way of three dimensional (3D) chip stacking has been designed in a view to improve heat dissipation across the layers. Chip stacking using vertical interconnections forms microscale channels for coolant to circulate through the gaps. Solder-based self-assembled (SBSA) 3D structures have been designed as posts on simulated through silicon vias (TSVs) to prove the processing concept. The processing of SBSA structures using a low temperature solder alloy and dip soldering method is described. Additional processing steps to fabricate interconnected 3D structures were demonstrated. Mechanical grinding of the 3D structures shows that soldered SBSA structures were void free and robust enough to be used as a connection post for chip stacking. SBSA structures provide a solder bump that serves as a connection path in the integration of dissimilar electronic technologies. Conventional copper posts, developed in a previous project, can be an effective approach to integrated circuit (IC) stacking. However, the SBSA post provides more variety in size and shape with a potential to serve as a reservoir for solder to aid in chip bonding. The solder bumps are heat resistant and uniform thicknesses were obtained across a large array of SBSA structures. The electrical durability of SBSA posts were determined by completing I-V measurements after thermal treatments. Fabricated SBSA posts were subjected to thermal cycling with temperatures ranging from room temperature to 300 °C. The interconnected SBSA posts are shown to be stable until 165 °C with little variation in measured resistance.