The use of leadless chip carriers in soldered assemblies represents a relatively new device packaging/interconnection technology. There is little published material treating any of the physical properties of the solder attachment in a quantitative fashion. The application of leadless hermetic chip carriers to high reliability microelectronics prompted a joint preliminary investigation by RCA and Sandia Laboratories to quantitatively characterize the solder assembly interface. It was determined that the mechanical and electrical integrity of the soldered connections could best be assured by measuring the yield strength and electrical resistance versus different fabrication conditions and environmental stresses. Sandia devised a program for parallel sample preparation and testing by both RCA and Sandia Laboratories. This program also included tests to evaluate the thick film material system which will not be reported here. The preparation of samples and the design of methods and fixtures for test!ng the yield strength of the soldered connections under lap shear is described. The measurements reported include values corresponding to controlled variation in fabrication and processing parameters and the different environmental stress conditions. While the sample sizes are quite modest, the methods and fixturing are believed to be of general interest, and the various values found for the yield strength and resistance provide a good indication of the magnitude of the influences of the various processing and environmental stress conditions on the integrity of soldered chip carrier assemblies. The measurement values reported were performed by RCA under contract to Sandia Laboratories and the values appear to correlate with those obtained at Sandia for the same sets of conditions.
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Sep 1, 1985
