Software Partitioning Research Articles

Multi-core model checking and maximum satisfiability applied to hardware-software partitioning

Bounded model checking (BMC) based on satisfiability modulo theories (SMT) is well-known by its capability to verify software. However, its use as optimisation tool, to solve hardware and software (HW-SW) partitioning problems, is something new. In particular, its integration with the maximum satisfiability solver vZ tool, which provides a portfolio of approaches for solving linear optimisation problems over SMT formulas, is unprecedented. We present new alternative approaches to solve the HW-SW partitioning problem. First, we use SMT-based BMC in conjunction with a multi-core support using open multi-processing to create four variants to solve the partitioning problem. The multi-core SMT-based BMC approaches allow initialising many verification instances based on the number of available processing cores, where each instance checks a different optimum value until the optimisation problem is satisfied. Additionally, we integrate the vZ into the BMC, making it a specialised solution for optimisation in a single-core environment. We implement all five approaches on top of the efficient SMT-based context-bounded model checker (ESBMC) and compare them to a state-of-the-art optimisation tool. Experimental results show that there is no single optimisation tool to solve all HW-SW partitioning benchmarks, but based on medium-size benchmarks, ESBMC-vZ had better performance.

Power and Execution Time Optimization through Hardware Software Partitioning Algorithm for Core Based Embedded System

Shortening the marketing cycle of the product and accelerating its development efficiency have become a vital concern in the field of embedded system design. Therefore, hardware/software partitioning has become one of the mainstream technologies of embedded system development since it affects the overall system performance. Given today’s largest requirement for great efficiency necessarily accompanied by high speed, our new algorithm presents the best version that can meet such unpreceded levels. In fact, we describe in this paper an algorithm that is based on HW/SW partitioning which aims to find the best tradeoff between power and latency of a system taking into consideration the dark silicon problem. Moreover, it has been tested and has shown its efficiency compared to other existing heuristic well-known algorithms which are Simulated Annealing, Tabu search, and Genetic algorithms.

Research on Method of Power System Electromagnetic Transient External System Equivalence Based on Fault Current Distribution

随着电力系统的重要性越来越高，仿真作为预防事故的重要手段也显得尤为必要，为提高仿真效率一般将仿真区域外的系统做一个等值，而目前常见的两种等值方法Ward等值法和网络等值法各有优缺点且无法满足大系统多节点的要求。针对以上问题，本文提出了一种基于动态分区的电力系统电磁暂态仿真外部系统等值方法，用来满足大系统多节点情况下的仿真需求，并提出了存在的问题及未来的发展趋势。 Due to fact that the importance of electric power system is higher and higher, the simulation as an important means of accident prevention is very necessary. In order to improve the simulation efficiency, an equivalent area is generally used for simulation system. Two common equivalent methods, Ward equivalent method and network equivalent method, have its advantages and disadvantages and cannot satisfy the requirement of large system more nodes. This paper, to solve above problems, according to a research unit based on the research and development of dynamic partitioning of power system electromagnetic transient simulation software, studies the use of two kinds of common external system equivalence method and dynamic partitioning method, and puts forward the existing problems and future development trend.

The optimal community detection of software based on complex networks

The community structure is important for software in terms of understanding the design patterns, controlling the development and the maintenance process. In order to detect the optimal community structure in the software network, a method Optimal Partition Software Network (OPSN) is proposed based on the dependency relationship among the software functions. First, by analyzing the information of multiple execution traces of one software, we construct Software Execution Dependency Network (SEDN). Second, based on the relationship among the function nodes in the network, we define Fault Accumulation (FA) to measure the importance of the function node and sort the nodes with measure results. Third, we select the top K(K=1,2,…) nodes as the core of the primal communities (only exist one core node). By comparing the dependency relationships between each node and the K communities, we put the node into the existing community which has the most close relationship. Finally, we calculate the modularity with different initial K to obtain the optimal division. With experiments, the method OPSN is verified to be efficient to detect the optimal community in various softwares.

Partitioning Application Using Graph Theory for Mobile Devices in Pervasive Computing Environments

The very first phase in software partitioning is to choose an appropriate clustering methodology before moving the clusters to multiple computational nodes since this stage can impact on the distribution of clusters and eventually on the performance of the overall application. In pervasive computing environments, certain memory and cpu intensive applications would prefer to use the computational nodes (anything with at least networking, storage and cpu capabilities) available in the environment. To this end, this paper investigates the very specific area of clustering or partitioning an object-oriented application running on mobile devices. Graph theory has been used to model an application and a cluster analysis algorithm has been proposed. Details about the implementation are covered, followed by a laboratory application partitioning using the proposed approach. Researchers and software designers willing to investigate software partitioning can consider this practical and easy implementable approach.

Software for partitioning and protecting a water supply network

ABSTRACTWater network partitioning (WNP) concerns the implementation of the paradigm of ‘divide and conquer’ in the water supply systems consisting in dividing a water network into k smaller subsystems by gate valves and flow meters. WNP allows improving the management of water distribution systems by transforming into Smart WAter Networks (SWANs) that represent key subsystems of Smart Cities. WNP is possible if water utilities start to use isolating valves (also with control devices) and flow meters. These instruments open new perspectives for the management of water supply systems both in terms of water saving and water protection. Recently, starting from the advantages offered by computing power and network analysis tools, some techniques based on graph partitioning algorithms have been developed by the authors to improve water management and protection, implementing the paradigm of ‘divide and conquer’. This paper presents the second release of SWANP 2.0 (Smart WAter Network Partitioning and Protection) software that integrates two different algorithms, based on multilevel and multi-agent techniques, for WNP and a novel algorithm, based on a multi-objective function, for water network protection from intentional contamination. The SWANP 2.0 software, developed in Python v2.7.6 language, provides the decision-maker different solutions comparing network layouts with some hydraulic and protection performance indices.

HTJoinSolver: Human immunoglobulin VDJ partitioning using approximate dynamic programming constrained by conserved motifs.

BackgroundPartitioning the human immunoglobulin variable region into variable (V), diversity (D), and joining (J) segments is a common sequence analysis step. We introduce a novel approximate dynamic programming method that uses conserved immunoglobulin gene motifs to improve performance of aligning V-segments of rearranged immunoglobulin (Ig) genes. Our new algorithm enhances the former JOINSOLVER algorithm by processing sequences with insertions and/or deletions (indels) and improves the efficiency for large datasets provided by high throughput sequencing.ResultsIn our simulations, which include rearrangements with indels, the V-matching success rate improved from 61% for partial alignments of sequences with indels in the original algorithm to over 99% in the approximate algorithm. An improvement in the alignment of human VDJ rearrangements over the initial JOINSOLVER algorithm was also seen when compared to the Stanford.S22 human Ig dataset with an online VDJ partitioning software evaluation tool.ConclusionsHTJoinSolver can rapidly identify V- and J-segments with indels to high accuracy for mutated sequences when the mutation probability is around 30% and 20% respectively. The D-segment is much harder to fit even at 20% mutation probability. For all segments, the probability of correctly matching V, D, and J increases with our alignment score.

Hardware software partitioning of control data flow graph on system on programmable chip

A System On Programmable Chip (SOPC) is a circuit that integrates all components of an electronic system into a single chip. It may consist of memories, one or more microprocessors, interface devices, configurable logic blocks and other necessary components to achieve an intended function. In this paper, we propose a new hardware–software partitioning algorithm of control data flow graph for SOPC. The main aim of our algorithm is to find a best compromise between hardware and software implementation of operations in order to satisfy design constraints in terms of latency and hardware resources of the target application. Our algorithm has been evaluated on real hardware device. In fact, experimentations have been done using a real FPGA Virtex-5. Results have shown that our algorithm provides a better performing system with the lowest possible cost compared to existing approaches.

A TTC upgrade proposal using bidirectional 10G-PON FTTH technology

A new generation FPGA-based Timing-Trigger and Control (TTC) system based on emerging Passive Optical Network (PON) technology is being proposed to replace the existing off-detector TTC system used by the LHC experiments. High split ratio, dynamic software partitioning, low and deterministic latency, as well as low jitter are required. Exploiting the latest available technologies allows delivering higher capacity together with bidirectionality, a feature absent from the legacy TTC system. This article focuses on the features and capabilities of the latest TTC-PON prototype based on 10G-PON FTTH components along with some metrics characterizing its performance.

The stochastic Petri net based reliability analysis for software partition integrated modular avionics

As discussed in Partitioning in Avionics Architectures: Requirements, Mechanisms, and Assurance by Rush by, J. [1], integrated modular avionics (IMA) is an embedded version of a centralized time-shared “mainframe,” which provides the hosted applications with the common computing resources and the airborne data network. The features of various IMA systems can be summarized in the following points: 1. high performance shared common computing resources 2. high speed communication network 3. open architecture for both software and hardware.

Software partitioning of hardware transactions

Best-effort hardware transactional memory (HTM) allows complex operations to execute atomically and in parallel, so long as hardware buffers do not overflow, and conflicts are not encountered with concurrent operations. We describe a programming technique and compiler support to reduce both overflow and conflict rates by partitioning common operations into read-mostly (planning) and write-mostly (completion) operations, which then execute separately. The completion operation remains transactional; planning can often occur in ordinary code. High-level (semantic) atomicity for the overall operation is ensured by passing an application-specific validator object between planning and completion. Transparent composition of partitioned operations is made possible through fully-automated compiler support, which migrates all planning operations out of the parent transaction while respecting all program data flow and dependences. For both micro- and macro-benchmarks, experiments on IBM z-Series and Intel Haswell machines demonstrate that partitioning can lead to dramatically lower abort rates and higher scalability.

Adaptive and Random Partition Software Testing

Random testing (RT) and subdomain testing are two major software testing strategies. Their simplicity makes them likely the most efficient testing strategies with respect to the time required for test case selection. However, the disadvantage of RT is its defect detection effectiveness. Adaptive testing (AT) is a feedback-based software testing strategy that has been shown to be more effective than RT and partition testing (PT). However, a major concern in the application of AT is its complexity and computational cost for test case selection. In this paper, we propose a hybrid approach that uses AT and random partition testing (RPT) in an alternating manner. The motivation for this approach is that both strategies are employed such that the underlying computational complexity of AT is reduced by introducing RPT into the testing process without affecting the defect detection effectiveness. A case study with seven real-life subject programs is presented. The experimental results demonstrate that this novel strategy considerably reduces the computational overhead of the original AT strategy but still outperforms the pure RT strategy and PT strategy in terms of the number of test cases used to detect and remove a given number of defects. In addition, a sensitivity analysis is conducted to validate the robustness of our strategy.

Applications of Dynamic Partitioning of Intersection Group

An urban intersection group consists of a set of intersections which are geographically adjacent and strongly correlated with each other [1]. It is the minimal network for traffic control and coordination control. In this paper, based on the dynamic partitioning results of the intersection group provided by the software and data collected by traffic flow detectors, the features of dynamic partitioning software for intersection group are further explored from two aspects: traffic control and emergency response to traffic accidents, using the method of green-wave control and traffic guidance respectively.

Effective Data Security in Virtualization using Maize Routing Technique

Virtualization is a technology that combines or divides computing resources to present one or many operating environments using methodologies like hardware and software partitioning or aggregation, partial or complete machine simulation, emulation, time-sharing and others. The hackers are also making use of it for hiding their identity and to exploit the other machines. One more terminology, as port scanner for scanning the presence of hackers. It is also distorted by them in such a way for the analysis of open ports and also it provides a solution with the roll backing system and the Maize routing. So whenever the information loss occurs, the roll back mechanism is introduced and used as a secondary security. As a primary, the proposed concept of Maize Routing (MR) is used. Here we uses the Base Internet Protocol (IP) of the virtualized system as a reference and produce multiple duplicated IP's. Whenever the presence of the hacker is found, then the revealing mechanism sends a link to the virtual machine and directed to the Maize routing. Then the execution mechanism activates and diverts them in to a wrong direction. Hence the effective data security is achieved by using the mechanism of maize routing.

HARDWARE MODELS FOR AUTOMATED PARTITIONING AND MAPPING IN MULTI-CORE SYSTEMS USING MATHEMATICAL ALGORITHMS

Multi-core CPUs offer several major benefits in embedded systems. For instance, they usually provide higher energy efficiency and more computing power compared to single-core CPUs. However, these benefits do not come for free: A program has to be divided into tasks, which can be executed in parallel on different cores. Partitioning of software and mapping on cores are nontrivial activities that require detailed knowledge about the underlying hardware platform, e.g., the number of cores, their speed, available memories, etc. Such information is typically stored in handbooks. If this information would be available in a machine readable model, we call it hardware model, the partitioning and mapping activities can be automated. In this paper, we propose a hardware model and illustrate it using an example of a Freescale multi-core CPU. We then discuss a small case study situated in the automotive domain, which illustrates the use of the hardware model in partitioning, mapping, and code generation.

Impact of mesh partitioning methods in CFD for large scale parallel computing

It was well known that high performance computing depends on load balance and mesh cell distributions. A well balanced load can improve efficiency of parallel computing and minimizing the number of cells with remote neighbors can reduce the time spent on the data communication among processors. Mesh partitioning methods were able to optimize the mesh cell distributions for large scale parallel computing. In this paper, the open source mesh partitioning software packages, such as Metis, ParMetis, Scotch, PT-Scotch and Zoltan, were ported into Code_Saturne, which is an open source CFD software package, for realizing the optimization on large scale CFD applications. Through the studies, it was found that the mesh partitioning methods strongly affect the CFD code on high performance computing especially for large scale parallel computing.

Identifying extract class refactoring opportunities for internetware

The quality of internetware software is significantly associated with class structure. As software evolves, changes often introduce many unrelated responsibilities to the same classes or distribute tightly-related methods in different classes. These changes make the classes difficult to understand and maintain. Extract class refactoring is an effective technique to improve the quality of software structure by decomposing unrelated methods in one class to create new classes or extracting tightly-related methods from different classes. In this paper, we propose a novel approach for class extraction from internetware source codes. This approach leverages a community structure detection technique to partition software into clusters and extracts classes from the resulting clusters. Our experimental results, which investigate the public well-known internetware PKUAS, indicate that: (1) the proposed approach is much faster than existing search-based clustering approaches (Hillclimbing and Genetic algorithm) and is thus applicable for large-scale internetware; (2) the proposed approach can identify meaningful class extractions for internetware; and (3) Extract Class refactoring candidates identified by the proposed approach significantly improve class cohesion of internetware.

Multi-objective hardware–software partitioning of embedded systems: A case study of JPEG encoder

Embedded systems have become integral parts of today's technology-based life, starting from various home appliances to satellites. Such a wide range of applications encourages for their economic design using optimization-based tools. The JPEG encoder is an embedded system, which is applied for obtaining high quality output from continuous-tone images. It has emerged in recent years as a problem of optimum partitioning of its various processes into hardware and software components. Realizing pairing and conflicting nature among its various cost terms, for the first time the JPEG encoder is formulated and partitioned here as a multi-objective optimization problem. A multi-objective binary-coded genetic algorithm is proposed for this purpose, whose effectiveness is demonstrated through the application to a real case study and a number of large-size hypothetical instances.

Quantitative reactive modeling and verification.

Formal verification aims to improve the quality of software by detecting errors before they do harm. At the basis of formal verification is the logical notion of correctness, which purports to capture whether or not a program behaves as desired. We suggest that the boolean partition of software into correct and incorrect programs falls short of the practical need to assess the behavior of software in a more nuanced fashion against multiple criteria. We therefore propose to introduce quantitative fitness measures for programs, specifically for measuring the function, performance, and robustness of reactive programs such as concurrent processes.This article describes the goals of the ERC Advanced Investigator Project QUAREM. The project aims to build and evaluate a theory of quantitative fitness measures for reactive models. Such a theory must strive to obtain quantitative generalizations of the paradigms that have been success stories in qualitative reactive modeling, such as compositionality, property-preserving abstraction and abstraction refinement, model checking, and synthesis. The theory will be evaluated not only in the context of software and hardware engineering, but also in the context of systems biology. In particular, we will use the quantitative reactive models and fitness measures developed in this project for testing hypotheses about the mechanisms behind data from biological experiments.

A Prototyping Environment for Hardware/Software Codesign of OFDM Systems

To make rapid implementation and verification for the systems becomes important in frontend Application Specific Integrated Circuits. Therefore, a field programmable gate array based hardware/software codesign prototyping environment is proposed to simulate the software implementation and verify the hardware implementation of a baseband OFDM system. The system is implemented by software and hardware partitions, respectively. The analog radio frequency front-end module helps take a full insight into the actual baseband system performance. User datagram protocol is used for data transmission between these two partitions, and hence makes a complete baseband system. With the proposed codesign environment, the software simulation is running over real wireless channels, and the hardware implemental results can be flexibly processed in real time and enhances the design efficiency.