Software Overhead Research Articles

Research on Fault Attacks of Lightweight Cryptographic Algorithms

Fault attacks exploit fault injection techniques to compromise cryptographic systems, compromising device operations and leaking secret keys. Lightweight block cipher algorithms are suitable for resource-constrained environments, ensuring security while reducing hardware and software overhead. This paper summarizes the current research status of fault attacks on some lightweight cryptographic algorithms, including block ciphers, stream ciphers, etc. These studies are crucial for addressing system vulnerabilities, protecting personal privacy, and enhancing the stability of embedded systems. The aim of this paper is to provide comprehensive references for cryptographers, assisting in selecting suitable algorithms and defense strategies.

Fine-grain Quantitative Analysis of Demand Paging in Unified Virtual Memory

The abstraction of a shared memory space over separate CPU and GPU memory domains has eased the burden of portability for many HPC codebases. However, users pay for ease of use provided by system-managed memory with a moderate-to-high performance overhead. NVIDIA Unified Virtual Memory (UVM) is currently the primary real-world implementation of such abstraction and offers a functionally equivalent testbed for in-depth performance study for both UVM and future Linux Heterogeneous Memory Management (HMM) compatible systems. The continued advocacy for UVM and HMM motivates improvement of the underlying system. We focus on UVM-based systems and investigate the root causes of UVM overhead, a non-trivial task due to complex interactions of multiple hardware and software constituents and the desired cost granularity. In our prior work, we delved deeply into UVM system architecture and showed internal behaviors of page fault servicing in batches. We provided quantitative evaluation of batch handling for various applications under different scenarios, including prefetching and oversubscription. We revealed that the driver workload depends on the interactions among application access patterns, GPU hardware constraints, and host OS components. Host OS components have significant overhead present across implementations, warranting close attention. This extension furthers our prior study in three aspects: fine-grain cost analysis and breakdown, extension to multiple GPUs, and investigation of platforms with different GPU-GPU interconnects. We take a top-down approach to quantitative batch analysis and uncover how constituent component costs accumulate and overlap, governed by synchronous and asynchronous operations. Our multi-GPU analysis shows reduced cost of GPU-GPU batch workloads compared to CPU-GPU workloads. We further demonstrate that while specialized interconnects, NVLink, can improve batch cost, their benefits are limited by host OS software overhead and GPU oversubscription. This study serves as a proxy for future shared memory systems, such as those that interface with HMM, and the development of interconnects.

SLIM Tricks: Tools, Concepts, and Strategies for the Development of Planar Ion Guides.

Traveling wave ion mobility experiments using planar electrode structures (e.g., structures for lossless ion manipulation, TW-SLIM) leverage the mature manufacturing capabilities of printed circuit boards (PCBs). With routine levels of mechanical precision below 150 μm, the conceptual flexibility afforded by PCBs for use as planar ion guides is expansive. To date, the design and construction of TW-SLIM platforms require considerable legacy expertise, especially with respect to simulation and circuit layout strategies. To lower the barrier of TW-SLIM implementation, we introduce Python-based interactive tools that assist in graphical layout of the core electrode footprints for planar ion guides with minimal user inputs. These scripts also export the exact component locations and assignments for direct integration into KiCad and SIMION for PCB finalization and ion flight simulations. The design concepts embodied in the set of scripts comprising SLIM Pickins (PCB CAD generation) and pigsim (SIMION workspace generation) build upon the lessons learned in the independent development of the research-grade TW-SLIM platforms in operation at WSU. Due to the inherent flexibility of the PCB manufacturing process and the time devoted to board layouts prior to manufacturing, both scripts serve to enable rapid, iterative design considerations. Because only a few predefined parameters are necessary (i.e., the TW-SLIM monomer width, x position following a TW Turn, and y position following a TW Turn) it is possible to design the exact component layouts and accompanying simulation space in a manner of minutes. There is no known limitation to the board layout capacities of the scripts, and the size of a designed layout is ultimately constrained by the abilities of the final PCB design and simulation tools, KiCad and SIMION, to accommodate the thousands of electrodes comprising the final design (i.e., RAM and software overhead). Toward removing the barriers to exploring new SLIM tracks and the likelihood of layout errors that require considerable revision and engineering time, the SLIM Pickins and pigsim tools (included as Supporting Information) allow the user to quickly design a length of planar ion guide, simulate its abilities to confine and transmit ions, compare hypothetical board outlines to given vacuum chamber dimensions, and generate a near-production ready PCB CAD file. In addition to these tools, this report outlines a series of cost-saving strategies with respect to vacuum feedthroughs and vacuum chamber design for TW ion mobility experiments using planar ion guides.

FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA

With reduced data reuse and parallelism, recent convolutional neural networks (CNNs) create new challenges for FPGA acceleration. Systolic arrays (SAs) are efficient, scalable architectures for convolutional layers, but without proper optimizations, their efficiency drops dramatically for reasons: (1) the different dimensions within same-type layers, (2) the different convolution layers especially transposed and dilated convolutions, and (3) CNN’s complex dataflow graph. Furthermore, significant overheads arise when integrating FPGAs into machine learning frameworks. Therefore, we present a flexible, composable architecture called FlexCNN, which delivers high computation efficiency by employing dynamic tiling, layer fusion, and data layout optimizations. Additionally, we implement a novel versatile SA to process normal, transposed, and dilated convolutions efficiently. FlexCNN also uses a fully pipelined software-hardware integration that alleviates the software overheads. Moreover, with an automated compilation flow, FlexCNN takes a CNN in the ONNX 1 representation, performs a design space exploration, and generates an FPGA accelerator. The framework is tested using three complex CNNs: OpenPose, U-Net, and E-Net. The architecture optimizations achieve 2.3× performance improvement. Compared to a standard SA, the versatile SA achieves close-to-ideal speedups, with up to 5.98× and 13.42× for transposed and dilated convolutions, with a 6% average area overhead. The pipelined integration leads to a 5× speedup for OpenPose.

Sample-Efficient Adaptive Calibration of Quantum Networks Using Bayesian Optimization

All physical systems employed for quantum information tasks must act as unbiased carriers of encoded quantum states. Ensuring such indistinguishability of information carriers is a major challenge in many quantum information applications, including advanced quantum communication protocols. For photons, the workhorses of quantum communication networks, it is difficult to obtain and maintain their indistinguishability because of environment-induced transformations and loss imparted by communication channels, especially in noisy scenarios. Conventional strategies to mitigate these transformations often require hardware or software overhead that is restrictive (e.g., adding noise), infeasible (e.g., on a satellite), or time-consuming for deployed networks. Here we propose and develop resource-efficient Bayesian optimization techniques to rapidly and adaptively calibrate the indistinguishability of individual photons for quantum networks using only information derived from their measurement. To experimentally validate our approach, we demonstrate the optimization of Hong-Ou-Mandel interference between two photons--a central task in quantum networking-- finding rapid, efficient, and reliable convergence towards maximal photon indistinguishability in the presence of high loss and shot noise. We expect our resource-optimized and experimentally friendly methodology will allow fast and reliable calibration of indistinguishable quanta, a necessary task in distributed quantum computing, communications, and sensing, as well as for fundamental investigations.

CFFS: A Persistent Memory File System for Contiguous File Allocation With Fine-Grained Metadata

Extensive research on persistent memory (PM)-aware file systems has led to the development of numerous methods for improving read/write throughput. In particular, accessing or modifying file contents in a similar manner to the memory operations through <i>mmap</i> is a common approach. We designed a file system, CFFS (Contiguous File Allocation with Fine-Grained Metadata File System), to rapidly allocate PM pages to upper layer applications for <i>mmap</i> and to alleviate page fault overheads due to <i>mmap</i>. We optimized the physical contiguity of files in PM to reduce file fragmentation and increase fragment alignment with the goal of reducing software overhead. To achieve this goal, we implemented greedy-based buddy systems and implicit preallocation with a not-most-recently-used (NMRU) policy based on our overall page allocation strategy of considering not only the spatial but also the temporal locality of file access patterns. Furthermore, for efficient and atomic metadata operations, we fully leveraged the byte-addressable property of PM to design fine-grained metadata. CFFS adopts persistent doubly linked lists for directory operations to identify and recover from inconsistencies caused by system failures, doing so without using traditional log mechanisms. In experiments, CFFS showed superior page allocation performance to EXT4-DAX and NOVA did under different PM fragmentation levels. Our allocation algorithm also reduced the cost of page faults for frequently appended files. Finally, CFFS&#x2019;s lightweight directory operations performed excellently in creating and deleting files of various quantities. In summary, the main contribution of the paper is proposing an efficient page allocation algorithm to improve the performance of subsequent <i>mmaps</i>, based on the strategy of considering not only the spatial but also the temporal locality of file access patterns in PM file systems. Another contribution was the fine-grained and log-free method for atomic directory operations.

$\mathit {O(N)}$ Memory-Free Hardware Architecture for Burrows-Wheeler Transform

A novel hardware architecture for Burrows-Wheeler Transform (BWT) scheme is presented. The core idea is to have a memory-free strategy that does not involve any software overhead during BWT operation. This is achieved by introducing a register-file concept and utilizing basic digital logic circuits to perform the entire BWT operation. Additionally, this is a kind of transformation scheme that does not utilize any kind of matrix during transformation, and thereby, it is free from run-time memory consumption. It efficiently handles the string terminating mechanism in the proposed design without involving any extra terminating symbol. This string terminator-free architecture eventually reduces additional operation and storage space to maintain the string, and thereby, the architecture does not necessitate any register read and write operations. This architecture exhibits efficient transformation without involving any indexing method or sorting mechanism during an inverse transformation operation. This architecture achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$O(N)$</tex-math></inline-formula> time complexity compared to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$O(N^{2})$</tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$O(N \log N)$</tex-math></inline-formula> as experienced by the existing state-of-the-art approaches.

QBLKe: Host-side flash translation layer management for Open-Channel SSDs

Open-Channel SSD (OCSSD) shows great potential in high-performance storage systems. Existing applications or file systems rely on host-based Flash Translation Layer (FTL) to use OCSSDs. However, the existing solution cannot fully exploit the OCSSD performance under multi-thread workloads. On the read/write critical paths, we find three components (ring buffer, translation map, and DMA memory pool) that use global spinlocks to achieve atomicity. The spinlocks exhaust CPU time and thus hurt system scalability. Besides, as the number of OCSSD parallel units increases, the granularity of garbage collection (GC) of the existing solution also increases. This results in unnecessary page migrations during GC. In this article, we propose QBLKe as an OCSSD host-based FTL. QBLKe adopts three techniques to improve scalability and minimize software overhead: (1) per-CPU ring buffer, (2) lock-free translation map, and (3) per-CPU DMA pool. To further minimize GC page migrations and the impacts on I/O performance, QBLKe implements per-channel GC and a new scheme called score-based rate limiter. Experimental results show that QBLKe improves up to 78.9% write bandwidth compared with the existing solution. It also increases the peak read IOPS by 139.31% and the GC efficiency by 49.11%.

DiPOSH: A portable OpenSHMEM implementation for short API‐to‐network path

SummaryIn this article, we introduce DiPOSH, a multi‐network, distributed implementation of the OpenSHMEM standard. The core idea behind DiPOSH is to have an API‐to‐network software stack as slim as possible, in order to minimize the software overhead. Following the heritage of its non‐distributed parent POSH, DiPOSH's communication engine is organized around the processes' shared heaps, and remote communications are moving data from and to these shared heaps directly. This article presents its architecture and several communication drivers, including one that takes advantage of a helper process, called the Hub, for inter‐process communications. This architecture allows use to explore different options for implementing the communication drivers, from using high‐level, portable, optimized libraries to low‐level, close to the hardware communication routines. We present the perspectives opened by this additional component in terms of communication scheduling between and on the nodes. DiPOSH is available at https://github.com/coti/DiPOSH.

DiG: enabling out-of-band scalable high-resolution monitoring for data-center analytics, automation and control (extended)

Data centers are increasing in size and complexity, and we need scalable approaches to support their automated analysis and control. Performance counters and power consumption are their key “vital signs”. State-of-the-Art (SoA) monitoring systems provide built-in tools to collect performance measurements, and custom solutions to get insight on their power consumption. However, with the increase in measurement resolution (in time and space) and the ensuing huge amount of measurement data to handle, new challenges arise, such as bottlenecks on the network bandwidth, storage and software overhead on the monitoring units. To face these challenges we propose a novel monitoring platform for data centers, which enables real-time high-resolution profiling (i.e., all available performance counters and the entire signal bandwidth of the power consumption at the plug—sampling up to 20 $$\upmu {\hbox {s}}$$ —with an error below 1%) and analytics, both at the edge (node-level analysis) and on a centralized unit (cluster-level analysis). The monitoring infrastructure is completely out-of-band, scalable, technology agnostic and low cost, and it is already installed in a SoA high-performance compute cluster (i.e., D.A.V.I.D.E. —18th in Green500 November 2017).

DySHARQ: Dynamic Software-Defined Hardware-Managed Queues for Tile-Based Architectures

The recent trend towards tile-based manycore architectures has helped to tackle the memory wall by physically distributing memories and processing nodes. However, this introduced a data-to-task locality challenge and inter-tile communication thus often imposes significant software overhead. Thus, we proposed software-defined hardware-managed SHARQ queues that enable efficient inter-tile communication by leveraging user-defined queues with arbitrarily sized elements. To ensure (remote) processing of queued elements, SHARQ introduces an optional handler task, which is scheduled by hardware on demand. Queue management, intra- and inter-tile data transfer, and handler task invocation are entirely handled by hardware. Only rare tasks, like the dynamic queue creation at run-time, are performed in software. DySHARQ, an extension of SHARQ, enables dynamic and concurrent queue memory management and queue length adjustments to be able to adapt to application and resource requirement changes. The DySHARQ hardware is able to monitor the queue memory requirements at run-time and conditionally schedules a software-defined memory management task. It further optimizes the hardware-software interaction for local queue operations. We integrated DySHARQ into the MPI library used by the NAS benchmarks. The evaluation shows a reduction in execution time by up to 43% (compared to software) for the communication intense IS kernel in a 4 $$\times$$ 4 tile design on an FPGA platform with a total of 80 LEON3 cores. The dynamic memory management reduces the memory footprint by 3.75 $$\times$$ in a 2 $$\times$$ 2 design.

Crab-tree

In recent years, the next-generation non-volatile memory (NVM) technologies have emerged with DRAM-like byte addressability and disk-like durability. Computer architects have proposed to use them to build persistent memory that blurs the conventional boundary between volatile memory and non-volatile storage. However, ARM processors, ones that are widely used in embedded computing systems, start providing architectural supports to utilize NVM since ARMv8. In this article, we consider tailoring B+-tree for NVM operated by a 64-bit ARMv8 processor. We first conduct an empirical study of performance overhead in writing and reading data for a B+-tree with an ARMv8 processor, including the time cost of cache line flushes and memory fences for crash consistency as well as the execution time of binary search compared to that of linear search. We hence identify the key weaknesses in the design of B+-tree with ARMv8 architecture. Accordingly, we develop a new B+-tree variant, namely, &lt;underline&gt;c&lt;/underline&gt; rash &lt;underline&gt;r&lt;/underline&gt; ecoverable &lt;underline&gt;A&lt;/underline&gt; RMv8-oriented &lt;underline&gt;B &lt;/underline&gt;+-tree (Crab-tree). To insert and delete data at runtime, Crab-tree selectively chooses one of two strategies, i.e., copy on write and shifting in place, depending on which one causes less consistency cost. Crab-tree regulates a strict execution order in both strategies and recovers the tree structure in case of crashes. To further improve the performance of Crab-tree, we employ three methods to reduce software overhead, cache misses, and consistency cost, respectively. We have implemented and evaluated Crab-tree in Raspberry Pi 3 Model B+ with emulated NVM. Experiments show that Crab-tree significantly outperforms state-of-the-art B+-trees designed for persistent memory by up to 2.2× and 3.7× in write and read performances, respectively, with both consistency and scalability achieved.

An efficient hybrid digital architecture for space vector PWM method for multilevel VSI

This paper presents an efficient, cost effective design implementation of a hybrid digital architecture for space vector pulse width modulation (SVPWM) method for multilevel inverters (MLIs). The SVPWM method is one of the most popular real time PWM method for three phase voltage source inverter (VSI). The implementation of SVPWM method becomes complex with an increase in the number of levels in a multilevel inverter. The SVPWM method for multilevel inverter is a multitask system. The main constraint when it comes to implementing SVPWM for multilevel inverters is the processing of dwell time computation and the generation of PWM gate signals for all of the switches with an accurate delay. A hybrid hardware structure consisting of a simple low-cost, low-power dsPIC micro controller (dsPIC 30F4011) and a state of the art Field Programmable Gate Array (FPGA) (Cyclone V 5CGXFC5C6F27C7N) is used to implement SVPWM. The proposed hybrid digital architecture utilizes the advantages and resources of the dsPIC and FPGA. The hybrid digital architecture meets the timing constraints of multitasking through synchronization and parallelism. A communication interface between the dsPIC and the FPGA reduces the design complexity. The software overhead for the communication interface remains fixed for any number of levels. The hybrid structure of the digital architecture provides scalability for the SVPWM method with more number of levels in multilevel inverter. The operation of the proposed hybrid digital architecture is experimentally validated with an optimized SVPWM method for a five level VSI. An optimized region identification algorithm and simple dwell time expressions are described for a five level SVPWM. The input DC of the five level VSI is obtained from a differential power processing (DPP) based PV system. Experimental results under different operating conditions are presented.

Using Approximate Computing and Selective Hardening for the Reduction of Overheads in the Design of Radiation-Induced Fault-Tolerant Systems

Fault mitigation techniques based on pure software, known as software-implemented hardware fault tolerance (SIHFT), are very attractive for use in COTS (commercial off-the-shelf) microprocessors because they do not require physical modification of the system. However, these techniques cause software overheads that may affect the efficiency and costs of the overall system. This paper presents a design method of radiation-induced fault-tolerant microprocessor-based systems with lower execution time overheads. For this purpose, approximate computing and selective fault mitigation software-based techniques are used; thus it can be used in COTS devices. The proposal is validated through a case study for the TI MSP430 microcontroller. Results show that the designer can choose among a wide spectrum of design configurations, exploring different trade-offs between reliability, performance, and accuracy of results.

Modeling and Optimization for Self-powered Non-volatile IoT Edge Devices with Ultra-low Harvesting Power

Energy harvesters are becoming increasingly popular as power sources for IoT edge devices. However, one of the intrinsic problems of energy harvester is that harvesting power is often weak and frequently interrupted. Therefore, energy harvesting powered edge devices have to work intermittently. To maintain execution progress, execution states need to be checkpointed into the non-volatile memory before each power failure. In this way, previous execution states can be resumed after power comes back again. Nevertheless, frequent checkpointing and low charging efficiency generate significant energy overhead. To alleviate these problems, this article conducts a thorough energy efficiency analysis and proposes three algorithms to maximize the energy efficiency of program execution. First, a non-volatile processor-aware task scheduling algorithm is proposed to reduce the size of checkpointing data. Second, a tentative checkpointing avoidance technique is proposed to avoid checkpointing for further reduction of checkpointing overhead. Finally, a dynamic wake-up strategy is proposed to wake up the edge device at proper voltages where the total hardware and software overhead is minimized for further energy efficiency maximization. The experiments on a real testbed demonstrate that, with the proposed algorithms, an edge device is resilient to the extremely weak and intermittent power supply and the energy efficiency can be achieved more than 2× higher than the fundamental baseline and 1.5× higher than the state-of-the-art technique.

Exploring Fault-Tolerant Erasure Codes for Scalable All-Flash Array Clusters

Large-scale systems with all-flash arrays have become increasingly common in many computing segments. To make such systems resilient, we can adopt erasure coding such as Reed-Solomon (RS) code as an alternative to replication because erasure coding incurs a significantly lower storage overhead than replication. To understand the impact of using erasure coding on the system performance and other system aspects such as CPU utilization and network traffic, we build a storage cluster that consists of approximately 100 processor cores with more than 50 high-performance solid-state drives (SSDs), and evaluate the cluster with a popular open-source distributed parallel file system, called Ceph. Specifically, we analyze the behaviors of a system adopting erasure coding from the following five viewpoints, and compare with those of another system using replication: (1) storage system I/O performance; (2) computing and software overheads; (3) I/O amplification; (4) network traffic among storage nodes, and (5) impact of physical data layout on performance of RS-coded SSD arrays. For all these analyses, we examine two representative RS configurations, used by Google file systems, and compare them with triple replication employed by a typical parallel file system as a default fault tolerance mechanism. Lastly, we collect 96 block-level traces from the cluster and release them to the public domain for the use of other researchers.

A Secure Exception Mode for Fault-Attack-Resistant Processing

Fault attacks are a known threat to secure embedded implementations. We propose a generic technique to detect and react to fault attacks on embedded software. The countermeasure combines a micro-architecture extension in hardware with a secure trap in software. The combined extension leads to a secure exception mode to handle fault attacks. The microprocessor hardware uses a low-level hardware checkpointing mechanism to recover from fault injection. A high-level secure trap in software then enables an application-specific response. The trap is user-defined and can be co-developed with the application. The combination of hardware fault detection and recovery, with a high-level fault response policy in software leads to significantly lower overhead when compared to traditional redundancy-based techniques in hardware or software. We demonstrate a prototype implementation of the proposed secure exception mode. The prototype is based on a modified LEON3 processor and it is able to detect and respond to setup-time violation attacks. We have realized the design in a 180 nm standard cell ASIC with integrated memory. Using several driver application examples, we characterize the software and hardware overhead of the proposed solution, and we compare it to the conventional redundancy-based solutions. In our understanding this is the first proof-in-silicon processor to offer a comprehensive secure exception mode against fault-injection attacks.

Efficient implementation of MPI-3 RMA over openFabrics interfaces

The Message Passing Interface (MPI) standard supports Remote Memory Access (RMA) operations, where a process can read or write memory of another process without requiring the target process to be involved in the communication. This enables new more efficient programming models.This paper describes the RMA design and implementation in MPICH-OFI, an MPICH-based open source implementation of the MPI standard that uses the OpenFabrics Interfaces* (OFI*) to communicate with the underlying network fabric. MPICH-OFI is based on a new communication layer called CH4, which was designed to achieve high performance by minimizing the runtime software overhead and by having an internal API that is well aligned with MPI functions. MPICH-OFI uses the OpenFabrics Interfaces (OFI), a lightweight communication framework to support modern high-speed interconnects. Thanks to CH4 and OFI, MPICH-OFI achieves low latency and high bandwidth for RMA operations. Our experimental results using microbenchmarks show that MPICH-OFI achieves more than 3x better put/get latency and bandwidth than MPICH CH3, 10% better latency than Open MPI and MVAPICH2, and more than 1.7x bandwidth than MVAPICH2 for small messages ( ≤ 4KB), on Intel® Omni-Path Architecture.

OFDM-OAM Modulation for Future Wireless Communications

Orbital angular momentum (OAM) has attracted considerable attention as a novel solution for wireless communications because its orthogonal modes significantly increase the channel capacity without an additional frequency band. The joint multiplexing between OAM technologies and other modulation techniques has not been thoroughly investigated. In this paper, we first proposed the orthogonal frequency-division multiplexing-orbital angular momentum (OFDM-OAM) multiple-input-multiple-output (MIMO) system. The proposed OFDM-OAM MIMO based on the discrete Fourier transformation (DFT) operations achieves a very high sum-rate and spectrum efficiency (SE). However, the expensive hardware and software overheads for transmitting and receiving OAM waves lead to an unexpected cost for the OFDM-OAM MIMO scheme. A time-switched OFDM-OAM (TOO) MIMO is then proposed to reduce the computational complexity, and the procedure of OAM generations and recoveries has also explicitly been derived. The mathematical derivation shows that the proposed TOO MIMO system based on a simple switching sequence is suitable for small-scale and low-cost wireless broadband communications, and the simulation results demonstrate that the TOO MIMO scheme achieves a considerable SE and much less computational complexity than the OFDM-OAM MIMO scheme.

Channel autocorrelation-based dynamic slot scheduling for body area networks

As a promising technology in the context of m-health and e-medical, wireless body area networks (WBANs) have a stringent requirement in terms of transmission reliability. Meanwhile, the wireless channel in WBANs is prone to deep fading due to multiple reasons, such as shadowing by the body, reflection, diffraction, and interference. To meet the challenge in transmission reliability, the dynamic slot scheduling (DSS) methods have attracted considerable interest in recent years. DSS method does not require extra hardware or software overhead on the sensor side. Instead, the hub optimizes the time-division multiple access slots by selecting the best permutation at the beginning of each superframe to improve the transmission reliability. However, most existing DSS works optimize the time slot scheduling based on a two-state (“good” or “bad”) Markov channel model, which is insufficient for human daily life scenarios with a variety of irregular activities. In this paper, we first collect the channel gain data in the real human daily scenarios and analyze the autocorrelation of wireless channels based on this real database. Motivated by the significant temporal autocorrelation, we then propose a new DSS method, which applies a temporal autocorrelation model to predict the channel condition for future time slots. The new method is designed to be compatible with IEEE 802.15.6 standard. Compared to the classical Markov model-based methods, simulation results show that the newly proposed DSS method achieves up to 12.9% reduction in terms of packet loss ratios.