Software Layer Research Articles

I/O Access Patterns in HPC Applications: A 360-Degree Survey

The high-performance computing I/O stack has been complex due to multiple software layers, the inter-dependencies among these layers, and the different performance tuning options for each layer. In this complex stack, the definition of an “I/O access pattern” has been reappropriated to describe what an application is doing to write or read data from the perspective of different layers of the stack, often comprising a different set of features. It has become common to have to redefine what is meant when discussing a pattern in every new study, as no assumption can be made. This survey aims to propose a baseline taxonomy, harnessing the I/O community’s knowledge over the past 20 years. This definition can serve as a common ground for high-performance computing I/O researchers and developers to apply known I/O tuning strategies and design new strategies for improving I/O performance. We seek to summarize and bring a consensus to the multiple ways to describe a pattern based on common features already used by the community over the years.

A Software-Defined Distributed Architecture for Controlling Unmanned Swarm Systems

An unmanned swarm is usually composed of a group of homogeneous or heterogeneous hardware platforms, software control systems, and interfaces for human–computer interaction that operate collectively to achieve a specific goal by information interaction. They exhibit robustness and fault tolerance when facing complex missions, making it crucial in military, transportation, intelligent traffic, and other fields. However, the coupling between the hardware and software of a heterogeneous unmanned swarm can indeed have significant implications for system flexibility, software development and deployment, and hardware maintenance. Over the years, there has been a significant shift from traditional hardware-focused control systems to a greater emphasis on the core software layer. In this paper, a distributed network architecture is proposed to solve this problem, in which hardware resources are abstracted and represented to accomplish standardization and unification by defining a consistent and uniform set of data formats, and a resource pool of hardware data is constructed to realize the function that the number and scale of platforms is irrelevant, the task module can be plug-and-play at any time, and the software can be configured on demand. The resource scheduling of a single platform is achieved through process and thread communication using shared memory, while the resource scheduling of a cross platform is achieved through a network using request and response and subscription and notification. As a result, it can satisfy the development of functional modules in a software-defined mode and gradually improve the intelligence capability of an unmanned swarm. Based on the above architecture, the overall framework of the autonomous navigation system and the collaborative control system has been successfully established. Finally, a hardware-in-the-loop simulation environment is constructed, and the integration and verification of the proposed distributed architecture is carried out by the cooperative formation experiment, which proves the feasibility of this proposal.

Implementation of a 4G/5G Base Station Using the srsRAN Software and the USRP Software Radio Module

This article presents the potential applications and scenarios for the implementation of a software-defined radio (SDR) module operating as a base station in 4G/5G networks. The paper presents test configurations of the srsRAN software environment in conjunction with various types of programmable radio modules. Then, the key performance metrics of the mobile telephony system and potential problems that may be encountered while implementing hardware and software layers are presented.

Security Aspects of Cryptocurrency Wallets—A Systematic Literature Review

Cryptocurrencies are gaining prominence among individuals and companies alike, resulting in the growing adoption of so-called cryptocurrency wallet applications, as these simplify transactions. These wallets are available in a myriad of different forms and specifications. All of them are susceptible to various ways the attacker can exploit the vulnerabilities and steal money from victims. Cryptocurrency wallets create a unique field as they combine features of password managers, banking applications, and the need to keep their users and their transactions anonymous. We collect the findings from previous literature to provide an overview of the different attack surfaces, possible countermeasures, and further research. Existing literature focused on one of the features mentioned before, while we considered all of them. Our systematic study shows that there is a considerable variety of attack vectors, which we have divided into six subcategories, (i) Memory and Storage, (ii) Operating Systems, (iii) Software Layer, (iv) Network Layer, (v) Blockchain Protocol, and (vi) Others. We have found a large gap between the possible countermeasures and their actual adoption. Therefore, we provide a list of possible directions for future research to tackle this gap.

Design and Optimization of a Distributed File System Based on RDMA

With the rapid development of computer and network technology, to deal with explosively growing mass data correctly, distributed file systems have come into being, and they have been applied in many enterprises. However, in the packet storage process, the traditional TCP/IP transmission protocol has to pass through the operating system and application software layer. It takes up many server resources and memory bus bandwidth, which places a heavy burden on the server’s CPU and memory. In this paper, we analyze the research status of the distributed file system based on analyzing and comparing the advantages of RDMA over traditional TCP Ethernet communication architecture. We propose an optimization scheme for the network transmission performance of the original FastDFS to replace the original TCP module with an RDMA network communication module, and we design a lightweight distributed file system with higher performance than the original FastDFS, which is suitable for small file storage. Using the zero-copy technology and kernel bypass technology of soft RDMA, the network communication mechanism in FastDFS is optimized to free the server’s CPU from heavy data processing work. In this paper, the RDMA-based FastDFS is compared with the original FastDFS. The test results show that the network transmission performance of the optimized FastDFS is improved compared with the original FastDFS, which achieves the expected effect and can better meet the requirements of mass small file storage for today’s Internet applications.

Developing a unit testing framework for control system software implementation of a degassing vacuum pumping station

Research objective is to develop a test automation system for the process algorithm software implementation of the degassing vacuum pumping station control system operation at a coal mine. Relevance. The vacuum pumping station is an essential component of a mine degassing system. Degassing system operation depends on its correct functioning. A programmable logic controller with appropriate software is a key component of the vacuum pumping station automation system. Correct software implementation of the system operation process algorithm is of primary importance. To verify the compliance of the implementation with the requirements, manual testing is commonly used according to a pre-compiled test-plan, which is formed based on the requirements imposed on the system. Manual testing has a number of disadvantages. It is a long process where human errors are likely to occur, and the use of a test bench and/or an assembled control system sample is inevitable. Requirements for the algorithm can be changed in the course of program development, debugging, and initiation, which greatly complicates the testing process. Results. To solve the problem of process algorithm software implementation testing automation, the process control algorithm should be isolated from the software components responsible for the hardware. Access to the process control algorithm should be provided through standard interfaces (for example, OPC UA). Additional process equipment (valves, etc.) used in the automation system should be implemented in the form of emulators with an opportunity to assign their modes of operation. By creating an additional software layer of interaction with a process algorithm and emulator in a programming language with advanced test tools (for example, Python), it is possible to implement test scenarios from a test plan in this language. It will allow testing in automatic mode rather than manually. Conclusions. The proposed approach to process algorithm software implementation testing automation will greatly simplify software development for this type of automation and control systems

KVRangeDB: Range Queries for a Hash-based Key–Value Device

Key–value (KV) software has proven useful to a wide variety of applications including analytics, time-series databases, and distributed file systems. To satisfy the requirements of diverse workloads, KV stores have been carefully tailored to best match the performance characteristics of underlying solid-state block devices. Emerging KV storage device is a promising technology for both simplifying the KV software stack and improving the performance of persistent storage-based applications. However, while providing fast, predictable put and get operations, existing KV storage devices do not natively support range queries that are critical to all three types of applications described above. In this article, we present KVRangeDB, a software layer that enables processing range queries for existing hash-based KV solid-state disks (KVSSDs). As an effort to adapt to the performance characteristics of emerging KVSSDs, KVRangeDB implements log-structured merge tree key index that reduces compaction I/O, merges keys when possible, and provides separate caches for indexes and values. We evaluated the KVRangeDB under a set of representative workloads, and compared its performance with two existing database solutions: a Rocksdb variant ported to work with the KVSSD, and Wisckey, a key–value database that is carefully tuned for conventional block devices. On filesystem aging workloads, KVRangeDB outperforms Wisckey by 23.7× in terms of throughput and reduce CPU usage and external write amplifications by 14.3× and 9.8×, respectively.

Virtualization Maturity in Creating System VM: An Updated Performance Evaluation

Virtualization technologies are indispensable in operating data centers and supporting cloud infrastructures, providing cost reduction (CapEx and OpEx), high availability, and disaster recovery. Hypervisor-assisted virtualization is one of the leading virtualization technologies, with the hypervisor being the software layer responsible for presenting the virtualized view of the hardware to system-level VMs. However, the virtualization overhead it introduces has implications into the computing infrastructure performance. This paper revisits key concepts about virtualization, technologies and techniques, types of VMs and hypervisors, and provides an up-to-date comparison between native and VM environments using workload metrics such as CPU and memory scores, disk speed, and network throughput to determine virtualization overhead. Our results show a clear overall trend toward meritorious performance and the maturity of the technologies used to create system-level VMs.

Flexible system software scheduling for asymmetric multicore systems with PMCSched: A case for Intel Alder Lake

SummaryAsymmetric multicore processors (AMPs) couple high‐performance big cores and power‐efficient small ones, all exposing a shared instruction set architecture to software, but with different microarchitectural features. The energy efficiency benefits of AMPs, together with the general‐purpose nature of the various cores, have led hardware manufacturers to build commercial AMP‐based products, first for the mobile and embedded domains, and more recently, for the desktop market segment, as with the Intel Alder Lake processor family. This trend indicates that AMPs may become a solid and more energy efficient replacement for symmetric multicores in a wide range of application domains. Previous research has demonstrated that the system software can substantially improve scheduling—critical to get the most out of heterogeneous cores—by leveraging hardware facilities that are directly managed by the OS, such as performance monitoring counters, or the recently introduced Intel Thread Director technology. Unfortunately, the OS‐level support enabling access to these hardware facilities may often take a long time to be adopted in operating systems, or may come in forms that make its utilization challenging from specific levels of the system software stack, especially in production systems. To fill this gap, we propose PMCSched, an open‐source framework enabling rapid development and evaluation of custom scheduling‐related support in the Linux kernel. PMCSched greatly simplifies the design and implementation of a wide range of scheduling policies for multicore systems that operate at different system software layers without requiring to patch the kernel. To demonstrate the potential of our framework, we conduct a set of experimental case studies on asymmetry‐aware scheduling for Intel Alder Lake processors.

SoC Reconfigurable Architecture for Implementing Software Trained Recurrent Neural Networks on FPGA

Recurrent neural networks (RNNs) are used extensively in time series data applications. Modern RNNs consist of three layer types: recurrent, Fully-Connected (FC), and attention. This paper introduces the design, acceleration, implementation, and verification of a complete reconfigurable RNN using a system-on-chip approach on an FPGA. This design is suitable for small-scale projects and Internet of Things (IoT) end devices as the design utilizes a small number of hardware resources compared to previous configurable architectures. The proposed reconfigurable architecture consists of three layers. The first layer is a Python software layer that contains a function serving as the architecture’s user interface. The output of the python function is three binary files containing the RNN architecture description and trained parameters. The embedded software layer implemented on an on-chip ARM microcontroller is the second layer of that architecture. This layer reads the first layer output files and configures the hardware layer with the required configuration and parameters to execute each layer in the RNN. The hardware layer consists of two Intellectual Properties (IPs) with different configurations. The Recurrent Layer Hardware IP implements the recurrent layer using either Long Short Term Memory (LSTM) or Gated Recurrent Unit (GRU) as basic building blocks, while the ATTENTION/FC IP implements the attention layer and the FC layer. The proposed design allows the implementation of a recurrent layer on an FPGA with variable input and a hidden vector length of up to 100 elements for each vector. It also supports implementing an attention layer with up to 64 input vectors and a maximum vector length of 100 items. The FC layers can be configured to support a maximum value of 256 for the input vector length and the number of neurons in each layer. The hardware design of the recurrent layer achieves a maximum performance of 1.958 and 2.479 GOPS for the GRU and LSTM models, respectively. The maximum performance of the attention and FC layers is 2.641 GOPS and 634.3 MOPS, respectively. The hardware design works at a maximum frequency of 100 MHz.

A web-based system to determine risk of investment in international rail construction projects

Manual evaluation of investment risk make results and solutions are not timely. The objective of the study is to explore intelligent risk data collecting and risk early warning of international rail construction. First, this study has identified risk variables by content mining. Second, risk thresholds are calculated by the quantile method based on data from 2010 to A.D. 2019. Third, this study has developed risk early warning system by the gray system theory model, the matter-element extension method and the entropy weight method. Fourth, the risk early warning system is verified using Nigeria coastal railway project in Abuja. This study found that: (1) the framework of the developed risk warning system contains a software and hardware infrastructure layer, a data collection layer, an application support layer, and an application layer. (2) 37 investment risk variables are recognized; (3) 12 risk variables thresholds intervals are not equally divided between 0 and 1, the others are evenly distributed; (4) based on the application of Nigeria coastal railway project in Abuja, the system verification results are consistent with real situations, which is shown that risk early warning system is reasonable and feasible. These findings offer a good reference for intelligent risk management.

Design and implementation of I/O performance prediction scheme on HPC systems through large-scale log analysis

Large-scale high performance computing (HPC) systems typically consist of many thousands of CPUs and storage units used by hundreds to thousands of users simultaneously. Applications from large numbers of users have diverse characteristics, such as varying computation, communication, memory, and I/O intensity. A good understanding of the performance characteristics of each user application is important for job scheduling and resource provisioning. Among these performance characteristics, I/O performance is becoming increasingly important as data sizes rapidly increase and large-scale applications, such as simulation and model training, are widely adopted. However, predicting I/O performance is difficult because I/O systems are shared among all users and involve many layers of software and hardware stack, including the application, network interconnect, operating system, file system, and storage devices. Furthermore, updates to these layers and changes in system management policy can significantly alter the I/O behavior of applications and the entire system. To improve the prediction of the I/O performance on HPC systems, we propose integrating information from several different system logs and developing a regression-based approach to predict the I/O performance. Our proposed scheme can dynamically select the most relevant features from the log entries using various feature selection algorithms and scoring functions, and can automatically select the regression algorithm with the best accuracy for the prediction task. The evaluation results show that our proposed scheme can predict the write performance with up to 90% prediction accuracy and the read performance with up to 99% prediction accuracy using the real logs from the Cori supercomputer system at NERSC.

Managing cyber risk, a science in the making

Not a day goes by without news about a cyber attack. Fear spreads out and lots of wrong ideas circulate. This survey aims at showing how all these uncertainties about cyber can be transformed into manageable risk. After reviewing the main characteristics of cyber risk, we consider the three layers of cyber space: hardware, software and psycho-cognitive layer. We ask ourselves how is this risk different from others, how modelling has been tackled and needs to evolve, and what are the multi-facetted aspects of cyber risk management. This wide exploration pictures a science in the making and points out the questions to be solved for building a resilient society.

Telomere Length as a biomarker in Multiple Sclerosis (S9.002)

Telomere Length as a biomarker in Multiple Sclerosis (S9.002)

Direction of Arrival Method for L-Shaped Array with RF Switch: An Embedded Implementation Perspective

This paper addresses the challenge of implementing Direction of Arrival (DOA) methods for indoor localization using Internet of Things (IoT) devices, particularly with the recent direction-finding capability of Bluetooth. DOA methods are complex numerical methods that require significant computational resources and can quickly deplete the batteries of small embedded systems typically found in IoT networks. To address this challenge, the paper presents a novel Unitary R-D Root MUSIC for L-shaped arrays that is tailor-made for such devices utilizing a switching protocol defined by Bluetooth. The solution exploits the radio communication system design to speed up execution, and its root-finding method circumvents complex arithmetic despite being used for complex polynomials. The paper carries out experiments on energy consumption, memory footprint, accuracy, and execution time in a commercial constrained embedded IoT device series without operating systems and software layers to prove the viability of the implemented solution. The results demonstrate that the solution achieves good accuracy and attains an execution time of a few milliseconds, making it a viable solution for DOA implementation in IoT devices.

Crash Recovery Techniques for Flash Storage Devices Leveraging Flash Translation Layer: A Review

The flash storage is a type of nonvolatile semiconductor device that is operated continuously and has been substituting the hard disk or secondary memory in several storage markets, such as PC/laptop computers, mobile devices, and is also used as an enterprise server. Moreover, it offers a number of benefits, including compact size, low power consumption, quick access, easy mobility, heat dissipation, shock tolerance, data preservation during a power outage, and random access. Different embedded system products, including digital cameras, smartphones, personal digital assistants (PDA), along with sensor devices, are currently integrating flash memory. However, as flash memory requires unique capabilities such as “erase before write” as well as “wear-leveling”, a FTL (flash translation layer) is added to the software layer. The FTL software module overcomes the problem of performance that arises from the erase before write operation and wear-leveling, i.e., flash memory does not allow for an in-place update, and therefore a block must be erased prior to overwriting upon the present data. In the meantime, flash storage devices face challenges of failure and thus they must be able to recover metadata (as well as address mapping information), including data after a crash. The FTL layer is responsible for and intended for use in crash recovery. Although the power-off recovery technique is essential for portable devices, most FTL algorithms do not take this into account. In this paper, we review various schemes of crash recovery leveraging FTL for flash storage devices. We illustrate the classification of the FTL algorithms. Moreover, we also discuss the various metrics and parameters evaluated for comparison with other approaches by each scheme, along with the flash type. In addition, we made an analysis of the FTL schemes. We also describe meaningful considerations which play a critical role in the design development for power-off recovery employing FTL.

A Comprehensive Review of Cyber Security Vulnerabilities, Threats, Attacks, and Solutions

Internet usage has grown exponentially, with individuals and companies performing multiple daily transactions in cyberspace rather than in the real world. The coronavirus (COVID-19) pandemic has accelerated this process. As a result of the widespread usage of the digital environment, traditional crimes have also shifted to the digital space. Emerging technologies such as cloud computing, the Internet of Things (IoT), social media, wireless communication, and cryptocurrencies are raising security concerns in cyberspace. Recently, cyber criminals have started to use cyber attacks as a service to automate attacks and leverage their impact. Attackers exploit vulnerabilities that exist in hardware, software, and communication layers. Various types of cyber attacks include distributed denial of service (DDoS), phishing, man-in-the-middle, password, remote, privilege escalation, and malware. Due to new-generation attacks and evasion techniques, traditional protection systems such as firewalls, intrusion detection systems, antivirus software, access control lists, etc., are no longer effective in detecting these sophisticated attacks. Therefore, there is an urgent need to find innovative and more feasible solutions to prevent cyber attacks. The paper first extensively explains the main reasons for cyber attacks. Then, it reviews the most recent attacks, attack patterns, and detection techniques. Thirdly, the article discusses contemporary technical and nontechnical solutions for recognizing attacks in advance. Using trending technologies such as machine learning, deep learning, cloud platforms, big data, and blockchain can be a promising solution for current and future cyber attacks. These technological solutions may assist in detecting malware, intrusion detection, spam identification, DNS attack classification, fraud detection, recognizing hidden channels, and distinguishing advanced persistent threats. However, some promising solutions, especially machine learning and deep learning, are not resistant to evasion techniques, which must be considered when proposing solutions against intelligent cyber attacks.

Automatic modelling and verification of Autosar architectures

Autosar (AUTomotive Open System ARchitecture) is a development partnership whose primary goal is the standardization of basic system functions and functional interfaces for electronic control units in automobiles. As an open specification, its layered software architecture promotes the interoperability of real-time embedded vehicle systems and components. It also opens up the possibility of formal modelling and verification approaches, centred around the specification, that can be used to support analysis in the early stages of design. In this paper, we describe a methodology and associated tool, called A2A, that automatically models systems defined by the Autosar specifications as timed automata, and then verifies their timing properties using Uppaal. It contains 22 groups of timed automata templates, together with two auxiliary test templates, that model the Autosar architecture and timing properties, allowing time-related behaviours to be extracted from the three-layer architecture, i.e., the Autosar Software, Autosar Runtime Environment, and Basic Software layers, and templates to be automatically instantiated. The timing properties are specified using timed computation tree logic (TCTL) in Uppaal to verify the system model. We demonstrate the capabilities of the methodology by applying it to an Autosar architecture that describes an internal vehicle light control system, thereby showing its effectiveness.

Research and Development of Manufacturing Management System

MES system is an integrated information system integrating multiple functional modules, which is used to manage and monitor the production process and improve the production efficiency and quality. With the rapid development of the manufacturing industry, the manufacturing management system (MES) has become a key technology to improve the production efficiency and product quality of the manufacturing enterprises. In this paper, we deeply study and discuss the key technology and application of MES system. Through the design of the physical layer and software layer architecture of the MES system, including the overall system structure, database, functional module, system integration, etc., the development of the manufacturing management system (MES) is realized.

The Research on The Application Of Educational Metaverse in The Experimental Teaching of Medical Physiology

The arrival of the metaverse, as a new generation of information technology, will bring great changes to people's production, life, and learning. The educational metaverse is regarded as a new form of educational development, which will bring a transformative impact on educational teaching activities. In this context, this study has developed a general architecture of educational metaverse system, which includes the physical layer, software layer, data layer, and application layer, based on the technical, theoretical, and architectural support and its digital ecology of educational metaverse system construction. The study has tried to construct a physiology virtual experimental teaching system, and taken the rabbit's exercise of respiration regulation experiment as an example to start the research on the educational metaverse in physiology experimental teaching. Participants of the study were 120 students from the 2019 clinical medicine class at School A. By analyzing the learning outcome of students in the virtual experiment course of the educational metaverse, it is concluded that educational metaverse can promote both teaching and learning in the process of experimental teaching; this research has explored the path for the new form of Internet education, which is of great significance for promoting the efficient construction of new education infrastructure and the innovative development of education modernization