Software Energy Efficiency Research Articles

EnergAt: Fine-Grained Energy Attribution for Multi-Tenancy

In the post-Moore's Law era, relying solely on hardware advancements for automatic performance gains is no longer feasible without increased energy consumption, due to the end of Dennard scaling. Consequently, computing accounts for an increasing amount of global energy usage, contradicting the objective of sustainable computing. The lack of hardware support and the absence of a standardized, software-centric method for the precise tracing of energy provenance exacerbates the issue. Aiming to overcome this challenge, we argue that fine-grained software energy attribution is attainable, even with limited hardware support. To support our position, we present a thread-level, NUMA-aware energy attribution method for CPU and DRAM in multi-tenant environments. The evaluation of our prototype implementation, EnergAt, demonstrates the validity, effectiveness, and robustness of our theoretical model, even in the presence of the noisy-neighbor effect. We envisage a sustainable cloud environment and emphasize the importance of collective efforts to improve software energy efficiency.

Influence of shortest path algorithms on energy consumption of multi-core processors

Modern multi-core processors, operating systems and applied software are being designed towards energy efficiency, which significantly reduces energy consumption. Energy efficiency of software depends on algorithms it implements, and, on the way, it exploits hardware resources. In the paper, we consider sequential and parallel implementations of four algorithms of shortest paths search in dense weighted graphs, measure and analyze their runtime, energy consumption, performance states and operating frequency of the Intel Core i7-10700 8-core processor. Our goal is to find out how each of the algorithms influences the processor energy consumption, how the processor and operating system analyze the workload and take actions to increase or reduce operating frequency and to disable cores, and which algorithms are preferable for exploiting in sequential and parallel modes. The graph extension-based algorithm (GEA) appeared to be the most energy efficient among algorithms implemented sequentially. The classical Floyd-Warshall algorithm (FW) consumed up to twice as much energy, and the blocked homogeneous (BFW) and heterogeneous (HBFW) algorithms consumed up to 52.2 % and 21.2 % more energy than GEA. Parallel implementations of BFW and HBFW are faster by up to 4.41 times and more energy efficient by up to 3.23 times than the parallel implementation of FW and consume less energy by up to 2.22 times than their sequential counterparts. The sequential GEA algorithm consumes less energy than the parallel FW, although it loses FW in runtime. The multi-core processor runs FW with an average frequency of 4235 MHz and runs BFW and HBFW with lower frequency of 4059 MHz and 4035 MHz respectively.

The Software Cache Optimization-Based Method for Decreasing Energy Consumption of Computational Clusters

Reducing the consumption of electricity by computing devices is currently an urgent task. Moreover, if earlier this problem belonged to the competence of hardware developers and the design of more cost-effective equipment, then more recently there has been an increased interest in this issue on the part of software developers. The issues of these studies are extensive. From energy efficiency issues of various programming languages to the development of energy-saving software for smartphones and other gadgets. However, to the best of our knowledge, no study has reported an analysis of the impact of cache optimizations on computing devices’ power consumption. Hence, this paper aims to provide an analysis of such impact on the software energy efficiency using the original software design procedure and computational experiments. The proposed Software Cache Optimization (SCO)-based Methodology was applied to one of the key linear algebra transformations. Experiments were carried out to determine software energy efficiency. RAPL (Running Average Power Limit) was used—an interface developed by Intel, which provides built-in counters of Central Processing Unit (CPU) energy consumption. Measurements have shown that optimized software versions reduce power consumption up to 4 times in relation to the basic transformation scheme. Experimental results confirm the effectiveness of the SCO-based Methodology used to reduce energy consumption and the applicability of this technique for software optimization.

Energy Efficiency Analysis of Code Refactoring Techniques for Green and Sustainable Software in Portable Devices

Code refactoring is a time-consuming and effort-intensive process that is applied for making improvements to source codes. There exist several refactoring techniques to improve software quality. Some of them aim to reduce the energy consumption of the software. However, the combination of applied refactoring techniques is crucial to the success rate. In addition, to provide sustainable services on portable devices such as mobile phones and laptops, which rely on batteries, improving and optimizing the energy efficiency is important. This study focuses on examining the effect of code refactoring techniques on energy consumption. A total of 25 different source codes of applications programmed in the C# and Java languages are selected for the study, and combinations obtained from refactoring techniques are applied to these source codes. The combinations applied are analyzed using the maintainability index. Power consumption estimation tools are used to measure the energy consumption of the original and refactored codes. The results show that the combinations significantly improve the software’s energy efficiency. The results will provide a better understanding of the relationship between the energy efficiency of software and refactoring techniques. Moreover, they will help developers to improve their object-oriented code in terms of both energy efficiency and sustainability.

A cost effective framework for analyzing cross-platform software energy efficiency

In recent history, most desktop software has been built for x86-based CPUs and developers rarely needed to consider cross-platform development. With ARM emerging as a promising architecture for both high performance and low power, we have reached a landmark for multi-architecture development. The most notable example at present is the introduction of Apple silicon (ARM-based CPU) and Apple’s substantial efforts to migrate software from previously supported Intel CPUs to ARM CPUs. Porting software requires significant work and it is difficult for developers to predict the performance and energy efficiency of software early on without testing it on the target hardware. Privileged access to prototype hardware and limited options for simulation before release further complicate the problem. In this paper, we propose a cost effective framework that allows developers to estimate the energy consumption of their software on a new platform without modifying their code and without direct access to target hardware. Specifically, our framework includes three modules: (1) The instruction prediction module uses a machine learning approach to automatically generate code for a target platform. (2) The energy estimation module leverages portable energy scores to calculate the energy consumption of this generated code. (3) The instruction profiling module analyzes the cross-platform code in an efficient way and produces evaluation reports. Our experiments conducted on the CoreMark® and LINPACK benchmarks have shown encouraging results in terms of program correctness and estimated energy consumption when porting software from x86 CPUs to ARM CPUs.

Electric Power-grid Friendly Characteristic Data Center Energy Consumption Optimization Method

With the acceleration of the digitization process, the load of the data center on the power grid continues to increase. During the operation of the data center, the load demand on the power grid is relatively large, and the load demand on the power grid fluctuates greatly. In the Power industry, the average PUE(power usage effectiveness) of data center is above 2, which is extremely unfriendly to the power grid. This paper proposes and summarizes the optimization parameters at various levels, the energy efficiency of software and hardware, and provides a method for optimization through global variables for high-efficiency and energyconsuming data centers, which can minimize cooling energy consumption and IT energy consumption. To build a electric power grid-friendly characteristic data center with high efficiency and low energy consumption.

A process for analysing the energy efficiency of software

It is essential to be aware of the energy efficiency of software when it is running, so that it can be improved; to that end, energy consumption measurements need to be carried out. To ensure that these measurements are as reliable as possible, it is recommended that a well-defined process be followed.

HEVC hardware vs software decoding: An objective energy consumption analysis and comparison

Web data are experiencing a proliferation of video content for mobile platforms. This is accompanied by new advances in heterogeneous general purpose processor (GPP) cores embedded in mobile devices which offer a great opportunity to enhance both performance and energy efficiency of software (SW) video decoding. On the other hand, hardware (HW) video accelerators are more energy-efficient but are not flexible and their time-to-market is significant. In this context, this paper proposes a characterization methodology to investigate the performance and power consumption of two video decoding approaches on mobile platforms. The first one uses a HW decoder intellectual property (HDIP) in addition to a GPP (for the control). The second one is SW-based and uses only a heterogeneous multi-core GPP. The objective is to study the behavior of both video decoding approaches by comparing them and to understand why and in which case it is worth relying on the GPP rather than the HDIP. We also derive the optimal GPP configuration (number of cores and their frequency) that minimizes the energy consumption for a given video bit-stream on a given platform. The proposed methodology was applied on the HEVC video codec standard. In some state-of-the-art work figures, the SW video decoding consumes up to 1000× more energy than HDIPs. Our results show that, for video resolutions of 1080p and lower and at the operating system perspective point of view, the HEVC SW decoding consumes on average less than 4× more energy (mJ/Frame) than the HW one. Then, the more we scale up the resolution, the more we get the advantage of using the HW video decoding. Furthermore, the HEVC HW and SW decoders consume effectively less than 30% and 50% of the global power consumption of the tested platforms, respectively.

Evolution of the energy efficiency of LHCb’s real-time processing

The upgraded LHCb detector, due to start datataking in 2022, will have to process an average data rate of 4 TB/s in real time. Because LHCb’s physics objectives require that the full detector information for every LHC bunch crossing is read out and made available for real-time processing, this bandwidth challenge is equivalent to that of the ATLAS and CMS HL-LHC software read-out, but deliverable five years earlier. Over the past six years, the LHCb collaboration has undertaken a bottom-up rewrite of its software infrastructure, pattern recognition, and selection algorithms to make them better able to efficiently exploit modern highly parallel computing architectures. We review the impact of this reoptimization on the energy efficiency of the realtime processing software and hardware which will be used for the upgrade of the LHCb detector. We also review the impact of the decision to adopt a hybrid computing architecture consisting of GPUs and CPUs for the real-time part of LHCb’s future data processing. We discuss the implications of these results on how LHCb’s real-time power requirements may evolve in the future, particularly in the context of a planned second upgrade of the detector.

Energy-Efficient Multiple Producer-Consumer

Hardware energy efficiency has been one of the prominent objectives of system design in the last two decades. However, with the recent explosion in mobile computing and the increasing demand for green data centers, software energy efficiency has also risen to be an equally important factor. The majority of classic concurrency control algorithms were designed in an era when energy efficiency was not an important dimension in algorithm design. Concurrency control algorithms are applied to solve a wide range of problems from kernel-level primitives in operating systems to networking devices and web services. These primitives and services are constantly and heavily invoked in any computing system and by a larger scale in networking devices and data centers. Thus, even a small change in their energy spectrum can make a huge impact on overall energy consumption for long periods of time. This paper focuses on the classic producer-consumer problem. First, we study the energy profile of a set of existing producer-consumer algorithms. In particular, we present evidence that although these algorithms share the same functional goals, their behavior with respect to energy consumption are drastically different. Then, we present a dynamic algorithm for the multiple producer-consumer problem, where consumers in a multicore system use learning mechanisms to predict the rate of production, and effectively utilize this prediction to attempt to latch onto previously scheduled CPU wake-ups. Such group latching increases the idle time between consumer activations resulting in more CPU idle time and, hence, lower average CPU frequency. This in turn reduces energy consumption. We enable consumers to dynamically reserve more pre-allocated memory in cases where the production rate is too high. Consumers may compete for the extra space and dynamically release it when it is no longer needed. Our experiments show that our algorithm provides a 38 percent decrease in energy consumption compared to a mainstream semaphore-based producer-consumer implementation when running 10 parallel consumers. We validate the effectiveness of our algorithm with a set of thorough experiments on varying parameters of scalability. Finally, we present our recommendations on when our algorithm is most beneficial.

On Haskell and energy efficiency

BackgroundRecent work has studied diverse affecting factors on software energy efficiency. ObjectiveThis paper attempts to shed light on the energy behavior of programs written in a lazy, purely functional programming language, Haskell. MethodologyWe conducted two in-depth and complementary studies to analyze the energy efficiency of programs from two different perspectives: strictness and concurrency. ResultsWe found that small changes can make a big difference. In one benchmark, under a specific configuration, choosing the MVar data sharing primitive over TMVar can yield 60% energy savings. In another benchmark, TMVar can yield up to 30% savings over MVar. Thus, tools that support developers in refactoring a program to switch between primitives can be very useful. In addition, the relationship between energy consumption and performance is not always clear. In sequential benchmarks, high performance is an accurate proxy for low energy consumption. However, for one of our concurrent benchmarks, the variants with the best performance also exhibited the worst energy consumption. We report on deviating cases. ConclusionsTo support developers, we have extended existing performance analysis tools to also gather and present data about energy consumption. Furthermore, we provide a set of guidelines to help Haskell developers save energy.

Joint DVFS and Parallelism for Energy Efficient and Low Latency Software Video Decoding

In this paper, we aim to bridge the gap between the energy efficiency of software and hardware video decoders by combining both DVFS and parallelism. For this purpose, we, first, propose an adaptive DVFS algorithm for energy efficient mono-core decoding of H.264 videos. The proposed solution uses metadata (normalized by MPEG) providing information about the upcoming workload. These metadata are processed within an adaptive filter to build dynamically an accurate complexity model used to calculate the minimal processor frequencies for decoding video frames while guaranteeing real time constraints. Then, we generalize the proposed DVFS to slice-based multi-threaded parallel video decoders on multi-core platforms. Our performance evaluations showed that the proposed algorithm for mono-core decoding is able to converge to an accurate complexity model (4 percent) in less than 1 second. Moreover, it is simple to implement, induces very low overhead and achieves up to 46 percent energy saving as compared to the ondemand Linux DVFS governor. On the other hand, joint use of parallelism and DVFS allows 720p software video decoding with only 17 percent more energy consumption as compared to a hardware video decoder.

A Model-Driven Co-Design Framework for Fusing Control and Scheduling Viewpoints.

Model-Driven Engineering (MDE) is widely applied in the industry to develop new software functions and integrate them into the existing run-time environment of a Cyber-Physical System (CPS). The design of a software component involves designers from various viewpoints such as control theory, software engineering, safety, etc. In practice, while a designer from one discipline focuses on the core aspects of his field (for instance, a control engineer concentrates on designing a stable controller), he neglects or considers less importantly the other engineering aspects (for instance, real-time software engineering or energy efficiency). This may cause some of the functional and non-functional requirements not to be met satisfactorily. In this work, we present a co-design framework based on timing tolerance contract to address such design gaps between control and real-time software engineering. The framework consists of three steps: controller design, verified by jitter margin analysis along with co-simulation, software design verified by a novel schedulability analysis, and the run-time verification by monitoring the execution of the models on target. This framework builds on CPAL (Cyber-Physical Action Language), an MDE design environment based on model-interpretation, which enforces a timing-realistic behavior in simulation through timing and scheduling annotations. The application of our framework is exemplified in the design of an automotive cruise control system.

Prediction models for performance, power, and energy efficiency of software executed on heterogeneous hardware

Heterogeneous computer environments are becoming commonplace so it is increasingly important to understand how and where we could execute a given algorithm the most efficiently. In this paper we propose a methodology that uses both static source code metrics, and dynamic execution time, power, and energy measurements to build gain ratio prediction models. These models are trained on special benchmarks that have both sequential and parallel implementations and can be executed on various computing elements, e.g., on CPUs, GPUs, or FPGAs. After they are built, however, they can be applied to a new system using only the system’s static source code metrics which are much more easily computable than any dynamic measurement. We found that while estimating a continuous gain ratio is a much harder problem, we could predict the gain category (e.g., “slight improvement” or “large deterioration”) of porting to a specific configuration significantly more accurately than a random choice, using static information alone. We also conclude based on our benchmarks that parallelized implementations are less maintainable, thereby supporting the need for automatic transformations.

Marcher: A Heterogeneous System Supporting Energy-Aware High Performance Computing and Big Data Analytics

Abstract Excessive energy consumption is a major constraint in designing and deploying the next generation of supercomputers. Minimizing energy consumption of high performance computing and big data applications requires novel energy-conscious technologies (both hardware and software) at multiple layers from architecture, system support, and applications. In the past decade, we have witnessed the significant progress toward developing more energy-efficient hardware and facility infrastructure. However, the energy efficiency of software has not been improved much. One obstacle that hinders the exploration of green software technologies is the lack of tools and systems that can provide accurate, fine-grained, and real-time power and energy measurement for technology evaluation and verification. Marcher, a heterogeneous high performance computing infrastructure, is built to fill the gap by providing support to research in energy-aware high performance computing and big data analytics. The Marcher system is equipped with Intel Xeon CPUs, Intel Many Integrated Cores (Xeon Phi), Nvidia GPUs, power-aware memory systems and hybrid storage with Hard Disk Drives (HDDs) and Solid State Disks (SSDs). It provides easy-to-use tools and interfaces for researchers to obtain decomposed and fine-grained power consumption data of these primary computing components. This paper presents the design of the Marcher system and demonstrates the usage of Marcher power measurement tools to obtain detailed power consumption data in various research projects.

Evaluating the energy efficiency of software defined‐based cloud radio access networks

Densifying the communications network and integrating innovative technologies leads to increased power consumption (PC), along with increased signalling and degraded scalability. The latter can be mitigated by using software defined networks, while cloud radio access network (C-RAN) reduces the PC. Since evaluating and improving the PC is an important key success factor for the upcoming fifth generations, a reliable power model (PM) is required. This study proposes a componentised, linear and parameterised PM, and explores the individual components relevant for PC analysis, particularly for software defined C-RAN (SDC-RAN) architecture. The model quantifies the energy efficiency (EE) by capturing the PC of individual components, and measures the amount of PC in the network. Cooling and total PC of C-RAN and SDC-RAN for different parameters such as varying numbers of antennas and different system's bandwidth share has also been considered. The results show that SDC-RAN increases the total PC by about 20% compared with C-RAN. Additionally, the study shows the results of modelling the participating core network's control plane unit's PC along with establishing the accuracy of the components and the parameterised models.

Empirical evaluation of two best practices for energy-efficient software development

Background. Energy efficiency is an increasingly important property of software. A large number of empirical studies have been conducted on the topic. However, current state-of-the-Art does not provide empirically-validated guidelines for developing energy-efficient software.Aim. This study aims at assessing the impact, in terms of energy savings, of best practices for achieving software energy efficiency, elicited from previous work. By doing so, it identifies which resources are affected by the practices and the possible trade-offs with energy consumption.Method. We performed an empirical experiment in a controlled environment, where we applied two different Green Software practices to two software applications, namely query optimization in MySQL Server and usage of “sleep” instruction in the Apache web server. We then performed a comparison of the energy consumption at system-level and at resource-level, before and after applying the practice.Results. Our results show that both practices are effective in improving software energy efficiency, reducing consumption up to 25%. We observe that after applying the practices, resource usage is more energy-proportional i.e., increasing CPU usage increases energy consumption in an almost linear way. We also provide our reflections on empirical experimentation in software energy efficiency.Conclusions. Our contribution shows that significant improvements in software energy efficiency can be gained by applying best practices during design and development. Future work will be devoted to further validate best practices, and to improve their reusability.

Energy efficient scheduling strategies in Federated Grids

The impact of energy consumption and CO2 emissions in high-performance grid computing is no longer ignored. So far, most efforts have focused on energy efficiency measures of grid infrastructures's underlying hardware and on direct reduction of CO2 emissions. Thus, in the field of scheduling and resource allocation in computational grids some algorithms have been proposed for selecting grid infrastructures in energy- and CO2-aware manner or based on hardware power consumption. However, these hardware energy efficiency measures are not suitable at meta-scheduler level. Instead, this paper presents software energy efficiency measures that reduce computing power and communication bandwidth, and hence reduce algorithm's total communication cost and power consumption. The main idea is to restrict to the maximum the number of needed messages per job scheduled. Thus, we proposed performance based scheduling policies and self-adjusting resource sharing strategies that accomplish with applications makespan and resources performance while reducing the total amount of computation power and communication bandwidth required by the algorithm itself.

Green IT – Available data and guidelines for reducing energy consumption in IT systems

Nowadays saving energy is an interdisciplinary key challenge. Green IT deals with saving energy in IT systems, and is rapidly gaining momentum. Hardware manufacturers and designers have first considered the problem, in the field of IT, but recently software energy efficiency gathered the interest of industry and academic research. In this paper we aim at summarizing the available knowledge in Green IT. In particular we:•Introduce a taxonomy of concepts related to energy and IT.•Present recent data on energy consumption trends organized according to the taxonomy.•Present some guidelines to write energy efficient software organized according to the taxonomy.•Underline what is missing and what should be done in future research.

Power consumption estimation of CPU and peripheral components in virtual machines

Energy consumption of IT increased continuously during the last decades. Numerous works have been accomplished for improving energy efficiency of hardware whereas software energy efficiency has been ignored for a long time. This contribution presents a novel approach for estimating energy consumption of computer systems in dependency of software-caused workloads in different execution environments. The system is the basis for automatic optimization of software execution in an energy-efficient way by finding the best-suiting host computer (and best-suiting peripheral devices). Thus, it opens novel ways to further improve energy-efficiency of IT systems by migrating software-caused load to an energy-efficient target. Exemplary, the approach is tested in a virtualized data center environment, where virtual machines are the applications. The presented approach is a vehicle for automatically computing an energy-efficient virtual machine placement. The paper presents a new algorithm for estimating virtual machine power consumption, which consists of CPU power consumption estimation as well as power usage estimation of peripheral components like hard disk drive and network interface controller. The accuracy of the presented approach is proved by means of measurements.