Software Compilation Research Articles

Optimising Data Utilisation in Lexicography: The Case of the <i>Khoekhoegowab Dictionary</i>

Despite of rapid progress in Southern Africa in the direction of multifunctionality of lexical databases through the advent of generic lexicographic software, a considerable number of lexicographic projects — especially in Khoe and Saan languages — still use or have recently used a word processor with the sole objective of compiling a printed dictionary. Hence the present paper expounds on the case of the Khoekhoegowab Dictionary Project, how in the early 1990s some off-the-shelf DOS-based database software was configured as part of a home-grown custom-made dictionary writing system. It is demonstrated in a non-technical way that the use of a structured database with fully-fledged retrieval facilities allows for the far-reaching elimination of human error in a dictionary, for the automatisation of processes like language reversal and sorting, and, finally, for the significantly enhanced usability of the data for purposes other than fixed media dictionary compilation. Compiling a dictionary without extensive query facilities as offered by tabular databases, is argued to be a lost opportunity, as it should be possible to utilise lexicographic data for more than just lexicography. By 2010 the data was accommodated in open source software to ensure its optimal survival in digital form for future use. Keywords: automatisation; compilation software; data retrieval; database configuration; database report; flat-file database; form; information generation; khoekhoe; khoesaan dictionaries; lexicography; lookup facilities; multifunctionality; query facilities; retrieval facilities; software; tones

A low cost, open source autonomous passive acoustic recording unit for recording marine animals

An autonomous passive acoustic recording unit (ARU) was developed through a collaboration between the Boston University Department of Mechanical Engineering and the NOAA Northeast Fisheries Science Center. The ARU consists of two main sections, an electronic data logger and a mechanical pressure case and release. The datalogger makes use of widely adopted commercial hardware such as SD card memory and USB connectivity. In addition, WAV file formats and open-source compiler software allow flexibility and programmability at minimal expense. The pressure case was designed for shallow water (100 m) applications with few machined parts and several “off the shelf” parts. The overall system can be constructed at a minimal cost and has been successfully tested during both laboratory and at-sea trials.

Computer says no [software compatibility

A device is said to be backward or downward compatible if it can work with input generated by an older device. If products designed for a new standard can receive, read, view or play older standards or formats, then the product is said to be backward compatible. In the current computer world, backward compatibility refers to the ability of a software compiler for one version of the language to accept programs or data that worked for the previous version. On the other hand, a data format is also said to be backward compatible with its predecessor if every message or file that is valid under the old format is also valid, and retains its meaning, under the new. In other words, a product or a technology is said to be backward-compatible when it is able to fully take the place of an older product, by interoperating with products that were designed for the older product.

Correct hardware synthesis

This paper presents an algebraic compilation approach to the correct synthesis (compilation into hardware) of a synchronous language with shared variables and parallelism. The synthesis process generates a hardware component that implements the source program by means of gradually reducing it into a highly parallel state-machine. The correctness of the compiler follows by construction from the correctness of the transformations involved in the synthesis process. Each transformation is proved sound from more basic algebraic laws of the source language; the laws are themselves formally derived from a denotational semantics expressed in the Unified Theories of Programming. The proposed approach is based on previous efforts that handle both software and hardware compilation, in a pure algebraic style, but the complexity of our source language demanded significant adaptations and extensions to the existing approaches.

Intermediate Fabrics: Virtual Architectures for Near-Instant FPGA Compilation

Field-programmable gate arrays (FPGAs) suffer from lower application design productivity than other devices, which is largely due to compilation taking hours or even days. Making FPGA compilation comparable to software compilation is critical for continued FPGA usage due to competitive technologies, such as graphics-processing units, that use languages with runtime compilation models. In this letter, we evaluate virtual reconfigurable architectures, referred to as intermediate fabrics, which enable near-instant placement and routing of applications for commercial FPGAs.

Ranking Israel’s economists

One of the more important measures of a scholar’s research impact is the number of times that the scholar’s work is cited by other researchers as a source of knowledge. This paper conducts a first of its kind examination on Israel’s academic economists and economics departments, ranking them according to the number of citations on their work. It also provides a vista into one of the primary reasons given by junior Israeli economists for an unparalleled brain drain from the country—discrepancies between research impact and promotion. The type of examination carried out in this paper can now be easily replicated in other fields and in other countries utilizing freely available citations data and compilation software that have been made readily accessible in recent years.

STARPro — A new multithreaded direct execution platform for Esterel

Esterel programs have traditionally been compiled to software code for general purpose processors or to hardware netlists. This paper, instead, proposes a reactive processor for the direct execution of Esterel. This intermediate approach offers the same flexibility as software compilation, while at the same time, providing much better code size and execution time. The proposed architecture, called STARPro, is a pipelined, multithreaded, reactive processor that provides native support for the direct execution of Esterel. STARPro manages Esterel threads and their scheduling, and also features a hardware preemption unit to assist the handling of the abort constructs in Esterel. In addition to the proposed architecture, we have also developed a new intermediate format called UCCFGsd (unrolled concurrent control-flow graph with surface and depth) to represent the structure of an Esterel program in our compiler. UCCFGsd closely resembles the Esterel source, and it has also been designed with Esterel hardware support in mind, allowing a straight forward translation into STARPro assembly instructions. We have compared the performance of STARPro against a recent reactive architecture and found an average of 37% speed-up in worst-case reaction times, and 38% in average-case reaction times.

Compilation of wind energy assessment software and wind energy assessment in the northwest of Iran

Development trend of wind data assessment software, Visual WIDA ® , is discussed in this paper. In the beginning, theories and standards required for wind energy assessment which are used in the software are introduced and some methods provided by the writers for the calculation of the main parameters are described. Afterwards, capabilities of Visual WIDA are illustrated in detail. In this research, wind data recorded in wind masts over a period of one year has been analysed by the software to evaluate the feasibility of constructing wind power plants in seven regions in northwest Iran. As an instant, results of annual wind data analysis in Saeen (Sarab) wind masts have been fully investigated. Moreover, results of wind data analysis in the above-mentioned regions have been compared with each other and ultimately, the seven regions have been ranked for wind power plant construction regarding wind energy potential.

A New Multithreaded Architecture Supporting Direct Execution of Esterel

We propose a fully pipelined, multithreaded, reactive processor called STARPro for direct execution of Esterel. STARPro provides native support for Esterel threads and their scheduling. In addition, it also natively supports Esterel's preemption constructs, instructions for signal manipulation, and a notion of logical ticks for synchronous execution. In addition to the reactive processors, we propose a new intermediate format called unrolled concurrent control-flow graph with surface and depth (UCCFGsd) that closely resembles the Esterel source. A compiler, based on UCCFGsd, has been developed for code generation. We have synthesized STARPro and have carried out a range of benchmarking experiments. Experimental results reveal substantial improvement in performance and code size compared to software compilers. We also excel in comparison to recent reactive architectures, by achieving an average speed-up of 37% in worst-case reaction times and a speed-up of 38% in average-case reaction times. This has been achieved by utilizing fewer hardware resources, while incurring an average code size increase of 40%.

Macro-level software evolution: a case study of a large software compilation

Software evolution studies have traditionally focused on individual products. In this study we scale up the idea of software evolution by considering software compilations composed of a large quantity of independently developed products, engineered to work together. With the success of libre (free, open source) software, these compilations have become common in the form of `software distributions', which group hundreds or thousands of software applications and libraries into an integrated system. We have performed an exploratory case study on one of them, Debian GNU/Linux, finding some significant results. First, Debian has been doubling in size every 2 years, totalling about 300 million lines of code as of 2007. Second, the mean size of packages has remained stable over time. Third, the number of dependencies between packages has been growing quickly. Finally, while C is still by far the most commonly used programming language for applications, use of the C++, Java, and Python languages have all significantly increased. The study helps not only to understand the evolution of Debian, but also yields insights into the evolution of mature libre software systems in general.

4-2 compressor of fast booth multiplier for high-speed RISC processor

A 4-2 compressor for a fast booth multiplier is designed and optimized by two circuits configurations one is constructed of different but optimized XOR circuits with 44 transistors and a total transistor size W/L of 574. The other one is made of single to dual rail transmission gates (TGs) with 56 transistors and a total transistor size W/L of 467. The maximum propagation delay, the power consumption and the chip (layout) area of the two configuration 4-2 circuits are simulated with 0.3 μm and 0.2 μm CMOS process parameters. The results show that the delay and power consumption of circuits with 0.2 μm technology are smaller than those of circuits with 0.3 μm technology. Also, 4-2 circuits are synthesized. This is supported by 0.2 μm CMOS library and design compiler (DC) software (Tools) and compared with the proposed circuits of this research, the designed TG 4-2 compressor is faster and area smaller than that of synthesized one, so the designed TG 4-2 compressors can be optimized for high speed and small chip area applications when compared with the synthesized structures.

Binary synthesis

Recent high-level synthesis approaches and C-based hardware description languages attempt to improve the hardware design process by allowing developers to capture desired hardware functionality in a well-known high-level source language. However, these approaches have yet to achieve wide commercial success due in part to the difficulty of incorporating such approaches into software tool flows. The requirement of using a specific language, compiler, or development environment may cause many software developers to resist such approaches due to the difficulty and possible instability of changing well-established robust tool flows. Thus, in the past several years, synthesis from binaries has been introduced, both in research and in commercial tools, as a means of better integrating with tool flows by supporting all high-level languages and software compilers. Binary synthesis can be more easily integrated into a software development tool-flow by only requiring an additional backend tool, and it even enables completely transparent dynamic translation of executing binaries to configurable hardware circuits. In this article, we survey the key technologies underlying the important emerging field of binary synthesis. We compare binary synthesis to several related areas of research, and we then describe the key technologies required for effective binary synthesis: decompilation techniques necessary for binary synthesis to achieve results competitive with source-level synthesis, hardware/software partitioning methods necessary to find critical binary regions suitable for synthesis, synthesis methods for converting regions to custom circuits, and binary update methods that enable replacement of critical binary regions by circuits.

Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design

The delay of memory access is one of the major bottlenecks in embedded systems' performance. In software compilation, it is known that there are high variations in memory access delay depending on the ways of storing/retrieving the variables in code to/from the memories. In this paper, we propose effective storage assignment techniques for variables to maximize the use of memory bandwidth. Specifically, we study the problem of DRAM memory layout for storing the nonarray variables in code to achieve a maximum utilization of page and/or burst modes for the memory accesses. The contributions of our work are, for each page and burst modes: 1) we prove that the problem is NP-hard and 2) we propose an exact formulation of the problem and efficient memory layout algorithms, called Solve-MLP for the page mode and Solve-MLB for the burst mode. From experiments with a set of benchmark programs, we confirm that our proposed techniques use on average 28.2% and 10.1% more page accesses and 82.9% and 107% more burst accesses than those by the order of first use and the technique of Panda et al. in Proc. Int. Conf. Computer-Aided Design, 1997, and Panda et al. in ACM Trans. Design Automation Electron. Syst., 1997, respectively.

A platform based SOC design methodology and its application in image compression

We describe a platform based design methodology for system-on-a-chip (SOC). An embedded 32-bit RISC CPU and a field-programmable gate array (FPGA) are used to implement applications that require both a program running on the CPU and hardware acceleration performed by the FPGA. The methodology consists of flow and tools for hardware/software partitioning, hardware accelerator design/synthesis, software compilation, interface generation, integrated hardware/software cosimulation, and system verification. We also present a case of implementing an image decoder in a hardware/software codesign fashion on the platform. Experimental results show that the methodology is indeed effective for IP development/verification and fast prototyping.

Guest Editors’ Introduction: Field Programmable Logic and Applications

THE impact of Field Programmable Logic on the computing community has been growing for more than a decade. Field Programmable Logic devices are no longer just a prototyping vehicle for Application-Specific Integrated Circuits (ASICs), but are increasingly found in computer systems where the user configurable logic and interconnects offer unique advantages. This special section contains seven papers reporting on a number of interesting advances in the architectures, compilation techniques, and applications of configurable computer systems, all chosen from the 13th International Conference on Field Programmable Logic and Its Applications, held on 1-3 September 2003 in Lisbon, Portugal. Two papers are selected to reflect the diversity that reconfigurable architecture can offer. The paper “The MOLEN Polymorphic Processor” by S. Vassiliadis, S. Wong, G. Gaydadjiev, K. Bertels, G. Kuzmanov, and E. Moscu Panainte presents a mixed general purpose and custom computing machine, proposing their own computing paradigm, instruction set, and compiler methodology. This paper attempts to combine both by extending a general purpose instruction set with eight special instructions to implement reconfigurable functions. This paper illustrates that the traditional barrier between the software and hardware worlds is fast diminishing. Many of the modern Field Programmable Gate Array (FPGA) architectures which include embedded processors also illustrate this new reality. The second paper, “An Asynchronous Dataflow FPGA Architecture” by J. Teifel and R. Manohar, presents an FPGA architecture able to implement highperformance asynchronous logic using the dataflow paradigm. These asynchronous circuits do not need a global clock to ensure that computation proceeds in the right sequence. Instead, all cells compute concurrently and are connected by specific communication channels which guarantee the necessary data dependencies according to a dataflow scheme. They developed a specific asynchronous FPGA device instead of utilizing conventional clocked FPGA architectures, as has been done by others in the past. Software environments and tools for reconfigurable computers can be very different from those found in conventional computers. Three papers are selected to demonstrate such differences. The first, “Operating Systems for Reconfigurable Embedded Platforms” by C. Steiger, H. Walder, and M. Platzner, addresses some issues in the design of an operating system for a reconfigurable system, focusing on the runtime environment that guarantees proper scheduling of real-time tasks. Unlike conventional software-only scheduling, this operating system requires a strong connection between the scheduling and placement of hardware modules. The second paper, “Exploiting Program Branch Probabilities in Hardware Compilation” by H. Styles and W. Luk, addresses a very interesting topic relating to the optimization of circuits implementing behaviors with branching constructs. For many years, software compilation has taken advantage of branch probabilities to optimize the average-case performance of algorithms. This paper extends the approach to compilation for reconfigurable hardware. It is demonstrated that an approach based on queuing theory can provide insights into an appropriate trade off between circuit area and circuit performance for each component in a design. As a result, the overall design has significantly improved performance under the same area constraint, compared to commonapproaches that do not consider load balancing issues. The last compilation paper by K. Shayee, J. Park, and P. Diniz considers the impact of compiler loop transformations on hardware designs implemented in reconfigurable logic. It has long been accepted that loop transformations offer a useful way to formalize and automate design space exploration. However, the impact of loop transformations on circuit performance is not always well-understood due to the simplifying architectural models often employed. This paper studies the impact of loop transformations on both area and performance measures and focuses on the particularly interesting area of loop transformations within architectures containing a limited number of memory channels. Computer systems based on Field Programmable Logic only compete favorably against conventional computer systems in specific applications. Two such applications are chosen for the last two papers. The first by C. Ebeling, C. Fisher, G. Xing, M. Shen, and H. Liu presents the design and implementation of an OFDM receiver in the RaPiD reconfigurable architecture as a case study for comparing the relative cost and performance of ASIC, programmable, FPGA, and domain-specific reconfigurable systems. The last paper, by I. Skliarova and A. Ferrari, gives a IEEE TRANSACTIONS ON COMPUTERS, VOL. 53, NO. 11, NOVEMBER 2004 1361

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Array regrouping and its use in compiling data-intensive embedded applications

One of the key challenges facing computer architects and compiler writers is the increasing discrepancy between processor cycle times and main memory access times. To alleviate this problem in array-intensive embedded signal and video processing applications, compilers may employ either control-centric transformations that change data access patterns of nested loops or data-centric transformations that modify memory layouts of multidimensional arrays. Most of the memory layout optimizations proposed so far either modify the layout of each array independently or are based on explicit data reorganizations at runtime. We focus on a compiler technique, called array regrouping, that automatically maps multiple arrays into a single data (array) space to improve data access pattern. We present a mathematical framework that enables us to systematically derive suitable mappings for a given array-intensive embedded application. The framework divides the arrays accessed in a given program into several groups and each group is independently layout-transformed to improve spatial locality and reduce the number of conflict misses. As compared to the previous approaches, the proposed technique makes two new contributions: 1) It presents a graph based formulation of the array regrouping problem and 2) it demonstrates potential benefits of this aggressive array-regrouping strategy in optimizing behavior of embedded systems. Extensive experimental results demonstrate significant improvements in cache miss rates and execution times. An important advantage of this approach over the previous techniques that target conflict misses is that it reduces conflict misses without increasing the data space requirements of the application being optimized. This is a very desirable property in many embedded/portable environments where data space requirements determine the minimum physical memory capacity. In addition to performance related issues, with the increased use of embedded/portable devices, improving energy efficiency of applications is becoming a critical issue. To develop a truly energy-efficient system, energy constraints should be taken into account early in the design process, i.e., at the source level in software compilation and behavioral level in hardware compilation. Source-level optimizations are particularly important in data-dominated media applications. We also show how our array regrouping strategy increases energy savings from using multiple low-power operating modes provided in current memory modules. Using a set of array-intensive benchmarks, we observe significant savings in memory system energy.

Memory system optimization of embedded software

The memory system often determines a great deal about the behavior of an embedded system: performance, power, and manufacturing cost. A great many software techniques have been developed over the past decade to optimize software to improve these characteristics. Embedded software design and compilation can take advantage of two important facts: the hardware target is known; and we can spend more time and computational effort to optimize the software. This paper surveys techniques for optimizing memory behavior of embedded software and points to some future trends in the field.

Message from the guest editors

HIS special issue of the IEEE Transactions on Computers is the result of the Parallel Architecture and Compilation Techniques (PACT2000) Conference which was successfully held in Philadelphia, Pennsylvania, during the third week of October 2000. To follow the PACT tradition, this special issue is also intended to act as a forum that brings together research in parallel architectures and compilation. As advances in technology increase processing power and computing speed, the need for new architectures and compilers to harness such a potential also increases. This is exactly the goal of this special issue in providing a forum for computer architects and compiler designers to respond to the ever increasing need for higher performance. The major theme of the special issue was composed of 13 topics ranging from performance characterization and analytical modeling, prediction/speculation mechanisms, novel architectures, and software and hardware compilation techniques. We received 115 papers and five referees reviewed each paper, on average. The program committee met on 24 and 25 June 24 2000 in Pittsburgh. A great effort was given to select high quality of papers for presentation during the conference. After a long debate about each individual paper, the program committee recommended about 15 percent of the total papers for this special issue. Based on such a recommendation, authors of these papers were contacted and encouraged to revise and expand their papers for possible inclusion in this special issue. However, to be fair and to increase the quality of this special issue, a general call for papers was also issued. The 25 papers submitted for this special issue were evaluated and refereed by another set of reviewers. Late January of 2001, the guest editors spent a great deal of time making the final decision about the papers in this special issue. It was a challenging and rewarding experience for us to select the best among the best. This effort resulted in the selection of eight papers (six regular and two brief) in this special issue.

System-level power optimization

This tutorial surveys design methods for energy-efficient system-level design. We consider electronic sytems consisting of a hardware platform and software layers. We consider the three major constituents of hardware that consume energy, namely computation, communication, and storage units, and we review methods of reducing their energy consumption. We also study models for analyzing the energy cost of software, and methods for energy-efficient software design and compilation. This survery is organized around three main phases of a system design: conceptualization and modeling design and implementation, and runtime management. For each phase, we review recent techniques for energy-efficient design of both hardware and software.