Soft-input Soft-output Decoder Research Articles

Energy Efficient VLSI Architecture for Linear Turbo Equalizer

In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and decoding in which soft information is iteratively exchanged between the equalizer and decoder. However, turbo equalizers can be computationally complex and hence require significant power consumption. In this paper, we present an energy-efficient VLSI architecture for such linear turbo equalizers. Key architectural techniques include elimination of redundant operations and early termination. Early termination enables powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power. Simulation results show that energy savings in the range 30---60% and 10---60% are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling method to prevent overflow.

Soft-Output Decoding of 17 Parity Preserve/Prohibit Repeated Minimum Transition Runlength (PP) Code

We propose a novel trellis decoding technique for soft-output decoding of 17 parity preserve/prohibit repeated minimum transition runlength (PP) code. The trellis of the 17 PP code has 21 states and 79 branches. We applied the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm to the trellis to obtain a soft-input soft-output (SISO) decoder. Using this SISO decoder, we have developed a turbo-coded 17 PP system for optical recording. It is experimentally confirmed that the turbo-coded 17 PP system effectively improves the bit error rate (BER) of high-density optical storage.

Low-Complexity Turbo Equalization and Multiuser Decoding for TD-CDMA

The authors propose a low complexity multiuser joint parallel interference cancellation (PIC) decoder and turbo decision feedback equalizer for code division multiple access (CDMA). In their scheme, an estimate of the interference signal (both multiple-access interference and intersymbol interference) is formed by weighting the hard decisions produced by conventional (i.e., hard-output) Viterbi decoders. The estimated interference is subtracted from the received signal in order to improve decoding in the next iteration. By using asymptotic performance analysis of random-spreading CDMA, they optimize the feedback weights at each iteration. Then, they consider two (mutually related) performance limitation factors: the bias of residual interference and the ping-pong effect. The authors show that the performance of the proposed algorithm can be improved by compensating for the bias in the weight calculation, and they propose a modification of the basic PIC algorithm, which prevents the ping-pong effect and allows higher channel load and/or faster convergence to the single-user performance. The proposed algorithm is validated through computer simulation in an environment fully compliant with the specifications of the time-division duplex mode of third-generation systems, contemplating a combination of time-division multiple access and CDMA and including frequency-selective fading channels, user asynchronism, and power control. The main conclusion of this work is that, for such application, soft-input soft-output decoders (e.g., implemented by the forward-backward BCJR algorithm) are not needed to attain very high spectral efficiency, and simple conventional Viterbi decoding suffices for most practical settings.

Mapping Interleaving Laws to Parallel Turbo Decoder Architectures

For high data rate applications, the implementation of iterative turbo-like decoders requires the use of parallel architectures posing some collision-free constraints to the reading/writing process in the soft-input soft-output (SISO) decoders. Contrary to the literature belief, we prove in this paper that the parallelism constraints can be met by any permutation law employed by the turbo-interleaver, and we give a constructive method to satisfy those constraints.

Floating-gate analog implementation of the additive soft-input soft-output decoding algorithm

The soft-input soft-output algorithm is used to iteratively decode concatenated codes. To efficiently implement this algorithm, an additive form in the logarithmic domain is employed. A novel analog implementation using CMOS translinear circuits is proposed. A multiple-input floating-gate CMOS transistor working in the subthreshold region is used as the main translinear computing element. The proposed approach allows a direct mapping between the decoding algorithm and the circuit implementation. Experimental CMOS chip results are in good agreement with theoretical and simulation results.

Adaptive bayesian and em-based detectors for frequency-selective fading channels

The problems of adaptive maximum a posteriori (MAP) symbol detection for uncoded transmission and of adaptive soft-input soft-output (SISO) demodulation for coded transmission of data symbols over time-varying frequency-selective channels are explored within the framework of the expectation-maximization (EM) algorithm. In particular, several recursive forms of the classical Baum-Welch (BW) algorithm and its Bayesian counterpart (often referred to a Bayesian EM algorithm) are derived in an unified way. In contrast to earlier developments of the BW and BEM algorithms, these formulations lead to computationally attractive algorithms which avoid matrix inversions while using sequential processing over the time and trellis branch indices. Moreover, it is shown how these recursive versions of the BW and BEM algorithms can be integrated with the well-known forward-backward processing SISO algorithms resulting in adaptive SISOs with embedded soft decision directed (SDD) channel estimators. An application of the proposed algorithms to iterative turbo-processing receivers illustrates how these SDD channel estimators can efficiently exploit the extrinsic information obtained as feedback from the SISO decoder in order to enhance their estimation accuracy.

Iterative space-time soft interference cancellation for UMTS-FDD uplink

Two efficient pilot-aided iterative space-time interference cancellation receivers are studied in order to increase the uplink capacity of the Universal Mobile Telecommunication System (UMTS) in frequency-division duplex (FDD) mode. Both iterative schemes use low-complexity beamforming and path combining techniques associated with soft-input soft-output decoding to mitigate the multiple-access interference in space and time. The difference between the two techniques is in the way they deal with unknown channels: the addition of a space-time channel estimation in each iteration on the one hand and iterative adaptive beamforming and path combining on the other hand. Thanks to the iterative structure, the observation signal used for estimation or adaptation contains less interference from one iteration to the following, and soft estimates of coded bits are available for data-aided estimation or adaptation. A detailed complexity analysis shows that renewing beamforming and path combining in each iteration without a-priori knowledge of the channel has no significant impact on the overall complexity of one iteration. Simulations of true UMTS-FDD uplink communications over a wideband directional channel model reveal that near-single user performance can be obtained for very high system loads, whereas more conventional receivers, such as the interference canceller without beamforming and the two-dimensional RAKE receiver, fail in recovering the transmitted information.

Turbo Decoding with Run Length Limited Code for Optical Storage

A new turbo decoding method with a run length limited (RLL) code for optical storage is proposed. The system entails a trellis code that joins the RLL code, the non-return-to-zero inverse (NRZI) conversion, and the partial response (PR) channel as the inner code. The inner a posteriori probability (APP) decoder is able to utilize the extrinsic information fed back from the output of the outer decoder. A turbo-coded (1, 7)RLL-constrained PR2 channel was simulated. The full, partial, and serial turbo decoding systems with the inner APP decoder achieved coding gains of 4.7 dB, 4.3 dB, and 3.3 dB, respectively, over the uncoded (1, 7)RLL-constrained PR2 channel at a bit error rate (BER) of 10-5. The full and partial turbos were also improved by 1.2 dB and 0.8 dB, respectively, over the partial turbo with the RLL soft-input soft-output (SISO) decoder at a BER of 10-5.

Symbol-by-symbol Decoding as an Approximation of Word-by-word Decoding

Abstract Soft-input soft-output decoding consists of estimating the information symbol a posteriori probablities, taking account of the coding constraints, given the received symbol a priori probabilities. Kullback's principle of cross-entropy minimization is used for deriving optimum decoding rules assuming a linear, possibly non-systematic, binary code. A log-likelihood formalism is used throughout. Two decoding rules results, one by solving a system of analog implicit non-linear equations written in terms of a generator matrix, the other being the conventional one. We discuss simplified versions of both, present an interpretation of the first rule and compare it with the second one, given that both are intended to provide approximates of the same quantities.

VLSI architectures for iterative decoders in magnetic recording channels

VLST implementation complexities of soft-input soft-output (SISO) decoders are discussed. These decoders are used in iterative algorithms based on Turbo codes or Low Density Parity Check (LDPC) codes, and promise significant bit error performance advantage over conventionally used partial-response maximum likelihood (PRML) systems, at the expense of increased complexity. This paper analyzes the requirements for computational hardware and memory, and provides suggestions for reduced-complexity decoding and reduced control logic. Serial concatenation of interleaved codes, using an outer block code with a partial response channel acting as an inner encoder, is of special interest for magnetic storage applications.

Data width requirements in SISO decoding with module normalization

This letter studies the numerical properties of log-MAP-based soft-input soft-output decoding. The ranges of the differences between the path metrics, the soft output, and the complete information are derived. Since the log-MAP algorithm is functionally dependent only upon the differences between path metrics, not their magnitudes, a module normalization technique that is automatically implemented in two's complement arithmetic can be used to accommodate overflow of the path metrics. An expression for the minimum internal data width of a soft-input soft-output decoder that employs the module normalization technique is derived. As an application, the minimum internal data width of a decoder for the turbo code used in third-generation mobile communication systems is determined.

On the equivalence between SOVA and max-log-MAP decodings

It is shown that after a proper simple modification, the soft-output Viterbi algorithm (SOVA) proposed by Hagenauer and Hoeher (1989) becomes equivalent to the max-log-maximum a posteriori (MAP) decoding algorithm. Consequently, this modified SOVA allows to implement the max-log-MAP decoding algorithm by simply adjusting the conventional Viterbi algorithm. Hence, it provides an attractive solution to achieve low-complexity near-optimum soft-input soft-output decoding.