Soft Error Susceptibility Research Articles

Time and space efficient method for accurate computation of error detection probabilities in VLSI circuits

The authors propose a novel fault/error model based on a graphical probabilistic framework. They arrive at the logic induced fault encoded directed acrylic graph (LIFE-DAG), which is proven to be a Bayesian network, capturing all spatial dependencies induced by the circuit logic. Bayesian networks are the minimal and exact representation of the joint probability distribution of the underlying probabilistic dependencies that not only use conditional independencies in modelling but also exploit them for achieving minimality and smart probabilistic inference. The detection probabilities also act as a measure of soft error susceptibility (an increased threat in the nano-domain logic block) which depends on the structural correlations of the internal nodes and also on input patterns. Based on this model, they show that they are able to estimate detection probabilities of faults/errors on ISCAS'85 benchmarks with high accuracy, linear space requirement complexity, and with an order of magnitude (≈5 times) reduction in estimation time over corresponding binary decision diagram based approaches.

Soft error susceptibility and immune structures in dynamic random access memories (DRAMs) investigated by nuclear microprobes

Soft error susceptibility mapping and ion-beam-induced-current (IBIC) measurements using a nuclear microprobe allow a quantitative evaluation of the charge collection which induces upset in dynamic random access memories (DRAMs). Soft error susceptibility in DRAMs as a function of local position and structure has been reviewed. Charge collection efficiency induced by incident ions on reverse-biased n/sup +/p junctions with various barrier well structures has been compared with that with a conventional well in a p/sup -/ epitaxial layer on a p/sup +/ substrate.

Significant reduction in the soft error susceptibility of GaAs field-effect transistors with a low-temperature grown GaAs buffer layer

The use of a low temperature grown GaAs buffer layer beneath the channel of a metal-semicon- ductor field-effect transistor is shown via computer simulation to reduce ion-induced charge collection by two or more orders of magnitude. This reduction in collected charge is expected to reduce the heavy ion soft error rate by four to seven orders of magnitude in GaAs integrated circuits, and could have significant implications for the applicability of GaAs technology in space-based systems.

Direct measurement and improvement of local soft error susceptibility in dynamic random access memories

Soft errors induced in a dynamic random access memory (DRAM) have been measured using a nuclear microprobe. Soft error susceptibility of the local position and structure to the soft error has been clarified. Collection efficiency of charge carriers, induced by incident ions on reverse biased p-n junctions with barrier well structures, has been verified for various implantation doses for well formation.

Total dose dependence of soft-error hardness in 64 kbit SRAMs evaluated by single-ion microprobe technique

Total dose effect on the soft-error susceptibility of 64 kbit CMOS SRAM has been investigated by using the single ion microprobe technique which enables us to get a map of soft-error sensitivity in a memory cell by hitting a micron-size area with single ions. The effects of the ion dose on the susceptibility of each error-sensitive site have been evaluated. The errors due to the upset of p-MOSFETs have become more susceptible at higher dose while that of the n-MOSFETs less susceptible. One of the origins of the errors are the negative threshold voltage (V/sub th/) shifts of the MOSFETs which are caused by oxide trapped charges. Displacement damage induced by ion irradiation also affects the susceptibility to the soft-error. >