Soft Error Rate Estimation Research Articles

Influence of 0.1–10 MeV neutron-induced SEUs on estimation of terrestrial SER in a nano-scale SRAM

The impact of 0.1–10 MeV neutron-induced single-event upsets (NSEUs) on terrestrial SER (soft error rate) prediction is analyzed for several broad spectrum neutron sources based on 0.1–200 MeV NSEU energetic-dependent cross-sectional data of a 40 nm SRAM. The results show that for test facilities with abundant <10 MeV neutrons, such as ISIS ChipIR, J-PARC BL10, CSNS Back-n, and CSNS BL09, the terrestrial SER is overestimated. The overestimation could reach 78%–287%. By reducing the cutoff energy (Emin) from 10 to 6 MeV, the overestimation can be decreased. However, the overestimation can still reach up to 164% in this case, significantly larger than the results reported by previous studies. By analyzing the contribution of neutrons in different energy bins to NSEUs, the discrepancy is proved to be attributed to the sensitivity of NSEUs to 0.1–1 MeV neutrons, along with the overpopulation of 0.1–1 MeV neutrons for certain test facilities, such as ISIS ChipIR and CSNS BL09. Therefore, it is necessary to take 0.1–1 MeV NSEU sensitivity into account when studying the prediction method using broad spectrum neutron sources.

Analysis of the Impact of Electrical and Timing Masking on Soft Error Rate Estimation in VLSI Circuits

Due to continuous CMOS technology downscaling, Integrated Circuits (ICs) have become more susceptible to radiation-induced hazards such as soft errors. Thus, to design radiation-hardened and reliable ICs, the Soft Error Rate (SER) estimation constitutes an essential procedure. An accurate SER evaluation is provided based on a SPICE-oriented electrical masking analysis, combined with a TCAD characterization process. Furthermore, the proposed work analyzes the effect of a Static Timing Analysis (STA) methodology and the actual interconnection delay on SER evaluation. An analysis of the generated Single Event Multiple Transients (SEMTs) and the circuit operating frequency that are related to the SER estimation is also discussed. Various benchmarks, synthesized utilizing a 45 nm and 15 nm technology, are employed, and the experimental results demonstrate the SER variation as the device node scales down.

Synergistic Effect of BTI and Process Variations on the Soft Error Rate Estimation in Digital Circuits

Soft errors, aging effects and process variations have become the three most critical reliabil-ity issues for nanoscale complementary metal oxide semiconductor (CMOS) circuits. In this paper, the effects of bias temperature instability (BTI) and process variations on the threshold voltage of MOS devices are theoretically deduced, and the drift of the threshold voltage under the synergistic effect of BTI and process variations is analyzed. Based on the deduced threshold voltage drift formula under the synergistic effect, the critical charge and delay of different logic gates under different aging times in NanGate’s 45 nm process are simulated and analyzed. A method based on the change in the critical charge and delay of the soft error rate (SER) calculation considering BTI effect and process variations is given, and the effective-ness of our method comprehensively demonstrated using the ISCAS85,89 benchmarks. As a result, we can observe that the effect of only considering the BTI effect on the critical charge of the circuit is smaller than that of considering both the BTI effect and process variations. The simulation results show that with in-creasing aging time, the synergistic effect of BTI and process variations makes the increase in the soft error rate more serious than the impact of either effect alone.

Fast and Accurate SER Estimation for Large Combinational Blocks in Early Stages of the Design

Soft Error Rate (SER) estimation is an important challenge for integrated circuits because of the increased vulnerability brought by technology scaling. This paper presents a methodology to estimate in early stages of the design the susceptibility of combinational circuits to particle strikes. In the core of the framework lies MASkIt , a novel approach that combines signal probabilities with technology characterization to swiftly compute the logical, electrical, and timing masking effects of the circuit under study taking into account all input combinations and pulse widths at once. Signal probabilities are estimated applying a new hybrid approach that integrates heuristics along with selective simulation of reconvergent subnetworks. The experimental results validate our proposed technique, showing a speedup of two orders of magnitude in comparison with traditional fault injection estimation with an average estimation error of 5 percent. Finally, we analyze the vulnerability of the Decoder, Scheduler, ALU, and FPU of an out-of-order, superscalar processor design.

Characterizing Energetic Dependence of Low-Energy Neutron-Induced SEU and MCU and Its Influence on Estimation of Terrestrial SER in 65-nm Bulk SRAM

Characterizing low-energy neutrons (<; 10 MeV)-induced single-event upsets (SEUs) and multiple cells upsets (MCUs) is essential to validate the current standard for terrestrial soft error rate (SER) and investigate its enhancement. Following our preliminary analysis on the contribution of the low-energy neutrons to the total terrestrial SER at the nominal operating voltage of 1.0 V by Liao et al. (2020), this article newly presents and analyzes the data measured at the low operating voltage of 0.4 V. The dependence of SEU cross section on the neutron energy is similar between the operating voltages of 0.4 and 1.0 V, including onset energy of around 6 MeV. The existence of MCUs at 4.1-MeV neutrons was also confirmed at both the operating voltages. Based on the measurement, we approximate the dependence of SEU and MCU cross sections as Weibull functions of the neutron energy. The terrestrial SER of SEUs and MCUs was calculated by folding the Weibull function and the flux spectrum. The calculated result indicates that the SER originating from the low-energy neutrons is less than 6% in the terrestrial environment at New York and Tokyo City. We confirm that disregarding the flux of neutrons below 10 MeV in the acceleration factor calculation at accelerated neutron tests, which follows the current standard defined in JESD89, could give a reasonable SER estimation accuracy for both SEUs and MCUs. On the other hand, for covering the beams having an extremely high proportion of low-energy neutrons, considering the flux of neutrons above 6 MeV would be an option for better SER estimation.

Temperature-Constrained Reliability Optimization of Industrial Cyber-Physical Systems Using Machine Learning and Feedback Control

As the backbone of Industry 4.0, industrial cyber-physical systems (ICPSs) that are geographically dispersed, federated, cooperative, and security-critical systems become the center of interest from both industry and academia. In ICPS, there are huge amounts of devices, such as sensors and actuators, which are embedded and networked together to improve the performance of real-time monitoring and control. Reliability and temperature are two important concerns of these embedded and networked devices in ICPS due to their stringent requirement of reliable execution and long lifespan. In this article, we study the problem of maximizing soft-error reliability of CPU- and GPU-integrated embedded platforms deployed in ICPS under the temperature constraint. To speed up the estimation of soft-error rate (SER) and temperature, we train an artificial neural network (ANN) that is able to quickly and accurately derive the system’s SER and temperature. To solve the temperature-constrained reliability optimization problem, we propose a feedback control-based task scheduling scheme that adaptively determines the number of tasks admitted in the system and the number of replicas for the admitted tasks. We perform a series of simulation experiments to verify the efficacy of our scheme. The experimental results demonstrate that: 1) the estimated SER and temperature derived by our ANN-based method are very close to the ground-truth data and 2) our proposed feedback control-based task scheduling method can improve system reliability by up to 184.2% with a lower peak temperature when compared with one baseline and two state-of-the-art methods. Note to Practitioners—This article is motivated by the safety-critical industrial cyber-physical system (ICPS) applications necessitating reliable execution and long lifespan, which could be realized by increasing reliability and controlling operating temperature. Our goal is to improve the system reliability of CPU- and GPU-integrated multiprocessor systems-on-chip (MPSoCs) deployed in ICPS under the temperature constraint. Most of the existing papers target either reliability or temperature. A few recent papers have focused on reliability and temperature optimization simultaneously. However, they are not designed for ICPS and do not consider the widely accepted CPU- and GPU-integrated MPSoC platforms. This article proposes a machine learning-based approach that trains an artificial neural network (ANN) to facilitate the online estimation of system SER and temperature. Compared to the offline estimation using simulation tools, the online approach is more applicable to real-time ICPS applications. This article also designs a feedback control-based approach for improving system reliability and reducing peak temperature of the CPU- and GPU-integrated MPSoCs by determining the number of tasks to be admitted and the number of replicas for tasks.

Joint Effects of Aging and Process Variations on Soft Error Rate of Nano-Scale Digital Circuits

Soft errors have always been a concern in the design of digital circuits. As technology down-scales toward Nanometer sizes, emergence of aging effects, process variations, and Multiple Event Transients (METs) has made the soft error rate (SER) estimation of digital circuits very challenging. This paper intends to characterize the challenges by investigating the cross effects of theses issues in overall SER of a circuit. To this regard, we employ a simulation-based SER estimation approach in which the aging effect, process variations and METs are jointly considered in our fault injection process. In our simulation-based SER estimation approach, a statistical gate delay model is used. The fault injection results into ISCAS85 circuit benchmark reveal that the SER estimation without taking into account the aging effects, the process variations, and METs is significantly inaccurate.

SET Pulse Characterization and SER Estimation in Combinational Logic with Placement and Multiple Transient Faults Considerations

Integrated circuit susceptibility to radiation-induced faults remains a major reliability concern. The continuous downscaling of device feature size and the reduction in supply voltage in CMOS technology tend to worsen the problem. Thus, the evaluation of Soft Error Rate (SER) in the presence of multiple transient faults is necessary, since it remains an open research field. In this work, a Monte-Carlo simulation-based methodology is presented taking into consideration the masking mechanisms and placement information. The proposed SER estimation tool exploits the results of a Single Event Transient (SET) pulse characterization process with HSPICE to obtain an accurate assessment of circuit vulnerability to radiation. A new metric, called Glitch Latching Probability, which represents the impact of the masking effects on a SET, is introduced to identify gate sensitivity and, finally, experimental results on a set of ISCAS’ 89 benchmarks are presented.

GPU-Accelerated Soft Error Rate Analysis of Large-Scale Integrated Circuits

In this article, a team of researchers from Shiraz University and the Shahid Bahonar University of Kerman, Iran, investigates soft error rate (SER) estimation. They propose an analytical framework to estimate SER accurately and an implementation on graphic processing units (GPUs) that is able to scale to circuits composed of thousands of gates. The framework exploits several levels of parallelism in the SER estimation process to map it efficiently onto GPUs.

An Incremental Algorithm for Soft Error Rate Estimation of Combinational Circuits

With the scaling of CMOS transistor dimensions, soft errors in combinational logic circuits are emerging as a significant reliability concern in nano-scale digital systems design. Hence, fast and efficient approaches to estimate the soft error rate (SER) of combinational circuits have become significantly important. SER is a crucial diagnostic metric which provides valuable information to guide SER optimization and reliability-driven logic synthesis. Existing works for SER analysis in the literature, however, computes this metric in a non-incremental manner, that is, after one or more changes in a previously timed circuit, it is required to recompute SER from scratch, which is obviously undesirable for optimizing large circuits. In this paper, an incremental technique is presented to estimate the SER of combinational circuits. An accurate model is proposed for SER estimation by considering all three masking mechanisms (namely, logical, electrical, and timing). The proposed incremental re-estimation SER algorithm is based on the information provided by the primary SER calculation. A set of rules, based on the topological locations of logic gates in the circuit graph, is introduced to identify the portion of the design for which the gates SER are affected, and quickly computes the new SER values. Experimental results on ISCAS’89 benchmarks show that, on average, 10 times speedup is achieved during SER re-estimations without sacrificing accuracy.

Accelerated Soft-Error-Rate (SER) Estimation for Combinational and Sequential Circuits

Radiation-induced soft errors have posed an increasing reliability challenge to combinational and sequential circuits in advanced CMOS technologies. Therefore, it is imperative to devise fast, accurate and scalable soft error rate (SER) estimation methods as part of cost-effective robust circuit design. This paper presents an efficient SER estimation framework for combinational and sequential circuits, which considers single-event transients (SETs) in combinational logic and multiple cell upsets (MCUs) in sequential elements. A novel top-down memoization algorithm is proposed to accelerate the propagation of SETs, and a general schematic and layout co-simulation approach is proposed to model the MCUs for redundant sequential storage structures. The feedback in sequential logic is analyzed with an efficient time frame expansion method. Experimental results on various ISCAS85 combinational benchmark circuits demonstrate that the proposed approach achieves up to 560.2X times speedup with less than 3% difference in terms of SER results compared with the baseline algorithm. The average runtime of the proposed framework on a variety of ISCAS89 benchmark circuits is 7.20s, and the runtime is 119.23s for the largest benchmark circuit with more than 3,000 flip-flops and 17,000 gates.

Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations

Soft errors in combinational logic circuits are emerging as a significant reliability concern for nanoscale VLSI designs. This paper presents a novel sensitivity-based gate sizing methodology to reduce the soft error rate (SER) of combinational circuits in the presence of process variations. The proposed method is based on modeling the statistics of SER of the circuit gates as a random variable to formulate a statistical optimization problem. A backward traversing algorithm with capability for incremental analysis is developed for computing the distribution of circuit gates of SER random variables. We present a gate resizing algorithm in which the gates with the most contribution to the circuit SER are selected in a candidate set using a statistical ordering approach. The proposed algorithm trades off SER reduction and area overheads. The experimental results show that using the proposed methodology, the circuit statistical SER can be reduced by up to 56.4% compared with the 14.8% SER reduction of a circuit obtained using the worst case methodology at the expense of 10% area overhead under 10% process variation ratio. The results also show that the proposed method achieves about 40% more SER reduction compared with that obtained using closed-form analysis for statistical soft error rate estimation (CASSER), the most recently published similar work, in the same experimental conditions. Comparing the runtime of the proposed optimization algorithm with the optimization based on CASSER, it is observed that the proposed method is two orders of magnitude faster than CASSER due to its incremental analysis property.

Layout-aware Soft Error Rate Estimation Technique for Integrated Circuits under the Environment with Energetic Charged Particles

Single Event Transient (SET) is a current and voltage disturbance in an integrated circuit (IC), caused by charged particle impact. In modern IC technologies single charged particle can cause multiple SETs on multiple electrical nodes, this can lead to faults. There are several mitigation techniques with their drawbacks affecting circuit performance. This work presents a comparison of experimental data with simulation results acquired by the means of our technique and tools. Our technique is able to simulate sub-100 nm IC performance under multiple SET using industry standard SPICE simulator, without incorporation of a T-CAD or physical measurements, and taking into account layout of the device.

Statistical soft error rate estimation of combinational circuits using Bayesian networks

Purpose With continuous scaling of digital circuit CMOS technology, the vulnerability of these circuits are significantly increasing against the soft errors. On the other hand, the effects of process variation in the electrical properties of nano-scale circuits, have introduced the statistical methods as an unavoidable choice for the soft error rate (SER) estimation. The purpose of this paper is to provide a statistical soft error rate (SSER) estimation approach for combinational circuits in the presence of process variation. Design/methodology/approach In this paper a new method is proposed for the SSER estimation of combinational circuits based on the Bayesian networks (BNs). This allows to factor the joint probability distributions over variables in a circuit graph. The distribution of the initial transient fault pulse is estimated by the pre-characterization tables. Timing signals are propagated by BN theory and the probability distribution of electrical and timing masking are calculated. Findings Simulation results for some benchmark circuits show that the proposed method is accurate with 3.7 percent difference with the Monte-Carlo SPICE simulation and with orders of magnitude improvement in runtime. Originality/value The proposed framework is the scheme giving the low estimation time with plausible accuracy compared to other schemes. The comparison exhibits that the designer can save its estimation time in terms of performance and complexity. The deterministic-based methods also are able to evaluate the SER of combinational circuit, yet in an unacceptable time.

A Fast Statistical Soft Error Rate Estimation Method for Nano-scale Combinational Circuits

Nano-scale digital integrated circuits are getting increasingly vulnerable to soft errors due to aggressive technology scaling. On the other hand, the impacts of process variations on characteristics of the circuits in nano era make statistical approaches as an unavoidable option for soft error rate estimation procedure. In this paper, we present a novel statistical Soft Error Rate estimation framework. The vulnerability of the circuits to soft errors is analyzed using a newly defined concept called Statistical Vulnerability Window (SVW). SVW is an inference of the necessary conditions for a Single Event Transient (SET) to cause observable errors in the given circuit. The SER is calculated using a probabilistic formulation based on the parameters of SVWs. Experimental results show that the proposed method provides considerable speedup (about 5 orders of magnitude) with less than 5 % accuracy loss when compared to Monte-Carlo SPICE simulations. In addition, the proposed framework, keeps its efficiency when considering a full spectrum charge collections (more than 36X speedups compared to the most recently published similar work).

Parallel SER analysis for combinational and sequential standard cell circuits

A parallel SER (soft error rate) evaluation framework ASSET-VLG was developed to analyze the SER of both combinational and sequential standard cell circuits. ASSET-VLG was constructed in practically oriented way: (i) it employs a verilog parser for automatically reading the synthesized DUT (device under test) netlist; (ii) it provides an accurate and unified SER analysis framework for both the combinational and sequential circuits rather than the former only; (iii) it targets to a 130nm production library and the modeling method can be easily ported to newer technologies. Furthermore, concurrency is also exploited for accelerating the evaluation procedure on modern multi-core computers. These features make ASSET-VLG appropriate for automatic SER estimation in design stage and can be easily integrated into current highly reliable ICs design flow. Experiments on ISCAS׳85 and ISCAS׳89 benchmark circuits show the evaluation time ranges from 0.5ms to 2.16s without previous memory explosion problem. Compared with spice, the modeling method of ASSET-VLG provides 98% accuracy. The parallelizing experiments indicate the proposed method has better scalability, e.g., 4.44X speedup are obtained in a 4 cores/8 threads platform. The experiments also reveal that sequential part (flip-flops) in the circuit dominating the system SER by one order than combinational gates for a 130nm CMOS process. Last but not least, significant frequency dependence of SER are observed in flip-flops, implying the commonly used critical charge measure is insufficient for characterizing soft error in sequential cells.

Soft error rate estimation of combinational circuits based on vulnerability analysis

Nanometer integrated circuits are getting increasingly vulnerable to soft errors and making the soft error rate (SER) estimation an important challenge. In this study, a novel approach is proposed for SER estimation of combinational circuits based on vulnerability analysis. The authors introduce a concept called probabilistic vulnerability window (PVW) which is an inference of necessary conditions for a single event transient (SET) to cause observable errors in the circuit. A proposed computational framework calculates PVWs for all circuit gates in a backward-traversing algorithm enabling the circuit designers for an accurate and efficient SER estimation. Experimental results show that the proposed approach is 2× faster than the traditional SER estimation methods and keep its efficiency when it is applied for estimating the SER considering various different SET widths while runtime of traditional estimation methods increases in such cases. In addition, results verify the accuracy (average difference of 0.02) and speedup (about four orders of magnitude) of the proposed method when compared with the Monte Carlo-based fault injection simulation on ISCAS'85 benchmark circuits.

A mixed-level framework to estimate SER induced by SEMT in advanced technologies

ABSTRACTAs the complementary metal oxide semiconductor feature size shrinks further, single event multiple transients (SEMTs) become more serious. However, SEMTs have not yet been appropriately modelled through traditional soft error rate (SER) estimation methods. Therefore, this paper presents a mixed-level framework to estimate SER induced by SEMTs. The precision of the proposed framework is verified through HSPICE simulation. The results show that multiple pulses and convergence of SEMTs significantly affect SER estimation.

Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits

Soft errors, due to cosmic radiations, are one of the major challenges for reliable VLSI designs. In this paper, we present a symbolic framework to model soft errors in both synchronous and asynchronous designs. The proposed methodology utilizes Multiway Decision Graphs (MDGs) and glitch-propagation sets (GP sets) to obtain soft error rate (SER) estimation at gate level. This work helps mitigate design for testability (DFT) issues in relation to identifying the controllable and the observable circuit nodes, when the circuit is subject to soft errors. Also, this methodology allows designers to apply radiation tolerance techniques on reduced sets of internal nodes. To demonstrate the effectiveness of our technique, several ISCAS89 sequential and combinational benchmark circuits, and multiple asynchronous handshake circuits have been analyzed. Results indicate that the proposed technique is on average 4.29 times faster than the best contemporary state-of-the-art techniques. The proposed technique is capable to exhaustively identify soft error glitch propagation paths, which are then used to estimate the SER. To the best of our knowledge, this is the first time that a decision diagram based soft error identification approach is proposed for asynchronous circuits.

A New Analytical Model of SET Latching Probability for Circuits Experiencing Single- or Multiple-Cycle Single-Event Transients

As technology scales down, more single-event transients (SETs) are expected to occur in combinational circuits and thus contribute to the increase of soft error rate (SER). We propose a systematic analysis method to precisely model the SET latching probability. Due to the decreased critical charge and shortened pipeline stage, the SET duration time is likely to exceed one clock cycle. In previous work, the SET latching probability is modeled as a function of SET pulse width, setup and hold times, and clock period for single-cycle SETs. Our analytical model does not only include new dependent parameters such as SET injection location and starting time, but also precisely categorizes the SET latching probabilities for different parameter ranges. The probability of latching multiple-cycle SETs is specifically analyzed in this work to address the increasing ratio of SET pulse width over clock period. We further propose a method that exploits the boundaries of those dependent parameters to accelerate the SER estimation. Simulation results show that the proposed analysis method achieves up to 97% average accuracy, which is applicable for both single- and multiple-cycle SETs. Our case studies on ISCAS'85 benchmark circuits confirm our analysis on the impact of SET injection location and starting time on the SET latching probability. By exploiting our analytical model, we achieve up to 78% simulation time reduction on the process of SET latching probability and SER estimation, compared with Monte-Carlo simulation.