Soft-core Processor Research Articles

Hybrid Spatial and Temporal Computing Histogrammer in Soft Processor Core of a FPGA Device

Hybrid Spatial and Temporal Computing Histogrammer in Soft Processor Core of a FPGA Device

FEINT: Automated Framework for Efficient INsertion of Templates/Trojans into FPGAs

Field-Programmable Gate Arrays (FPGAs) play a significant and evolving role in various industries and applications in the current technological landscape. They are widely known for their flexibility, rapid prototyping, reconfigurability, and design development features. FPGA designs are often constructed as compositions of interconnected modules that implement the various features/functionalities required in an application. This work develops a novel tool FEINT, which facilitates this module composition process and automates the design-level modifications required when introducing new modules into an existing design. The proposed methodology is architected as a “template” insertion tool that operates based on a user-provided configuration script to introduce dynamic design features as plugins at different stages of the FPGA design process to facilitate rapid prototyping, composition-based design evolution, and system customization. FEINT can be useful in applications where designers need to tailor system behavior without requiring expert FPGA programming skills or significant manual effort. For example, FEINT can help insert defensive monitoring, adversarial Trojan, and plugin-based functionality enhancement features. FEINT is scalable, future-proof, and cross-platform without a dependence on vendor-specific file formats, thus ensuring compatibility with FPGA families and tool versions and being integrable with commercial tools. To assess FEINT’s effectiveness, our tests covered the injection of various types of templates/modules into FPGA designs. For example, in the Trojan insertion context, our tests consider diverse Trojan behaviors and triggers, including key leakage and denial of service Trojans. We evaluated FEINT’s applicability to complex designs by creating an FPGA design that features a MicroBlaze soft-core processor connected to an AES-accelerator via an AXI-bus interface. FEINT can successfully and efficiently insert various templates into this design at different FPGA design stages.

Antimalware applied to IoT malware detection based on softcore processor endowed with authorial sandbox

Antimalware applied to IoT malware detection based on softcore processor endowed with authorial sandbox

Real-Time Implementation of Stockwell Transform in FPGA Platform Using Soft-core Processor Applied to Novelty Detection in Power Quality Signals

Real-Time Implementation of Stockwell Transform in FPGA Platform Using Soft-core Processor Applied to Novelty Detection in Power Quality Signals

FPGA-Based High-Speed Energy-Efficient 32-Bit Fixed-Point MAC Architecture for DSP Application in IoT Edge Computing

Designing high-speed and energy-efficient blocks for image and digital signal processing (DSP) architecture is an evolving research field. This work designs a high-speed and energy-efficient multiply-accumulate (MAC) unit to augment the performance of field-programmable gate array (FPGA)-based accelerators and softcore processors. In this work, three discrete 32-bit fixed-point signed MAC architectures were designed in Verilog and synthesized for the Zynq 7000 ZedBoard to obtain efficient MAC architecture. The ultimate goal of this work is to design a fast and energy-efficient MAC unit that can achieve speed up to the DSP48 block to reduce the latency of IoT edge computing. Energy efficiency was achieved in PPG and partial product addition (PPA) for the proposed Booth radix-4 Dadda (BR4D)-based MAC. At PPG, the width of the partial product (PP) terms was optimized with Bewick’s signed extension to reduce the power consumption. At PPA, the number of PP rows reduces the critical path delay (CPD) with Dadda-based PPA. The proposed BR4D MAC unit offers a reduction in dynamic power, CPD, power-delay product (PDP) and energy-delay product (EDP) by 22%, 9%, 29% and 36%, respectively, compared to standard Booth radix-4 Wallace tree (BR4WT) based MAC. Furthermore, hybrid MACs (BR4WT and BR4D) were compared with the current state-of-the-art (SoA) designs, and it was found that the proposed BR4D MAC is 47% faster compared to the same design in SoA. The proposed BR4D was tested for frequency scaling technique by reducing the frequency in steps of 10 MHz from a maximum usable frequency (MUF) of 64 MHz to 10 MHz to evaluate the performance for low-power applications. Reducing clock frequency by 84% will reduce the power consumption at the same proportion and speed by 38%. Additionally, the proposed design helps to improve the battery life of IoT end nodes with a reduction in energy consumption and EDP by 76% and 61%, respectively.

Design and Evaluation of Open-Source Soft-Core Processors

The advantage of FPGAs lies in their ability to implement a fully hardware solution for interfacing with various input/output (I/O) devices. Each block can work in parallel with all the others, simplifying the satisfaction of timing constraints. However, this hardware utilization consumes FPGA resources that could otherwise be allocated to the primary project. An alternative involves employing a small “soft-core” processor to implement I/O in software. With the goal of designing and evaluating a new tiny soft-core processor optimized for FPGA resources in I/O, a novel processor named Baby8 is developed. It is an 8-bit CISC soft-core processor optimized for reduced FPGA resources, including program size for 8-bit applications. The number of instructions is not large, but any instruction can access arbitrary memory locations. The performance and resource utilization of the newly designed processor are evaluated and compared with a variety of other soft-core processors. The results demonstrate its competitive performance, achieving an average maximum clock frequency of approximately 57 MHz and a power consumption of around 2 mW. Furthermore, it conserves nearly half of the FPGA resources in implementation.

A flexible soft error mitigation framework leveraging dynamic partial reconfiguration technology

Fault tolerance is crucial for mission-critical FPGA-based systems in radiation environments. Soft-core processors in these systems, performing both control and computational tasks, require efficient soft error mitigation techniques to enhance their fault tolerance. In this paper, we investigate the variation trends in the fault tolerance of various processor components as the software workload changes. Based on our investigation, we propose a reconfigurable soft error mitigation framework that dynamically switches the hardening strategies for the processor according to the running workloads. The innovative application of dynamic partial reconfiguration technique in FPGAs enables time-multiplexing of the same circuit region to accommodate various hardening schemes, consequently achieving high area efficiency. We apply the framework to an open-source dual-issue superscalar RISC-V processor on a Xilinx ZCU102 FPGA board. Compared to traditional spatial redundancy-based hardening techniques, the proposed framework achieves a 20.84 % reduction in LUT utilization and a 20.53 % reduction in flip-flop utilization. The effectiveness of our framework has been evaluated through fault injection campaigns. The results indicate that, on average, only 0.05 % of faults would lead to system failure after hardening. Therefore, our work offers a new perspective on dynamic soft error mitigation in reconfigurable systems.

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring instruments. In this work, however, we analyze the CPU instruction-level power side-channel leakage in an environment that lacks physical access or expensive measuring equipment. We show that instruction leakage is present even in a multitenant FPGA scenario, where the victim uses a soft-core CPU, and the adversary deploys on-chip voltage-fluctuation sensors. Unlike previous remote power side-channel attacks, which either require a considerable number of victim traces or attack large victim circuits such as machine learning accelerators, we take an evaluator’s point of view and provide an analysis of the instruction-level power side-channel leakage of a small open-source RISC-V soft processor core. To investigate whether the power side-channel traces leak secrets, we profile the victim device and implement various instruction opcode classifiers based on both classical machine learning algorithms used in disassembly attacks, and novel, deep learning approaches. We explore how parameters such as placement, trace averaging, profiling templates, and different FPGA families (including a cloud-scale FPGA) impact the classification accuracy. Despite the limited leakage of the soft-core CPU victim and a reduced accuracy and sampling rate of on-chip sensors, we show that in a worst-case scenario for the evaluator, i.e., an attacker breaching physical separation, we can identify the opcode of executed instructions with an average accuracy as high as 86.46%. Our analysis shows that determining the executed instruction type is not a classification bottleneck, while leakages between instructions of the same type can be challenging for deep learning models to distinguish. We also show that the instruction-level leakage is significantly reduced in a cloud-scale FPGA scenario with higher soft-core CPU frequencies. Nevertheless, our results show that even small circuits, such as soft-core CPUs, leak potentially exploitable information through on-chip power side channels, and users should deploy mitigation techniques against disassembly attacks to protect their proprietary code and data.

RECO-ASCON: Reconfigurable ASCON hash functions for IoT applications

The need for reconfigurable lightweight cryptographic processors with low power consumption for securing the Internet of Things (IoT) with adaptive functionalities is getting attracted due to security properties, such as data fidelity, provenance, and privacy concerns. This paper presents RECO-ASCON, a reconfigurable security processor that supports both cryptographic Hash and Hasha ASCON algorithms. The proposed design is implemented in Chisel hardware construction language, an open-source hardware library. It has been evaluated in various hardware platforms such as FPGAs, embedded systems and ASICs with various technology nodes and design flows. In the PYNQ-Z1 board, RECO-ASCON can be mapped to five processors in total with a Micro-Blaze soft-core processor for streaming data to all of them while running at 200MHz without producing any timing violations. Moreover, mapping the proposed RECO-ASCON processor on the Nexsys4-DDR Xilinx Kit (ARTIX-7 chip) would cost ∼ two times fewer resources and run 1.25 × faster than the existing implementation of just one of the ASCON hash functions on the same family of the chip. We implement the proposed processor in 28 nm industry technology with commercial design flow, it achieves a maximum frequency of 1.12 GHz while achieving highest energy efficiency compared to the state-of-the-art implementations. The total area is only 9170.82um2 in 28 nm. To further evaluate the design, we also implement it with all open-source design tools and process technology libraries in 45 nm, it achieves 1 GHz maximum frequency and consumes only 18225um2 in 45 nm. Overall, the proposed reconfigurable processor is compact and more energy efficient, making it a perfect candidate to be deployed in wide range of IoT systems.

Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation.

One of the fundamental requirements of a real-time system (RTS) is the need to guarantee re-al-time determinism for critical tasks. Task execution rates, operating system (OS) overhead, and task context switching times are just a few of the parameters that can cause jitter and missed deadlines in RTS with soft schedulers. Control systems that are susceptible to jitter can be used in the control of HARD RTS as long as the cumulative value of periodicity deviation and worst-case response time is less than the response time required by that application. This artcle presents field-programmable gate array (FPGA) soft-core processors integration based on different instruction set architectures (ISA), custom central processing unit (CPU) datapath, dedicated hardware thread context, and hardware real-time operating system (RTOS) implementations. Based on existing work problems, one parameter that can negatively influence the performance of an RTS is the additional costs due to the operating system. The scheduling and thread context switching operations can significantly degrade the programming limit for RTS, where the task switching frequency is high. In parallel with the improvement of software scheduling algorithms, their implementation in hardware has been proposed and validated to relieve the processor of scheduling overhead and reduce RTOS-specific overhead.

A comparison of an evolvable hardware controller with an artificial neural network used for evolving the gait of a hexapod robot

This paper investigates the implementation of a novel evolvable hardware controller used in evolutionary robotics. The evolvable hardware consists of a Cartesian based array of logic blocks comprised of multiplexers and logic elements. The logic blocks are configured by a bit stream which is evolved using a genetic algorithm. A comparison is performed between an evolvable hardware and an artificial neural network controller evolved using the same genetic algorithm to produce the gait of a hexapod robot. To compare the two controllers, differences in their evolutionary efficiency and robot performance are investigated. The evolutionary efficiency is measured by the required number of generations to achieve an optimal fitness. An optimal hexapod controller allows the robot to walk forward in a straight line maintaining a constant heading and body attitude. It was found that the evolutionary efficiency and performance of the evolvable hardware and artificial neural network were similar, however the EHW was the most evolutionary efficient requiring less generations on average to evolve. Both evolved controllers were evaluated in simulation, and on a physical robot using a softcore processor and custom hardware implemented on a FPGA. The implementation showed that the controllers performed equally well when deployed, allowing the hexapod to meet the optimal gait criteria. These findings have shown that the evolvable hardware controller is a valid option for robotic control of a multilegged robot such as a hexapod as its evolutionary efficiency and deployed performance on a real robot is comparable to that of an artificial neural network. One future application of these evolvable controllers is in fault tolerance where the robot can dynamically adapt to a fault by evolving the controller to adjust to the fault conditions.

MPSoC design and implementation using microblaze soft core processor architecture for faster execution of arithmetic application

The research paper presents the design methodology with novel task distribution technique on multi-processor system on chip (MPSoC) for speeding up the execution of arithmetic application. Utilisation of multiple soft core processors on field programmable gate array (FPGA) reduces the overload of adding external hardware to a system. Parallel processing of soft core processor with proposed task distribution technique makes any application to execute at faster rate. This task distribution based speed enhancement technique for arithmetic application is very feasible and appealing to the modern applications like neural networks, fuzzy logic, algorithms of machine learning etc. Experimentation on such architecture with arithmetic application shows significant increase in speed of operation with respect to conventional design. This is implemented using Microblaze soft core processor architecture on Xilinx Virtex 5 FPGA board.

MPSoC design and implementation using Microblaze soft core processor architecture for faster execution of Arithmetic application

MPSoC design and implementation using Microblaze soft core processor architecture for faster execution of Arithmetic application

Customized FPGA Design and Analysis of Soft-Core Processor for DNN

Transistor scaling has continued to yield significant performance gains. The general-purpose architecture will not suffice in this dark silicon era with the big data boom and growing emphasis on performance. Artificial neural networks and deep learning are sophisticated computing activities that cannot be optimally executed (accuracy, performance, and energy) on today's general-purpose computer architecture. The demand for domain-specific computer architectures is increasing. This paper suggests and evaluates a highly reconfigurable domain-specific design for deep learning and artificial neural networks to overcome these problems. An FPGA-based soft-core processor for deep neural network (DNN) acceleration is suggested in this paper. Using a combination of unicast and multicast for collective operations, the proposed FPGA accelerates the performance of the deep learning network. The suggested design outperforms the current general-purpose processor by 6.6 times, according to a thorough examination and comparison. The existing architecture's level of accuracy is retained.

Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension

The Consultative Committee for Space Data Systems (CCSDS) recommends the use of short-block length Bose-Chaudhuri-Hocquenghem (BCH) and binary low-density parity-check (LDPC) codes. Despite the high error-correction capacity of non-binary low-density parity-check (NB-LDPC) codes, they have not yet been considered due to their high decoding complexity. In this paper, the feasibility of NB-LDPC coding for space telecommand link applications using a RISC-V soft-core processor plus a vector co-processor is demonstrated. The purpose of this work is to avoid the need for a dedicated decoder hardware, and thus the customized general-purpose processor which performs decoding can be reconfigured to perform other important on-board tasks. In this way, the logic utilization and power consumption can be reduced since more functionalities can be assumed by the on-board processor. The method of acceleration of a NB-LDPC decoder over GF(16) using the RISC-V vector extension is demonstrated, and a throughput of 8.48 kbps is achieved for the Forward-Backward implementation of the min-max decoding algorithm, which is compatible with the low-rate and mid-rate telecommand systems recommended by CCSDS.

Proposal of a reliable embedded circuit to control a stepper motor using microblaze soft-core processor

The vast majority of embedded system designs start with a processor-based system, using a microcontroller or microprocessor as the core element to predict and process the basic control tasks. This paper aims to increase the reliability of controlling a stepper motor by an embedded circuit, which generates four digital signals of pulse width modulation (PWM). The manager of this circuit is an embedded processor licensed from Microblaze, which sits within the FPGA architecture Virtex 5. This processor analyzes the parameters to execute the rotation under the best conditions (energy consumption, speed, precision, reliability). The communication with the PC takes place via the RS232 link to provide feedback. The autonomous processor generates an independent control frequency of the PC. The four digital signals of PWM are simulated on Xilinx's ISim interface and sent to the ULN2803 amplifier circuit to run the stepper motor.

XML-Based Automatic NIOS II Multi-Processor System Generation for Intel FPGAs

Many embedded systems are introducing processing units to accelerate the processing speed of tasks, such as for multi-media applications. The units are mostly customized designs. Another method of designing multi-unit systems is using pre-defined standard intellectual properties. However, the procedure of arranging IP cores in a system and maintaining a high performance as well are the remaining challenges. Implementing softcore processors on field-programmable gate arrays (FPGAs) is a relatively fast and inexpensive choice to design and validate a desired system. This paper describes the rapid prototyping of hardware/software co-design based on FPGAs. A novel system generator to effortlessly design a multiple NIOS II soft-processor core systems is also purposed. The NIOS II CPU is a configurable RISC processor designed by Altera/Intel and can be trimmed to complete specific tasks. The error-prone and time-consuming process of designing an IP block-based system is improved by the new novel system generator. The detail of the implementation of such system is discussed. To test the performance of a multi-NIOS II system, a parallel application is executed on 1-, 2-, 5-, and 10-core NIOS II systems separately. Test results prove the feasibility of the proposed methodology (for an FIR filter, a dual-core system is 29% faster than a single-core system; a 5-core system is 28% faster than the dual-core system).

Remote reconfiguration of FPGA-based wireless sensor nodes for flexible Internet of Things☆

Recently, sensor nodes in Wireless Sensor Networks (WSNs) have been using Field Programmable Gate Arrays (FPGA) for high-speed, low-power processing and reconfigurability. Reconfigurability enables adaptation of functionality and performance to changing requirements. This paper presents an efficient architecture for full remote reconfiguration of FPGA-based wireless sensors. The novelty of the work includes the ability to wirelessly upload new configuration bitstreams to remote sensor nodes using a protocol developed to provide full remote access to the flash memory of the sensor nodes. Results show that the FPGA can be remotely reconfigured in 1.35 s using a bitstream stored in the flash memory. The proposed scheme uses negligible amount of FPGA logic and does not require a dedicated microcontroller or softcore processor. It can help develop truly flexible IoT, where the FPGAs on thousands of sensor nodes can be reprogrammed or new configuration bitstreams uploaded without requiring physical access to the nodes.

A Run-Time Reconfiguration Method for an FPGA-Based Electrical Capacitance Tomography System

A desirable feature of an electrical capacitance tomography system is the adaptation possibility to any sensor configuration and measurement mode. A run-time reconfiguration of a system for electrical capacitance tomography is presented. An original mechanism is elaborated to reconfigure, on the fly, a modular EVT4 system with multiple FPGAs installed. The outlined system architecture is based on FPGA programmable logic devices (Xilinx Spartan) and PicoBlaze soft-core processors. Soft-core processors are used for communication, measurement control and data preprocessing. A novel method of FPGA partial reconfiguration is described, in which a PicoBlaze soft-core processor is used as a reconfiguration controller. Behavioral reconfiguration of the system is obtained by providing run-time access to the program code of a soft-core control processor. The tests using EVT4 hardware and different algorithms for tomographic scanning were performed. A test object was measured using 2D and 3D sensors. The time and resources required for the examined reconfiguration procedure are evaluated.

Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors

With the rise of edge computing and the advancement of cryptography and error correction codes, portable device processors are demanded to increase their efficiency to run different applications and algorithms. To improve the performance of microprocessors, manufacturers add coprocessors or custom instructions to execute specific operations. Two essential contributions related to the customization of the instruction set are presented in this article. The first is the operator’s improvement for Galoid-field (GF) arithmetic, where the polynomial reduction module is fully programmable using a new zero-padding technique. The second is resource sharing between different operators within the microprocessor. This paper additionally describes two programmable and area-efficient GF arithmetic logic units for soft-core processors. The logic utilization is reduced from 16.67% to 37.00% for the combinational solution and 35.59% to 88.38% for the sequential solution, in ranges from 4 to 64 bits, running on a Kintex-7T field-programmable gate array (FPGA).