So-called Side-channel Attacks Research Articles

On some relations of SCA-related properties of S-box under the Hamming weight leakage mode

Abstract— Physical implementations of cryptographic algorithms are vulnerable to so-called side-channel attacks, in which sensitive information can be recovered through the analysis of the leakages produced by the operating device. In the particular case of block ciphers, substitution boxes are often the target of such attacks, as they are the main nonlinear component of the cipher. Literature survey contains some definitions of theoretical properties to measure the resistance provided by substitution boxes with respect to the imminent threat of side-channel attacks. The fundamental questions we board in this paper are: are all these properties related? And if so, what can we tell of their relation? We pretend to bring some clarification to this subject using some well-known side-channel related properties of S-box.

TSCL: A time–space crossing location for side-channel leakage detection

Cryptographic algorithms on devices are vulnerable to the so-called side-channel attacks(SCAs). The security evaluation of the cryptographic circuits is necessary to provide earlier leakage detection before manufacture. However, the complexity of locating leakage points is high because of the long execution time and the large scale of the circuit. To overcome this limitation, we propose an efficient leakage location method named time–space crossing location(TSCL) to locate the leakage in the hardware design, which combines the dynamic and static analysis. Unlike the traditional detection methods, we analyze the design features and power consumption characteristics of implementation to construct the candidate set on dynamic detection while further verifying candidate leakage points in the static detection stage. The t -test is known as a dynamic detection method to decrease the time of formal verification based on label propagation. The design features decrease the complexity of dynamic detection while the results of power consumption analysis promote static detection. We confirm the efficiency of the proposed method on unprotected and masking implementation of AES. Moreover, TSCL can be regarded as a third-party tool in the existing EDA tools of hardware design.

Fast Algebraic Immunity of Boolean Functions and LCD Codes

Nowadays, the resistance against algebraic attacks and fast algebraic attacks are considered as an important cryptographic property for Boolean functions used in stream ciphers. Both attacks are very powerful analysis concepts and can be applied to symmetric cryptographic algorithms used in stream ciphers. The notion of algebraic immunity has received wide attention since it is a powerful tool to measure the resistance of a Boolean function to standard algebraic attacks. Nevertheless, an algebraic tool to handle the resistance to fast algebraic attacks is not clearly identified in the literature. In the current paper, we propose a new parameter to measure a Boolean function's resistance to fast algebraic attack. We also introduce the notion of fast immunity profile and show that it informs both on the resistance to standard and fast algebraic attacks. Further, we evaluate our parameter for two secondary constructions of Boolean functions. Moreover, A coding-theory approach to the characterization of perfect algebraic immune functions is presented. Via this characterization, infinite families of binary linear complementary dual codes (or LCD codes for short) are obtained from perfect algebraic immune functions. Some of the binary LCD codes presented in this paper are optimal. These binary LCD codes have applications in armoring implementations against so-called side-channel attacks (SCA) and fault non-invasive attacks, in addition to their applications in communication and data storage systems.

Power Side-Channel Attack Analysis: A Review of 20 Years of Study for the Layman

Physical cryptographic implementations are vulnerable to so-called side-channel attacks, in which sensitive information can be recovered by analyzing physical phenomena of a device during operation. In this survey, we trace the development of power side-channel analysis of cryptographic implementations over the last twenty years. We provide a foundation by exploring, in depth, several concepts, such as Simple Power Analysis (SPA), Differential Power Analysis (DPA), Template Attacks (TA), Correlation Power Analysis (CPA), Mutual Information Analysis (MIA), and Test Vector Leakage Assessment (TVLA), as well as the theories that underpin them. Our introduction, review, presentation, and survey of topics are provided for the “non expert”, and are ideal for new researchers entering this field. We conclude the work with a brief introduction to the use of test statistics (specifically Welch’s t-test and Pearson’s chi-squared test) as a measure of confidence that a device is leaking secrets through a side-channel and issue a challenge for further exploration.

Classical Leakage Resilience from Fault-Tolerant Quantum Computation

Physical implementations of cryptographic algorithms leak information, which makes them vulnerable to the so-called side-channel attacks. The problem of secure computation in the presence of leakage is generally known as leakage resilience. In this work, we establish a connection between leakage resilience and fault-tolerant quantum computation. We first prove that for a general leakage model, there exists a corresponding noise model in which fault tolerance implies leakage resilience. Then we show how to use constructions for fault-tolerant quantum computation to implement classical circuits that are secure in specific leakage models.

Uniform Montgomery multiplier

As the importance of the modular arithmetic in public-key systems remains, the pursuits of sophisticated cryptographic engineering continue in designing improved architectures for realizing modular arithmetic. This sophistication does not only involve the high-performance, low-power or area-aware optimizations, but also includes secure or hardened realizations, immune against the so-called side-channel attacks. Among these, simple power analysis attack (SPA) requiring only one or a few power traces of the cryptographic activity is considered as the most dangerous treat for security. This study concentrates on implementing SPA-resistant Montgomery multipliers which are the key ingredients in designing substantial cryptosystems. We introduce new encoding schemes that allow multiplication with the operands having no zero digits. Naturally, such encodings result in a homogeneous multiplication in which accumulation needs equivalent computational work. Moreover, in order to layout more secure and timing-independent multipliers, we impose the I/O requirements that resulting Montgomery multipliers do not need extra final reduction. Finally, as proposed methods allow architectures suitable for word serial processing, a memory performance trade-off is possible for constraint environments.

Side-channel protected MPSoC through secure real-time networks-on-chip

The integration of Multi-Processors System-on-Chip (MPSoCs) into the Internet-of-Things (IoT) context brings new opportunities, but also represent risks. Tight real-time constraints and security requirements should be considered simultaneously when designing MPSoCs. Network-on-Chip (NoCs) are specially critical when meeting these two conflicting characteristics. For instance the NoC design has a huge influence in the security of the system. A vital threat to system security are so-called side-channel attacks based on the NoC communication observations. To this end, we propose a NoC security mechanism suitable for hard real-time systems, in which schedulability is a vital design requirement. We present three contributions. First, we show the impact of the NoC routing in the security of the system. Second, we propose a packet route randomisation mechanism to increase NoC resilience against side-channel attacks. Third, using an evolutionary optimisation approach, we effectively apply route randomisation while controlling its impact on hard real-time performance guarantees. Extensive experimental evidence based on analytical and simulation models supports our findings.

Complementary Dual Algebraic Geometry Codes

Linear complementary dual (LCD) codes is a class of linear codes introduced by Massey in 1964. LCD codes have been extensively studied in literature recently. In addition to their applications in data storage, communications systems, and consumer electronics, LCD codes have been employed in cryptography. More specifically, it has been shown that LCD codes can also help improve the security of the information processed by sensitive devices, especially against so-called side-channel attacks (SCA) and fault non-invasive attacks. In this paper, we are interested in the construction of particular algebraic geometry (AG) LCD codes which could be good candidates to be resistant against SCA. We firstly provide a construction scheme for obtaining LCD codes from elliptic curves. Then, some explicit LCD codes from elliptic curve are presented. MDS codes are of the most importance in coding theory due to their theoretical significance and practical interests. In this paper, all the constructed LCD codes from elliptic curves are MDS or almost MDS. Some infinite classes of LCD codes from elliptic curves are optimal due to the Griesmer bound. Finally, we introduce a construction mechanism for obtaining LCD codes from any algebraic curve and derive some explicit LCD codes from hyperelliptic curves and Hermitian curves.

Retrieving Lost Efficiency of Scalar Multiplications for Resisting against Side-Channel Attacks

At the elliptic curve cryptosystems (ECC) implementation stage, a ma jor concern is securing scalar multiplications against so-called side-channel attacks (SCA). Existing s olutions reach the goal by inserting dummy operations (typically increase 33% computational costs) based on commonly-used binary method , which largely increases the computational costs and prohibits the deployment of ECC in computation resource-restricted devices . In this paper, we for the first time propose a secure scalar multiplication method that does not penalise the computational cost compared to binary method. We partition the bit string of the scalar in half and extract ing the common substring from the two parts based on bit-wise logical operations, so as to save the number of point additions required for the computation of the common substring. Computational results demonstrate th e proposed method remains approximately the same computational cost as binary method. The side-channel experiments prove that the proposed method is secure against SSCA . Also, we use the randomization technique to secure our method against differential SCA (DSCA).

A digital design flow for secure integrated circuits

Small embedded integrated circuits (ICs) such as smart cards are vulnerable to the so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power consumption, execution time, electromagnetic radiation, and other information leaked by the switching behavior of digital complementary metal-oxide-semiconductor (CMOS) gates. This paper presents a digital very large scale integrated (VLSI) design flow to create secure power-analysis-attack-resistant ICs. The design flow starts from a normal design in a hardware description language such as very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) or Verilog and provides a direct path to an SCA-resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. The basis for power analysis attack resistance is discussed. This paper describes how to adjust the library databases such that the regular single-ended static CMOS standard cells implement a dynamic and differential logic style and such that 20 000+ differential nets can be routed in parallel. This paper also explains how to modify the constraints and rules files for the synthesis, place, and differential route procedures. Measurement-based experimental results have demonstrated that the secure digital design flow is a functional technique to thwart side-channel power analysis. It successfully protects a prototype Advanced Encryption Standard (AES) IC fabricated in an 0.18-mum CMOS

Recovering lost efficiency of exponentiation algorithms on smart cards

At the RSA cryptosystem implementation stage, a major security concern is resistance against so-called side-channel attacks. Solutions are known but they increase the overall complexity by a non-negligible factor (typically, a protected RSA exponentiation is 133% slower). For the first time, protected solutions are proposed that do not penalise the running time of an exponentiation.