SnAg Bumps Research Articles

A Novel Chip-Join Assembly Using Heterogeneous Sn-Ag Bumps

In this article, a flip-chip assembly using a heterogeneous solder bump structure is studied. The metallurgical and shape evolution, from bump fabrication through final assembly, is presented, characterized, and discussed. Aiming for lower residual stress during flip-chip assembly, a sequentially plated bump is fabricated to ensure a ductile low Ag content solder proximate to the fragile chip back end of line (BEOL) layers while providing a separate solder portion with a high Ag content. Such a heterogeneous structure is enabled by the integration of a Ni cap barrier within the sequential electroplating process that serves to prevent Ag diffusion between the two distinct solder portions. The heterogeneous structure is shown to remain intact through the chip join operation, thereby proposing improved BEOL integrity during joint solidification. Further, the cap barrier induces a unique, pillar-like solder structure that provides the opportunity to optimize fine pitch assembly processes without the use of a stiff Cu-pillar layer. Finally, the cap barrier is shown to successfully break down using an additional reflow after underfill reinforcement, thus homogenizing the structure into a high-Ag content solder to optimize electromigration resistance.

14nm Chip Package Interaction (CPI) Technology Development

Abstract This paper presents the 14 nm chip and package interaction (CPI) challenges and development by using 140 um minimum pitch with SnAg bump in flip chip BGA package. We evaluated 14 nm back-end-of-line (BEOL) film strength/structure / adhesion with large die size of 21×21 mm2 and optimized bumping technology by passing all the CPI reliability tests (QTC, Precon, UBHAST, TCJ, MSV, and HTS) with following the JEDEC standard. We also evaluated assembly with different bump foot print at 140um bump pitch with SnAg bump, and no assembly issues were encountered. Crack stop plays very critical role in defending the crack propagation into the die active area. In our development, we observed reliability failure with severe test condition TCG (−45°C to 125°C), but passed TCJ (0°C to 100°C) with single wall crack stop on the large die size. With increasing crack stop width which enhanced the mechanical strength of crack stop, both TCG and TCJ passed. So it is strongly recommended to use wider crack stop for large dies to eliminate any failures.

Development of n+-in-p planar pixel quadsensor flip-chipped with FE-I4 readout ASICs

We have developed flip-chip modules applicable to the pixel detector for the HL-LHC. New radiation-tolerant n+-in-p planar pixel sensors of a size of four FE-I4 application-specific integrated circuits (ASICs) are laid out in a 6-in wafer. Variation in readout connection for the pixels at the boundary of ASICs is implemented in the design of quadsensors. Bump bonding technology is developed for four ASICs onto one quadsensor. Both sensors and ASICs are thinned to 150 μm before bump bonding, and are held flat with vacuum chucks. Using lead-free SnAg solder bumps, we encounter deficiency with large areas of disconnected bumps after thermal stress treatment, including irradiation. Surface oxidation of the solder bumps is identified as a critical source of this deficiency after bump bonding trials, using SnAg bumps with solder flux, indium bumps, and SnAg bumps with a newly-introduced hydrogen-reflow process. With hydrogen-reflow, we establish flux-less bump bonding technology with SnAg bumps, appropriate for mass production of the flip-chip modules with thin sensors and thin ASICs.

Thin hybrid pixel assembly with backside compensation layer on ROIC

The entire ATLAS inner tracking system will be replaced for operation at the HL-LHC . This will include a significantly larger pixel detector of approximately 15 m2. For this project, it is critical to reduce the mass of the hybrid pixel modules and this requires thinning both the sensor and readout chips to about 150 micrometres each. The thinning of the silicon chips leads to low bump yield for SnAg bumps due to bad co-planarity of the two chips at the solder reflow stage creating dead zones within the pixel array. In the case of the ATLAS FEI4 pixel readout chip thinned to 100 micrometres, the chip is concave, with the front side in compression, with a bow of +100 micrometres at room temperature which varies to a bow of −175 micrometres at the SnAg solder reflow temperature, caused by the CTE mismatch between the materials in the CMOS stack and the silicon substrate. A new wafer level process to address the issue of low bump yield be controlling the chip bow has been developed. A back-side dielectric and metal stack of SiN and Al:Si has been deposited on the readout chip wafer to dynamically compensate the stress of the front side stack. In keeping with a 3D process the materials used are compatible with Through Silicon Via (TSV) technology with a TSV last approach which is under development for this chip. It is demonstrated that the amplitude of the correction can be manipulated by the deposition conditions and thickness of the SiN/Al:Si stack. The bow magnitude over the temperature range for the best sample to date is reduced by almost a factor of 4 and the sign of the bow (shape of the die) remains constant. Further development of the backside deposition conditions is on-going with the target of close to zero bow at the solder reflow temperature and a minimal bow magnitude throughout the temperature range. Assemblies produced from FEI4 readout wafers thinned to 100 micrometres with the backside compensation layer have been made for the first time and demonstrate bond yields close to 100%.

Study of Void Formation Mechanism in Electroplated SnAg Solder Bump

AbstractSnAg electroplating method is widely used in the formation of LF solder bump for flip chip connection. While electroplating is able to form void free solder bump in a suitable operating condition, void may occur suddenly when used in mass production. This study aims at understanding the gas source in the void of electroplated SnAg solder bumps and determining the manufacturing process factors which affect the void formation.There are various types of void formation mode. One mode is H2 gas generation on cathode surface during electroplating. Both the cross-sections of solder bumps, as well as an analysis data of the gas in the void taken by the TDS (Thermal Desorption Spectrometry) were evaluated. The cross-section of the solder bump which contains void due to the reflow process revealed the existence of several tens of nm to several μm size pits in the solder bump before reflow. TDS analysis indicates that the pits consisted of mainly H2O, H2 and the decomposition of organics. A possible void formation mechanism is the evaporation of H2 gas and the incorporated electrolyte solution in the bump by reflow. These pits in the solder were caused by various process parameters. One of the causes is due to the setting of the current density in the SnAg electroplating process being inappropriate. The current density should be adjusted corresponding to the electrolyte performance and bump design such as PR thickness, opening diameter and bump density. The computer simulation demonstrated that a thick PR limits the diffusion of the Sn2+ ions into via holes and having the current density too high causes a lack of Sn2+ ions on the cathode surface and causes H2 gas generation.The other mode of void formation is Ag displacement of the under bump metallization (UBM) surface in dwell time in the SnAg electrolyte solution before the start of plating. The adjustment of each process parameter can eliminate the source of the void and achieve a high reliability of SnAg bump formation.

Formation Mechanism of Porous Cu3Sn Intermetallic Compounds by High Current Stressing at High Temperatures in Low-Bump-Height Solder Joints

Electromigration tests of SnAg solder bump samples with 15 μm bump height and Cu under-bump-metallization (UBM) were performed. The test conditions were 1.45 × 104 A/cm2 at 185 °C and 1.20 × 104 A/cm2 at 0 °C. A porous Cu3Sn intermetallic compound (IMC) structure was observed to form within the bumps after several hundred hours of current stressing. In direct comparison, annealing alone at 185 °C will take more than 1000 h for porous Cu3Sn to form, and it will not form at 170 °C even after 2000 h. Here we propose a mechanism to explain the formation of this porous structure assisted by electromigration. The results show that the SnAg bump with low bump height will become porous-type Cu3Sn when stressing with high current density and high temperature. Polarity effects on porous Cu3Sn formation is discussed.

Development of chip-on-flex bonding using Sn-based bumps and non-conductive adhesive

We developed a reliable and low cost chip-on-flex (COF) bonding technique using Sn-based bumps and a non-conductive adhesive (NCA). Two types of bump materials were used for the bonding process: Sn bumps and Sn–Ag bumps. The bonding process was performed at 180°C for 10s using a thermo-compression bonder after dispensing the NCA. Sn-based bumps were easily deformed to contact Cu pads during the bonding process. A thin layer of Cu6Sn5 intermetallic compound was observed at the interface between Sn-based bumps and Cu pads. After bonding, electrical measurements showed that all COF joints had very low contact resistance, and there were no failed joints. To evaluate the reliability of COF joints, high temperature storage tests (150°C, 1000h), thermal cycling tests (−25°C/+125°C, 1000 cycles) and temperature and humidity tests (85°C/85% RH, 1000h) were performed. Although contact resistance was slightly increased after the reliability test, all COF joints passed failure criteria. Therefore, the metallurgical bond resulted in good contact and improved the reliability of the joints.

Comparison of Cu-Sn Compound Formation Between Snag and Pure Sn Solder Bumps by EBSD

Anisotropic behavior of Sn based solder during electromigration has been studied by many researchers, and it is very important to control the microstructure for more reliable bump joints[1]. Here, we prepared various SnAg bumps with different Ag concentrations including pure Sn[2]. Unary electroplating has various advantages such as easy handling bath, negligible bump composition and maintaining equipment with securing about environmental health and safety issue.Figure 1 shows our preliminary experiments for the cross-sectional EBSD and EDS measurement of Cu pillar with pure Sn bump, and it is reflowed at 235°C for 6 min. In this study, we will report comparison of Sn microstructures according to various Ag inclusions by using cross-sectional EBSD(electron backscattered diffraction) analysis and EDS(energy dispersive spectroscopy) measurement. We carried out multiple reflows at various atmosphere how this impact IMC(intermetallic compound) growth along with microstructures. Through this crystallographic aspect approach, we will present optimum condition for resistance of electro migration and void formation.[1] Yiwei Wang, Kuan H. Lu, Vikas Gupta, Leon Stiborek, Dwayne Shirley, Seung-Hyun Chae, Jay Im, Paul S. Ho, J. Mater. Res., 27, 1131 (2008)[2] Ui-Hyoung Lee, Moongi Cho, Woojin Choi, Ha-Young You, Jinho Choi and Jaihyung Won, 224th ECS meeting, San Francisco, Oct. (2013)

Fabrication of a membrane probe card using transparent film for three-dimensional integrated circuit testing

We fabricated a novel membrane probe card using a transparent film for the chip-level testing of a three-dimensional integrated circuit (3D-IC). In this membrane probe card, 20-µm-pitch Ni–Au contact bumps and Ti–Au wirings were formed on a biaxially oriented poly(ethylene naphthalate) (PEN) film. This probe card was fabricated using a low-temperature (lower than 100 °C) process, which included through-hole formation by a laser beam, photolithography, Ar plasma irradiation to improve the adhesion between the PEN film and the metal wiring, Ti–Au sputtering, Au electroplating, Ni electroplating, and electroless Au plating. The probe card has three characteristics: (1) fine pitch probes. (2) small-gap alignment between the probe card and the tested chip owing to transparency of the probe card, which offers high accurate probing. (3) damageless (low-load) probing owing to the compliancy of the PEN film. Using this probe card, we performed pre-bond testing of a 10-mm-square chip with Cu–SnAg bumps. The probing to 20-µm-pitch, 1,000 Cu–SnAg bumps and the pre-bond testing of thin Si chips were realized without causing damage to the chip even when chip was very thin (50 µm thick).

Non-PR Sn-3.5Ag Bumping on a Fast Filled Cu-Plug by PPR Current

The electroplating of Sn-3.5 wt% Ag bumps without a photoresist (PR) mould on a Si chip was performed to reduce the production steps and cost for 3-D chip stacking. The electroplating characteristics of Sn-Ag and Sn-Ag bump growth were examined. The Sn-Ag bumps were electroplated on the Cu-plugged TSVs (through-silicon vias) of a Si chip. The Cu plug in the via was produced using a high-speed Cu filling process by a periodic pulse reverse current waveform. The electroplating current was supplied to the exposed Cu surface in the TSVs to produce the Sn-3.5Ag bumps. As the experimental results show, the Sn-3.5Ag bumps were fabricated successfully without a PR mould, with no serious defects by electroplating. The Ag contents in the Sn-Ag bump decreased with increasing current density. Besides, the bump height and width increased with increasing plating time. The bump width grew isotropically because of the absence of a PR mould. The Sn-3.55 wt% Ag bumps were obtained at a current density of -55 mA/cm2 for 20 min on the Cu plugs.

Fabrication of electroplate Sn-Ag bumps without a lithography process for 3D packaging

A new process of electroplate Sn-Ag bumping without a patterned photo resist (PR) mould on a Si chip for 3-dimensional packaging was investigated. The electroplating characteristics of the Sn-Ag electrolyte and the bump growth were examined. The substrate was a Si die with a thickness of 70 μm in which the through-Si-vias (TSVs) were plugged with Cu. The Sn-Ag bumps were electroplated on the Cu-plugged vias of the Si-chip with an increasing DC current density and plating time. The experimental results of the polarization curve showed that Sn-Ag had two reduction potentials, namely, a Ag reduction starting potential of −0.387 V and a Sn and Ag co-reduction potential of −0.474 V. The Sn-Ag bumps were fabricated successfully without serious defects by electroplating without a PR mould. The bump height and width increased to 14.5 and 72.0 μm, respectively, when the plating time was raised to 15 min. The growth of the bump width was caused by the absence of the PR mould. The Sn-Ag bump exhibited rivet-head morphology in 15 min plating, and no short circuit between neighboring bumps was found. The near eutectic composition of Sn-3.24 wt%Ag bump was obtained by plating at −30 mA/cm2 for 15 min.

Development of Large Die Fine-Pitch Cu/Low-$k$ FCBGA Package With Through Silicon via (TSV) Interposer

The continuous push for smaller bump pitch interconnection in line with smaller Cu/low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in fine-pitch wiring due to its technology limitation, and the cost of fabricating finer pitch organic substrate is higher. To address these needs, Si interposer with through silicon via (TSV) has emerged as a good solution to provide high wiring density interconnection, and at the same time to minimize coefficient of thermal expansion mismatch to the Cu/low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> chip that is vulnerable to thermal-mechanical stress and improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21 × 21 mm Cu/low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> test chip on flip chip ball grid array (FCBGA) package. The Cu/low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> chip is a 65-nm nine-metal layer chip with 150-μm SnAg bump pitch of total 11 000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25 × 25 × 0.3 mm with CuNiAu as under bump metallization on the top side and SnAgCu bumps on the underside. The conventional bismaleimide triazine substrate size is 45 × 45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free solder bumps and underfill have been set up. The FCBGA samples have passed moisture sensitivity test and thermal cycling reliability testing without failures in underfill delamination and daisy chain resistance measurements.

Reliability Investigation of Large GaAs Pixel Detectors Flip-Chip-Bonded on Si Readout Chips

Lead-free reflow soldering techniques applying AuSn as well as SnAg electroplated bumps were chosen for the evaluation of the flip-chip-bonding process for X-ray pixel detectors. Both solders can be used in pick-and-place processes with a subsequent batch reflow suitable for high-volume production. AuSn solder was selected because of its fluxless bondability, good wettability, and self-alignment process capability, and SnAg solder was chosen for its more ductile behavior and lower yield stress compared to AuSn. GaAs test chips with daisy chain and four-point Kelvin probe structures together with appropriate Si test substrates were designed, manufactured, and bumped. Test chips with 55 and 170 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\rm m}$</tex></formula> pitch and different chip sizes (maximum 16.3 down to 4 mm square) were used. AuSn bumps were deposited by electroplating (first Au and a thin Sn layer on top). Thick Au bonding pads were formed on substrate side in case of AuSn bumps. Two under-bump metallizations (UBMs) were used for the SnAg samples: Cu and Ni. Finite element (FE) simulation was performed comparing AuSn and SnAg interconnections and different chip sizes. A local model was designed for bump interconnection and a global octant model for the assembly process. Very high values were calculated for the peel stress using AuSn bumps. SnAg bumps, on the other hand, showed 3–5 times reduction in peel stress depending on the chip size. A flip-chip-bonding process setup was carried out for both solder types (AuSn as well as SnAg), with an analysis of the samples by electrical measurements, cross-sectioning, and scanning electron microscopy. Due to the different coefficients of the thermal expansion of GaAs and Si, no stable bonding process was obtained for the AuSn modules as already predicted by the FE simulation. With increasing chip size, failures like pad lift or cracking of the GaAs bulk material were observed. In comparison, the SnAg samples showed good bonding results. This technology was then selected to assemble test modules for thermal cycling between <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}{55}$</tex></formula> and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${+}{\rm 125}^{\circ}{\rm C}$</tex></formula> comparing Cu and Ni as UBM. The modules were qualified by electrical monitoring as well as cross sectioning. More than 200 cycles were reached by the 55- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\rm m}$</tex></formula> pitch 16.3-mm square bonded GaAs chips and about 400 by the smallest 4-mm square chips, although no underfilling was used. The dominant failure mode was fracture within the solder. Based on experimental and simulation results, functional 256 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,\times\,$</tex></formula> 256 GaAs pixel detectors with a chip size of 14 mm <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,\times\,$</tex></formula> 14 mm were assembled on Si readout chips using SnAg bumps on a Cu UBM. Finally, these X-ray image sensors were wire-bonded to a printed circuit board and successfully tested, showing an yield (at the pixel level) of about 98%.

A Comparison of Flip Chip Bump Electromigration Reliability for Cu Pillar, High Pb, SnAg, and SnPb Bump Structures

Electromigration failure in flip-chip bumps has emerged as a major reliability concern due to potential elimination of Pb from flip-chip bumps and a continuous drive to increased IO density resulting in a reduction of bump size and pitch. Traditionally, flip-chip interconnects incorporate a high Pb bump soldered with a SnPb eutectic paste to the substrate or another die. However, because of RoHS directives, the industry is responding with Pb free bump development, such as SnAg bump with SAC solder or Cu Pillar with SAC/SnAg solder. Although a number of recent publications deal with electromigration reliability of Pb free and Cu Pillar bumps, a gap exists in terms of their performance comparison with high Pb and SnPb solder on the same bump geometry. The available test data is based on different test vehicles and it becomes difficult to determine the relative performance of these different metallurgies under accelerated test conditions. In addition, not all published data provides the essential parameters of Black's equation to determine the performance and reliability for actual use conditions. This paper attempts to fill this gap by comparing electromigration performance of High Pb, SnPb eutectic, SnAg, and Cu Pillar bumps using the same test vehicle. A special test vehicle was designed with daisy chain structures for electromigration testing and the packages we assembled on test cards. The testing is being done using five (5) stress conditions (combination of current and temperature) to estimate the current density exponent, n, and activation energy, Ea, parameters for Black's equation. The reliability data as well as failure modes for these bump metallurgies will be presented in the paper.

Evaluation of Cu-bumps with lead-free solders for flip-chip package applications

Low cost electroplated Cu-bump with environmental friendly Sn solder was developed for flip-chip applications. The seed layer used was Ti/WN x /Ti/Cu where WN x was used as the Cu diffusion barrier and Ti was used to enhance the adhesion between bump and the chip pad. Thick negative photoresist (THB JSR-151N) with a high aspect ratio of 2.4 was used for electroplating of copper bump and Sn solder. The Sn solder cap was reflowed at 225° for 6 min at N 2 atmosphere. No wetting phenomenon was observed for the Sn solder as evaluated by energy-dispersed spectroscopy (EDS). The Cu-bump with Ti/WN x /Ti/Cu seed layer not only have higher shear force than the Cu-bump with Ti/Cu seed layer but also has higher resistance to fatigue failure than the Au, SnCu, SnAg bumps.

Sub-100 μm SnAg Solder Bumping Technology and the Bump Reliability

Lead-free solder bumping and its related interconnection and reliability are becoming one of the important issues in today’s electronic packaging industry. In this paper, alloy electroplating was used as SnAg solder bumping process. Multiple reflow was preformed on as-plated solder bumps. Scanning electron microscopy and energy dispersive X-ray analysis were used to investigate the intermetallic compound and microvoids of cross-sectioned solder bump. Shear test was used to evaluate the reliabilities of the SnAg bumps. The 13×13 area-array Sn/3.0Ag solder bumps of 70 μm in height and 90 μm in diameter were fabricated with a smooth and shiny surface and with a uniform distribution of Ag. During multireflow, the scalloped Cu6Sn5 phase grows by a ripening process. Volume shrinkage was the main reason for the formation of microvoids during multireflow. The average shear strength of solder bumps on TiW/Cu under bump metallurgy (UBM) increased with reflow times. The electroplating process is suitable for mass production of well-controlled geometry and uniformity of SnAg solder bumps. Microvoids have trivial negative impacts on the solder bonds. The combination of TiW/Cu UBM and SnAg solder is reliable.

The effects of electroplating parameters on the composition and morphology of Sn-Ag solder

The Sn-Ag solder was electrodeposited from a bath that basically is composed of tin sulfate (SnSO4), silver nitrate (AgNO3), and thiourea (CH4N2S), acting as a complexing agent to silver. The composition and morphology of electrodeposited Sn-Ag solder were studied in terms of silver concentration in bath current density, duty cycle, and additives. It was possible to control silver content in the electrodeposit by means of varying silver concentration in bath and current density. The microstructure and surface morphology of the electrodeposit become finer and smoother with increasing current density. The pulse-current (PC) plating method was applied to compare to the conventional direct-current (DC) plating. Varying duty cycle in PC plating did not change the microstructure in general, but some improvement in surface roughness was observed compared to DC plating. However, the silver composition in the electrodeposit increased with decreasing the duty cycle at a constant current density. An addition of a surface-active agent helped to reduce the surface roughness and the variation of silver content in the electrodeposit. In an optimum condition, eutectic Sn-Ag solder bumps with a fine pitch of 30 µm and height of 15 µm were successfully electroplated. The composition of Sn-Ag bumps was analyzed by energy dispersive x-ray spectrometry (EDS) and wavelength dispersive x-ray spectrometry (WDS) methods, and the surface morphology was characterized by scanning electron microscopy (SEM) and a three-dimensional surface analyzer.

CHARACTERISATION OF ELECTROPLATED EUTECTIC Sn-Ag SOLDER

International Journal of Computational Engineering ScienceVol. 04, No. 03, pp. 733-736 (2003) Poster PapersNo AccessCHARACTERISATION OF ELECTROPLATED EUTECTIC Sn-Ag SOLDERZ. W. ZHONG, K. C. CHAN and Y. H. CHENZ. W. ZHONGNanyang Technological University, School of Mechanical & Production Engineering, Nanyang Avenue, Singapore 639798, Singapore Search for more papers by this author , K. C. CHANMicroFab Technology (S) Pte Ltd, 2 Woodlands Sector 1, Woodlands Spectrum #01-20, Singapore 738068, Singapore Search for more papers by this author and Y. H. CHENNanyang Technological University, School of Mechanical & Production Engineering, Nanyang Avenue, Singapore 639798, Singapore Search for more papers by this author https://doi.org/10.1142/S1465876303002167Cited by:2 Previous AboutSectionsPDF/EPUB ToolsAdd to favoritesDownload CitationsTrack CitationsRecommend to Library ShareShare onFacebookTwitterLinked InRedditEmail AbstractThis paper discusses the effects of electro-deposition processing conditions on the film composition and surface morphology. The rate of Ag deposition onto the bump depends on various processing parameters like current density, agitation and temperature. Among these parameters, the Ag content in the bump was found to be most sesitive to current plating density. At various Ag content, the morphology of the deposited solder was found to be different. This is due to the different types of drain growth at different Ag content. A high content bump was found with a needle-like Ag3Sn structure. This strcuture is believed to be the cause for the reduction in shear strength.Keywords:Sn-Agbump compositionsurface morphologyshear strength References H. Ezawa, M. Miyata and S. Homma, Eutectic Sn-Ag solder bump process for ULSI flip chip technology, Proc. 50th Electronic Components and Technology Conference, USA, (2000) 1095-1100 . Google Scholar S. Arai, H. Akatsuka, N. Kaneko, N. Shinohara and S. Wakabayashi, Sn-Ag solder bump formation for flip-chip bonding using electroplating method, Proc. 2nd International Conference on Electronics Packaging, Japan, (2002) 178-183 . Google Scholar S. Arai, Sn-Ag solder bump forming using electroplating method, Proc. of Symposium on Microjoining and Assembly Technology in Electronics, Japan, (1997) 59-64 . Google ScholarD. W. Hendersonet al., Journal of Material Research 17(11), 2775 (2002). Crossref, Google Scholar FiguresReferencesRelatedDetailsCited By 2Effects of process conditions on reliability, microstructure evolution and failure modes of SnAgCu solder jointsPeriannan Arulvanan, Zhaowei Zhong and Xunqing Shi1 Feb 2006 | Microelectronics Reliability, Vol. 46, No. 2-4Lead‐free PCB assembly and effects of process conditions on the profile and reliability of solder jointsZ.W. Zhong, P. Arulvanan and X.Q. Shi1 Dec 2005 | Soldering & Surface Mount Technology, Vol. 17, No. 4 Recommended Vol. 04, No. 03 Metrics History Keywords Sn-Ag bump compositionsurface morphologyshear strengthPDF download

Pb-free Sn/3.5Ag wafer-bumping process and UBM (under bump metallurgy) study

This paper describes newly defined eutectic SnAg solder bumping process using an alloy electroplating method and the interface reactions between four different types of UBM (under bump metallurgy) layers and eutectic SnAg bumps. In addition, the bumping process and UBM reactions of eutectic SnAg were compared with those of eutectic PbSn which is most commonly used as a solder bumping material.