The progression in the electronics industry is toward further minimization and the global semiconductor assembly community is striving for a robust replacement for leaded solders due to increased environmental regulations. A family of Pb-free solder alloys based on Sn-Ag-Cu (SAC) compositions has shown promise, but due to reliability issues in certain assembly and operating environments, quaternary (Mn, Ni, Zn, and Al-doped SAC) solders are currently under investigation. With more computing power, higher performance is needed for smaller areas. The ball-grid-array (BGA) packaging system with a decreased size, is likely to be replaced by chip-scale packages (CSPs) (i.e. µBGA) and Copper Pillar Bumps (CPBs). There are several methods to form solder bumps such as screen printing, evaporation and electroplating. As the pitch and the bump size decrease, electroplating becomes the only efficient way to fabricate bumps with small size, fine pitch and low cost. Electroplating is considered to be the only feasible technique to form the copper pillar and the solder cap to realize the CPBs. Currently, solder electroplating is limited mainly to binary compound plating and there exist no stable solutions for electroplating of ternary alloys due to a large gap in electrochemical reduction potentials between different elements. For example, in order to perform SAC electroplating Karim et al. had to use sequential plating from two separate binary SnCu and SnAg plating solutions [1]. However, if developed, ternary alloy plating solutions may not be practical under manufacturing conditions considering that it is hard to maintain bath and alloy composition even for binary plating solutions. Obviously the development of a plating solution for quaternary alloy is even less probable. In order to deposit alloy with precise composition, multilayer electroplating method is proposed instead. The method lies in the sequential electroplating of each of the solder components from a separate bath and a consequent reflow to form uniform alloy. Unfortunately to warrantee the reliability the electroplating sequence should be carefully watched [2]. To overcome inter-diffusion limitation and achieve a uniform and fast reflow, low thickness of each layer is necessary and a proportional increase of layers number makes the process time-consuming and impractical from a conventional electroplating point of view due to multiple switching between solution baths. The present work will show how using a new concept in electroplating, based on multiple Dynamic Liquid Drop/Meniscus (DLD/DLM), is possible to realize multilayer approach to plate binary, ternary and even quaternary solder alloy at high throughput, high precision and low cost. The DLD/DLM [3] represents a constantly refreshed confined electrolyte volume in touch with a substrate surface. The plating concept lies in assembling multiple independent DLD/DLM in a sequential array (one or many for each plating component intercalated by a rinse DLD/DLM) into a multiple plating head. Thus scanning the plating head over the wafer surface will allow consequent plating of a layer of each of the component. Each pass of the plating head leads to deposition of the multilayered structure representing consequent components layers (grains) with a required proportion. Total thickness of the alloy depends on the number of passages and can be varied in a wide range. Using the proposed technique various solder compositions were deposited. As a proof-of-concept, SAC305 and SAC405 layers with 30µm thickness were deposited containing more than 350 layers of each element. A detailed investigation of SAC and quaternary SAC+Mn alloys composition will be presented; EDX analysis before and after reflow proving that the high number of layers an homogenous solder is obtained independently of metal deposition sequence and even without reflow. The proposed breakthrough technique offers the unique opportunity to deposit any kind of binary, ternary and quaternary Pb-free alloy solder from single bath solutions without any kind of cross contamination. Such technique poses a key milestone to obtain ternary and/or quaternary Pb-free solder alloy for the CSPs and CPBs allowing to tune the correct solder alloy in order to finally solve reliability issues. [1] Z. S. Karim and J. Martin, “Lead-free solder bump technologies for flip-chip packaging applications”, SMTA (2001). [2] Qinghua Zhao, Anmin Hu, Ming Li, Jiangyan Sun, “Effect of electroplating layer structure on shear property and microstructure of multilayer electroplated Sn-3.5Ag solder bumps” Microelectronics Reliability 53 (2013) 321–326 [3] Konstantin Kholostov, et al. “High uniformity and high speed copper pillar plating technique” IEEE 64th Electronic Components and Technology Conference (ECTC), 2014, 1571-1576 Figure 1 shows the SEM pictures and EDX analysis of SAC 305 μBGA by multiple DLD/DLM technique. Figure 1