SMT Solder Joint Research Articles

Effects of interface cracks on reliability of surface mount technology interconnection in service environment

PurposeSurface mount technology (SMT) is widely used and plays an important role in electronic equipment. The purpose of this paper is to reveal the effects of interface cracks on the fatigue life of SMT solder joint under service load and to provide some valuable reference information for improving service reliability of SMT packages.Design/methodology/approachA 3D geometric model of SMT package is established. The mechanical properties of SMT solder joint under thermal cycling load and random vibration load were solved by 3D finite element analysis. The fatigue life of SMT solder joint under different loads can be calculated by using the modified Coffin–Manson model and high-cycle fatigue model.FindingsThe results revealed that cracks at different locations and propagation directions have different effect on the fatigue life of the SMT solder joint. From the location of the cracks, Crack 1 has the most significant impact on the thermal fatigue life of the solder joint. Under the same thermal cycling conditions, its life has decreased by 46.98%, followed by Crack 2, Crack 4 and Crack 3. On the other hand, under the same random vibration load, Crack 4 has the most significant impact on the solder joint fatigue life, reducing its life by 81.39%, followed by Crack 1, Crack 3 and Crack 2. From the crack propagation direction, with the increase of crack depth, the thermal fatigue life of the SMT solder joint decreases sharply at first and then continues to decline almost linearly. The random vibration fatigue life of the solder joint decreases continuously with the increase of crack depth. From the crack depth of 0.01 mm to 0.05 mm, the random vibration fatigue life decreases by 86.75%. When the crack width increases, the thermal and random vibration fatigue life of the solder joint decreases almost linearly.Originality/valueThis paper investigates the effects of interface cracks on the fatigue life and provides useful information on the reliability of SMT packages.

Study on Intelligent Analysis of the Causes of SMT Solder Joint Defects Based on Fuzzy Neural Network

By determining membership function of the input parameters and selecting defuzzification method, the evaluation model which can be used to intelligent analyzing the causes of SMT solder joint defects was set up. The fuzzy neural network was trained by using the output variables of the training samples from intelligent discrimination as the input variables of training samples of fuzzy neural network. The fuzzy neural network was tested by using the output variables of the testing samples from intelligent discrimination as the input variables of testing samples of fuzzy neural network. The results show that by using the evaluation model the cause of SMT solder joint defects can be analyzed intelligently and the results of intelligently analysis are reasonable, the evaluation model can be used practically.

Study on the SMT Chip Resistor Solder Joint Two-Dimensional Quality of Information Extraction Based on VC++

This paper introduces the content included in two-dimensional quality information of the SMT solder joint and illustrates the basic principle of extracting two-dimensional information quality of SMT solder joint .By explaining the basic theory and principles and combining with example, the implemention of extracting methods and steps are discussed.The extraction algorithms carry out in VC + + programming, And this lay a good groundwork for follow-up intelligent analysis of solder joint.

Fatigue of SMT solder joint including torsional curvature and chip location optimization

The objective is to find whether fatigue of the solder joint or the location of the chip is related to the curvature and torsional curvature when SMT solder joints are under vibration or shock condition. However, the torsional curvature is always omitted. In this paper the relationship of curvature and torsional curvature is argued, and it is found that the quantity of the curvature is closer to that of the torsional curvature and shows that omitting the torsional curvature is not accurate. Also, the fatigue of the solder joint including torsional curvature is obtained. One kind of SMT printed circuit board (PCB) used in aviation and spaceflight has been obtained to test its modes. According to the modal results, the location of the SMT assembly is not very suitable and the reliability of SMT solder joints will decrease, which will make an unreasonable catastrophe appear. Meanwhile, the location optimization including curvature and torsional curvature is considered and four areas are obtained in the PCB to locate the chip for increasing the fatigue of solder joints. In this paper the results obtained by assuming the PCB is simply supported in its four boundary. The other fixed condition will be calculated using a similar method.

Vibration fatigue experiments of SMT solder joint

The low-cycle fatigue induced by thermal cycling is the major concern in the reliability of SMT for electronic packaging; however, dynamic loading effects on solder joint fatigue life have not been thoroughly investigated. In fact, the high-cycling fatigue induced by vibration can also contribute a significant effect. In certain circumstances it can become a dominant failure case when semiconductor devices are used in vibration environment. In this paper, a series of vibration fatigue experimental vehicles including PBGA256 assembly and FCBGA1521 assembly were conducted. After these experiments, a new phenomenon of cracks of solder joints have been detected and given a reasonable reason, which could lead to a new concept of solder joints' fatigue.

Aging studies of Cu-Sn intermetallic compounds in annealed surface mount solder joints

This is the second in a series of investigations aimed at studying the effect of Cu-Sn intermetallic compound on the reliability of surface mount solder joints. Our previous investigation revealed the formation kinetics and characteristics of Cu-Sn intermetallic compounds in LCCC surface mount solder joints during IR-reflow soldering. The present study focuses on the solid state growth of the interfacial Cu-Sn intermetallic compound in LCCC surface mount solder joints under prolonged annealing at elevated temperature. A thick Cu-Sn IMC layer at the Sn-Pb solder/Cu interface of a surface mount solder joint (which can be achieved by prolonged storage at high temperature or after long term operation of modern SMT electronic assemblies) makes the interface more sensitive to stress and may eventually lead to fatigue failure of all SMT solder joint. The microstructural morphology of the Cu-Sn IMC layer at the solder/Cu pad interface in all annealed LCCC surface mount solder joints is duplex and consists of /spl eta/-phase Cu/sub 6/Sn/sub 5/ and /spl epsi/-phase Cu/sub 3/Sn IMC. Both Cu-Sn IMC phases thicken as the aging time increases. On the other hand, at the interface close to the component metallization, the growth of both the /spl eta/- and /spl epsi/-phase were showed to be suppressed, with more pronounced effect on /spl epsi/-phase, by Ni originating from the metallization. The mean total layer thickness was found to increase linearly with the square root of aging time and the growth was faster for higher annealing temperature. The activation energy for the growth of interfacial Cu-Sn IMC layers and the pre-exponential factor, D/sub o/, for diffusion were calculated to be 1.09 eV and 1.68/spl times/10/sup -4/ m/sup 2//s respectively for the 0805 LCCC surface mount solder joint using eutectic Sn-Pb solder. These values are useful in predicting the thickness of interfacial Cu-Sn IMC layers in real surface mount solder joints in electronic assemblies after prolonged operation and hence the reliability factor of the solder joint attributed to the interfacial Cu-Sn IMC layer. Finally, the pad size and quantity of Sn-Pb solder employed in LCCC surface mount solder joints were shown to have an insignificant effect on the solid state growth rate for the interfacial Cu-Sn IMC layers.

Effects of Voids and Their Interactions on SMT Solder Joint Reliability

Several finite element models were proposed to investigate the effects of voids and their interactions on SMT solder joint reliability in thermal mismatch loading. Both linear elastic analysis and non‐linear and time‐dependent finite element analysis were performed on models with different sizes and locations of voids in solder joints. The focus was on the interactions of the two voids. Various distances between voids are considered. Constitutive equations accounting for both plasticity and creep for one solder material were assumed and implemented in a finite element program. The following observations have been obtained: (i) the stress and strain in a solder joint of two voids are different from those of a one void joint; (ii) the stress and strain reach a maximum for a particular void size and location either along the interface of the solder joint or at the edges of voids; (iii) the initiation of interfacial debonding may be induced by the interaction of the voids; (iv) creep due to thermal cycling has a significant effect on solder joint reliability.

The Influence of Metal Plating of Chip Carriers on Reliability of SMT Solder Joints under Thermal Cycling

An experimental set‐up and a simulated ceramic chip carrier to study SMT solder joint reliability under thermal cycling have been developed. The influence of metal plating of the chip carrier on the reliability of the SMT solder joints under thermal cycling has been studied statistically.