Smooth Sidewall Surface Research Articles

Investigation of the cross-sectional morphology of epitaxial Si nanowires grown by chemical vapor deposition for the fabrication of vertical devices

The interfacial structure of Si nanowire transistors is decisively important to their electronic properties. Smooth sidewall surface of Si nanowires is therefore a prerequisite for the fabrication of vertical transistors. In this study, the axial cross-sectional morphology of epitaxial Si nanowires, which are grown vertically on Si[111] substrates by chemical vapor deposition via the vapour-liquid-solid mechanism, are analyzed by transmission electron microscopy to understand their surface morphology. It is noted that the cross-sections do not exhibit sharp facets. The roughness of the sidewall surface is attributed to precipitation of Si from AuSi liquid droplets. The cross-sectional shape of the Si nanowires is truncated-triangular, but not exactly symmetric. A larger distortion of the cross-sectional shape appears in tilted nanowires. It is also demonstrated that after removing the surface Au, post-growth oxidation of Si nanowires is helpful to rebuild smooth sidewall surface.

High-quality nanodisk of InGaN/GaN MQWs fabricated by neutral-beam-etching and GaN regrowth: towards directional micro-LED in top-down structure

A nanodisk array of blue InGaN/GaN multiple quantum wells was made using neutral beam etching (NBE) followed by GaN regrowth. The NBE-fabricated nanodisk presented a vertical and highly smooth sidewall surface where the InGaN well layers were easily distinguished even with a scanning electron microscope. A high interface quality without any voids or obvious defects was obtained between the nanodisk and the regrown-GaN layer. The nanodisk after regrowth presented a smaller blueshift of photoluminescence emission energy (12 meV) and a substantially higher and almost constant internal quantum efficiency of ∼50% over three orders of magnitude of excitation laser power when compared to the nanodisk before regrowth. This study shows that the process of NBE nanodisk etching followed by GaN regrowth represents a promising step forward in the development of truncated cone-shaped directional micro-LEDs with a buried active region in a top-down structure.

An Optimized FinFET Channel With Improved Line-Edge Roughness and Linewidth Roughness Using the Hydrogen Thermal Treatment Technology

Evolutionary process of a nanoscale FinFET channel during rapid hydrogen thermal treatment is modeled using a kinetic Monte Carlo simulation. In this paper, a novel model of nanoscale FinFET channel is proposed based on the surface diffusion theory of silicon fin structures. The evolution characteristics of fin surface morphology, including line edge roughness (LER), line width roughness, and the cross-correlation coefficient ρ, are investigated in the diffusion process of silicon fin structures at different temperatures and time. All the characteristic parameters can directly affect the carrier transport performance of FinFET. The LER of a silicon fin has been effectively reduced by at least 60%. The linewidth roughness and ρ was also investigated in the evolution of FinFET channel. The results indicate that an optimized nanoscale FinFET channel can be achieved by controlling the migration of surface silicon atoms in rapid hydrogen thermal treatment technology application, yielding atomically smooth sidewall surfaces. The present experimental results are coincided with the simulation results. Thus, such technology plays a crucial role in the application of nanoscale FinFET.

Effect of process parameters on sidewall damage in deep silicon etch

Sidewall damage caused in deep reactive ion silicon etch was investigated by varying etch cycle time, bias power, etch pressure and SF6 flow rate using the Bosch process in a uniquely designed, inductively coupled plasma reactor. The effects of these process parameters on the etch profile and sidewall angle were also studied for high density metal–insulator–metal capacitor structure. By choosing the proper etch cycle time of 2 s, it was observed that the sidewall damage was very sensitive to these etch process parameters. As bias power increased, the sidewall damage increased gradually. Especially, at the bias power of 500 W, a dual bowing shape with severe sidewall damage was seen, which might be due to a combination of two mechanisms: the formation of a redeposition region and a secondary ion etch effect. With increasing pressure, the sidewall damage was not always located in a specific depth range but distributed along almost the whole trench sidewall. An etch pressure below 80 mTorr was favorably recommended for reducing the extent of the sidewall damage. In addition, we found that an appropriate SF6 flow rate was also very beneficial to the realization of a smooth trench sidewall when it was controlled within an appropriate range. Based on these investigations, an acceptable etch condition could be selected to achieve a nearly vertical etch profile as well as a smooth sidewall surface.

Electrowetting Lens Employing Hemispherical Cavity Formed by Hydrofluoric Acid, Nitric Acid, and Acetic Acid Etching of Silicon

We demonstrate the design of an electrowetting lens employing a high-aspect-ratio hemispherical lens cavity and its micro-electro-mechanical-system (MEMS) fabrication process in this study. Our preliminary simulation results showed that the physical and electrical durability of the lens can be improved by the mitigation of stresses on the insulator at the hemispherical cavity. High-aspect-ratio hemispherical cavities with various diameters and very smooth sidewall surfaces were uniformly fabricated on a silicon wafer by a sophisticated isotropic wet etching technique. Moreover, we experimentally investigated the optical properties of the MEMS-based electrowetting lens with the proposed cavity. Two immiscible liquids in the proposed lens cavity were electrostatically controlled with negligible optical distortion and low focal-length hysteresis due to the fully axis-symmetrical geometry and smooth sidewall of the cavity.

Selective growth of GaN nanodots and nanostripes on 6H‐SiC substrates by metal organic vapor phase epitaxy

AbstractGaN nanodots and nanostripes with smooth sidewall surfaces have been selectively grown on 6H‐SiC substrates by metal organic vapor phase epitaxy. By varying the growth reactor pressure, we have been able to grow either isolated nanostructures or laterally overgrown structures. As confirmed by the Raman scattering and X‐ray diffraction techniques, the nanostructures have no influence of step bunching that occurs in the unmasked area of the continuous GaN film. The frequency shift of the E2 optical phonons shows that the residual strain in the nanostripes is relaxed compared to the continuous GaN film. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Additive-Gas Effects on Cl2 Plasma-Based Copper-Etch Process and Sidewall Attack

The influence of the additive gas in plasma-based copper etch and sidewall attack was investigated. The additive gas, such as Ar, , and , drastically changed the plasma-phase chemistry, i.e., the Cl radical concentration, and the ion-bombardment energy, which resulted in changes of the copper chlorination rate and the sidewall roughness. The addition of Ar increased the Cl concentration, which increased the copper chlorination rate and the sidewall attack. The addition of enhanced ion bombardment, which increased the copper chlorination rate. Meanwhile, the addition of diluted the Cl concentration and formed a copper nitride passivation layer, which protected the sidewall and reduced roughness. The addition of induced a fluorocarbon passivation layer, which decreased the copper chlorination rate in the vertical direction but protected the sidewall from vigorous Cl attack and resulted in a smooth sidewall surface. Therefore, the additive gas not only affected the Cu chlorination rate but also influenced sidewall roughness.

Control of Edge Shape, Sidewall Profile, and Sidewall Roughness of the Plasma Etched Copper

A novel plasma-based, room-temperature copper etching method was reported recently. In this paper, the authors investigated the influence of process parameters on the edge shape, sidewall profile and the sidewall roughness of the etched copper patterns. The additive gas, such as CF4 and N2, affects not only the etch rate but also the sidewall profile. With the proper plasma condition, such as power, pressure, and additive gas, copper lines with a vertical profile and smooth sidewall surface were obtained.

Multi-mode Planar Waveguide Fabricated by a (110) Silicon Hard Master

We fabricated (110) silicon hard master by using anisotropic wet etching for embossing. The etching chemical for the silicon wafer was a TMAH <TEX>$25\%$</TEX> solution. The anisotropic wet etching produces a smooth sidewall surface and the surface roughness of the fabricated master is about 3 nm. After spin coating an organic-inorganic sol-gel hybrid material on a silicon substrate, we employed hot embossing technique operated at a low pressure and temperature to form patterns on the silicon substrate by using the fabricated master. We successfully fabricated the multi-mode planar optical waveguides showing low propagation loss of 0.4 dB/cm. The surface roughness of embossed patterns was uniform for more than 10 times of the embossing processes with a single hydrophobic surface treatment of the silicon hard master.

Fabrication of a (100) Silicon Master Using Anisotropic Wet Etching for Embossing

To fabricate a (100) silicon hard master, we used anisotropic wet etching for the embossing. The etching chemical for the silicon wafer was a TMAH 25% solution. The anisotropic wet etching produces a smooth sidewall surface inclined at 54.7˚, and the surface roughness of the fabricated master is about 1 nm. After spin coating an organic-inorganic sol-gel hybrid resin on a silicon substrate, we used the fabricated master to form patterns on the silicon substrate. Thus, we successfully obtained patterns via the hot embossing technique with the (100) silicon hard master. Moreover, by using a single hydrophobic surface treatment of the master, we succeeded in achieving uniform surface roughness of the embossed patterns for more than ten embossments.

Sidewall polishing with a gas cluster ion beam for photonic device applications

We present new developments of a novel surface smoothing method so-called gas cluster ion beam–chemical mechanical polishing (GCIB–CMP). This method employs GCIB with irradiation angles above 60° from the surface normal, and therefore can be applied to the smoothing of sidewalls of a patterned structure. Surface morphology is compared between various optical materials Si, SiO2 and MgF2 irradiated by SF6 clusters. Si and SiO2 surfaces are substantially smoothed at 0.3nm and below in average roughness at incident angles around 80°. We estimate the expected performance improvement of Si and/or SiO2 based photonic devices having smooth sidewall surfaces formed by the GCIB–CMP method.

Etching Characteristics of Silica-Based Optical Waveguide for Planar Lightwave Circuit

We have successfully synthesized high quality silica by using plasma enhanced chemical vapor deposition (PECVD) of tetraethyl orthosilicate (TEOS) precursors. Optical transmission spectroscopy and Fourier transform infrared (FTIR) spectroscopy indicated that, the TEOS/O 2 ratio had pronounced influence on the deposition rate and optical properties for SiO 2 films. Modification on refractive index (n) for the synthesis of single mode optical waveguide can be easily achieved in PECVD process, by addition of TMP in the precursors. Based on this, a Si/SiO 2 /P-SiO 2 /SiO 2 ridge-type waveguide structure could be derived following a photolithography, lift-off and reactive ion etching (RIE) process sequence. In this study, silica etch characteristics of different etching parameters were investigated using CHF 3 /O 2 as the etch gases. Metal mask could offer higher selectivity and yielded smaller deposition of polymer, so that an optical quality ridge structure with high vertical sidewall angle and dimension controllability, and smooth sidewall surface became possible. The results came out that the etching parameters such as RF power and CHF 3 /O 2 ratio had significant influence on the etch rates, etch selectivities and etch profiles. Under optimal etching conditions and post-treatment, a single mode waveguide with vertical etch profile and smooth sidewall could be fabricated successfully.

Etching Characteristics of Silica-Based Optical Waveguide for Planar Lightwave Circuit

We have successfully synthesized high quality silica by using plasma enhanced chemical vapor deposition (PECVD) of tetraethyl orthosilicate (TEOS) precursors. Optical transmission spectroscopy and Fourier transform infrared (FTIR) spectroscopy indicated that, the TEOS/O 2 ratio had pronounced influence on the deposition rate and optical properties for SiO 2 films. Modification on refractive index (n) for the synthesis of single mode optical waveguide can be easily achieved in PECVD process, by addition of TMP in the precursors. Based on this, a Si/SiO 2 /P-SiO 2 /SiO 2 ridge-type waveguide structure could be derived following a photolithography, lift-off and reactive ion etching (RIE) process sequence. In this study, silica etch characteristics of different etching parameters were investigated using CHF 3 /O 2 as the etch gases. Metal mask could offer higher selectivity and yielded smaller deposition of polymer, so that an optical quality ridge structure with high vertical sidewall angle and dimension controllability, and smooth sidewall surface became possible. The results came out that the etching parameters such as RF power and CHF 3 /O 2 ratio had significant influence on the etch rates, etch selectivities and etch profiles. Under optimal etching conditions and post-treatment, a single mode waveguide with vertical etch profile and smooth sidewall could be fabricated successfully.

A merged process for thick single-crystal Si resonators and BiCMOS circuitry

A simple process has been developed which combines thick single-crystal Si micromechanical devices with a bipolar complimentary metal-oxide-semiconductor (BiCMOS) integrated circuit process. This merged process allows the integration of Si mechanical resonators as thick as 11 /spl mu/m with any integrated circuit process with the addition of only a single masking step. The process does not require the use of Si on insulator wafers or any type of wafer bonding. The Si resonators were etched in an inductively coupled plasma source which allowed deep trenches to be fabricated with high aspect ratios and smooth sidewall surfaces. Clamped-clamped beam Si resonators that were 500 /spl mu/m long, 5 /spl mu/m wide, and 11 /spl mu/m thick have been fabricated and tested. A typical resonator had a resonance frequency of 28.9 kHz and a maximum amplitude of vibration at resonance of 4.6 /spl mu/m in air. The average measured resonance frequency across a 4-in-diameter Si wafer was within 0.5% of that predicted by theory. Working NMOS transistors were fabricated and tested on the same chip as the resonator with measured threshold voltages of 0.6 V and an output conductance of 2.0/spl times/10/sup -5/ /spl Omega//sup -1/ for a gate voltage of 4 V.