Smart Power Technology Research Articles

Floating well based design methodology aimed to improve latch-up immunity in a smart power technology

The main challenge of Smart Power Integrated Circuits lies in operating simultaneously on a same chip a power device and its control circuitry. To this purpose, static and dynamic isolation between these two active parts are required. A self-isolated CMOS/DMOS technology where the drain of the vertical DMOS is coincident with the substrate (N --epilayer) of the CMOS circuitry provides a cost effective static isolation. However, voltage transients induced during the power device switching can be capacitively coupled to the CMOS circuitry and latch-up can be initiated. Instead of introducing supplementary technological steps, a design based solution is proposed to improve dynamic isolation and then latch-up immunity [1]. Such a shielding is obtained by letting float the voltage of the P-well of the CMOS technology.

A simplified low-voltage smart power technology

A novel self-isolated low-voltage smart power technology, based on a conventional polysilicon-gate VDMOS process, has been developed for applications where cost is a crucial factor. The low mask count (eight) and the optimization of the VDMOS power device are the main process characteristics. Besides, different devices (high-voltage PMOS, low-voltage CMOS, vertical and lateral n-p-n bipolar transistors, diodes, Zeners, and high-value isolated capacitors) are also fabricated, all MOS transistors being self-aligned to the gate.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An overview of smart power technology

The evolution of smart power technology and the impact of this technology on electronic systems are reviewed. After providing a definition of smart power technology, the author describes the key technological developments in power semiconductor devices, namely power MOSFETs and IGBTs (insulated-gate bipolar transistors). These developments are the foundation upon which smart power technology rests. Smart power technology requires the marriage of power device technology with CMOS logic and bipolar analog circuits. The technical challenges involved in combining power handling capability with on-chip regulation of overcurrent, overvoltage, and overtemperature conditions are described, together with examples of solutions for telecommunications, motor control, and switch mode power supplies. >

Optimally scaled low-voltage vertical power MOSFETs for high-frequency power conversion

The systematic optimization of low-voltage silicon power MOSFET technology is described. It is shown that device scaling using advanced fabrication technologies can result in nearly optimal performance from low-voltage silicon power MOSFETs. The details discussed include: (1) system impact; (2) unit cell optimization; (3) device and process modeling; (4) fabrication technology development; and (5) performance results. The device technologies optimized include 30-, 50-, and 100-V vertical power DMOSFETs with optimally scaled gate polysilicon and source/drain contacts. Devices with the lowest specific on-resistance, the lowest specific input capacitance, and improved high-frequency switching performance have been fabricated with excellent wafer yield. This is the first successful demonstration of device scaling and its impact on performance of high-voltage and smart-power technologies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Smart power and high voltage integrated circuits and related MOS technologies

The state-of-the-art of high voltage and integrated power circuits in MOS technology is presented. In the introduction, the evolution of these integrated structures is described, their major advantages over the discrete device solution are recalled and the issues concerning integration are addressed. The structures of the various devices realized in MOS technology and used as power switches in integrated circuits are reviewed. The two main families of circuits currently developed are considered, i.e. (i) smart power technologies including one or several (common drain) power switches having a vertical configuration, integrated with their control and protection circuitry and (ii) high voltage integrated circuits in which the power devices are lateral, of low current capability and where the control circuits (CMOS or bipolar) may have a higher integration density. The major functional issues related with the design of a smart power switch are presented. The main building blocks, in particular the thermal limit circuitry as well as the bias stabilized networks, are detailed at the transistor level. It appears that the involved analog circuitry can be properly stabilized with respect to electrical fluctuations as well as to process related parameter variations and instabilities.

A Bipolar Smart Power Technology for High Voltage Applications

A Bipolar Smart Power Technology for High Voltage Applications