Smart Power Integrated Circuits Research Articles

Design of a NMOS-triggered SCR for dual-direction low-voltage ESD protection

An improved NMOS triggered dual-direction silicon controlled rectifier (NMOS-DDSCR) device is fabricated in 0.18 μm Silicon-on-Insulator (SOI) Bipolar-CMOS-DMOS (BCD) process. The proposed NMOS-DDSCR structure is designed based on the conventional DDSCR structure, which adds two additional auxiliary trigger paths achieved by NMOS transistors, diodes, and RC coupling circuits. The internal mechanism of NMOS-DDSCR is analyzed using two-dimension (2D) TCAD simulations, and the ESD performance is characterized by means of transmission line pulse (TLP) and very-fast TLP (VFTLP) measurements. Superior to the conventional DDSCR, the proposed NMOS-DDSCR exhibits a lower trigger voltage of 8.2 V, a higher human-body model (HBM) level of 4.0 kV, and a smaller leakage current of about 160 nA for low power application. In addition, the proposed NMOS-DDSCR has lower overshoot voltage, faster turn-on speed, and sufficient latchup immunity, which can be applied to ESD protection of 5.0 V input and output (I/O) pins in smart power integrated circuit (SPIC).

Compact Modeling of Fin-LDMOS Transistor Based on the Surface Potential

One of the basic components of smart power integrated circuits (SPICs) is the laterally diffused metal oxide semiconductor (LDMOS) transistors. In this paper, we propose Fin-LDMOS transistor based on the surface potential. In order to improve the accuracy, we have taken into account not only the fin-shape structure of the gate but also the mobility reduction and saturation velocity. The proposed method is evaluated considering a broad range of biases and physical parameters of the device. The comparison between modeling results and 3D simulations confirm the remarkable accuracy of our model.

Digital Integrated Circuits on an E-Mode GaN Power HEMT Platform

GaN-based digital integrated circuits (ICs) are realized on a 6-inch GaN-on-Si power high-electron-mobility transistor (HEMT) platform by monolithic integration of enhancement/depletion-mode HEMTs using a 0.5- $\mu \text{m}$ gate technology. A direct-coupled FET logic inverter and a 101-stage ring oscillator are fabricated and characterized. The inverter exhibits a large input voltage swing, wide noise margin, and high temperature stability, while the ring oscillator features a small propagation delay of 0.1 ns/stage under a supply voltage of 4 V. These digital ICs can operate properly up to at least 200 °C and show great potential for GaN smart power IC applications.

Modeling Minority Carriers Related Capacitive Effects for Transient Substrate Currents in Smart Power ICs

This paper presents an extended model for transient and ac circuit-level simulation of minority carriers propagation through the substrate of smart power integrated circuits (ICs). A p-n junction and a diffusion resistor with capacitive components are proposed to efficiently simulate transient parasitic coupled currents in high-power stages. From a general chip layout, an equivalent substrate network including capacitive effects (junction and diffusion capacitances) can be extracted and parasitic bipolar transistor can be simulated for the first time in transient operation by circuit simulators once the minority carriers continuity conditions are satisfied. This paper shows simulation results of the implemented models in good agreement with those obtained from technology computer-aided design. This implies that transient layout dependent mechanisms between high-voltage aggressor wells and low-voltage victims can be verified in early stages of IC design flow.

EMI susceptibility: The achilles' heel of smart power ICs

In this paper the main causes of failures induced by radio frequency interference in elementary integrated circuits (ICs) are summarized, then more complex devices like smart power ICs are considered and a method to evaluate their susceptibility to such disturbances is presented. The weakness of smart power ICs against radio frequency interference is highlighted referring to the results of measurements carried out on a test chip composed of a power MOS and an analog block both integrated in the same silicon die but electrically isolated one to each other.

Publisher's Note: “A Latch-up Immunized Lateral Trench Insulated Gate Bipolar Transistor with a p+ Diverter Structure for Smart Power Integrated Circuit”

Publisher's Note: “A Latch-up Immunized Lateral Trench Insulated Gate Bipolar Transistor with a p+ Diverter Structure for Smart Power Integrated Circuit”

Publisher's Note: “A Latch-up Immunized Lateral Trench Insulated Gate Bipolar Transistor with a p+ Diverter Structure for Smart Power Integrated Circuit”

Publisher's Note: “A Latch-up Immunized Lateral Trench Insulated Gate Bipolar Transistor with a p+ Diverter Structure for Smart Power Integrated Circuit”

Feasibility and limitations of anti-fuses based on bistable non-volatile switches for power electronic applications

Anti-fuse devices based on non-volatile memory cells and suitable for power electronic applications are demonstrated for the first time using silicon technology. These devices may be applied as stand alone devices or integrated using standard junction-isolation into application-specific and smart-power integrated circuits. The on-resistance of such devices can be permanently switched by nine orders of magnitude by triggering the anti-fuse with a positive voltage pulse. Extrapolation of measurement data and 2D TCAD process and device simulations indicate that 20A anti-fuses with 10mΩ can be reliably fabricated in 0.35μm technology with a footprint of 2.5mm2. Moreover, this concept offers distinguished added-values compared to existing mechanical relays, e.g. pre-test, temporary and permanent reset functions, gradual turn-on mode, non-volatility, and extendibility to high voltage capability.

Experimental Identification Method for Small-Signal Analysis of Smart Power ICs

Smart power integrated circuits (ICs), as the combination of control and power functions on a single chip, enable the production of more miniaturized systems. This paper presents an experimental method for the small-signal frequency-response analysis of smart power ICs in switch-mode power supplies. In this method, the switching-duty-cycle output of a power IC is converted into a digital signal by using two high-speed counters during each switching period, and the power IC's control input signal is simultaneously converted into a digital signal by an analog-to-digital converter. After processing the data of the duty-cycle output and the control input, not only the transient response but also the frequency response of the power IC can be obtained. Using least square identification, the smart power IC's transfer function is finally synthesized from the measurement data. This analysis method, referred to as sampling the transient responses and frequency responses of power ICs, can efficiently provide reliable and accurate transfer functions whether the switching frequency of a power IC is jittered or frequency modulated. The experiments using different power ICs were presented herein to validate the analysis method. The results were discussed, and the effectiveness and practicality of the method were verified.

A Smart Power Integrated Circuit Educational Tool

This paper describes a course in Smart Power based on the introduction of an innovative educational tool-a preprocessed Smart Power integrated circuit. The methodology used to introduce students to the issue of Smart Power design, resorting to low cost standard CMOS technology is presented. The theoretical support is envisaged to provide the required knowledge to specify characteristics and performance of the most common blocks used in Smart Power and to develop skills for monolithic integration. Through design, simulation, and experimental characterization, the students were able to experience the different steps of a Smart Power project, from the power device basic switching cell mask layout to the final system prototype, in 60 hours of a one semester course. The referred Smart Power Integrated Circuit (IC) embedding analog and digital basic blocks and high-voltage transistor arrays is the key idea to the presented pedagogical methodology. Based on this Smart Power IC, different topologies required by power electronics and power management systems were implemented. A complete system illustrative example-a step-down hard-switching dc-dc regulator (buck regulator)-implemented by the students is shown and discussed.

A Latch-up Immunized Lateral Trench Insulated Gate Bipolar Transistor with a p+ Diverter Structure for Smart Power Integrated Circuit

A new lateral trench insulated gate bipolar transistor (LTIGBT) with a p+ diverter was proposed to improve the characteristics of the conventional LTIGBT. The p+ diverter layer was placed between the anode electrode and the cathode electrode. As the conventional LTIGBT has a p+ divert region, the forward blocking voltage was decreased significantly because the n-drift layer corresponding to the punch-through region was reduced. However, the forward blocking voltage of the proposed LTIGBT with a p+ diverter was about 140 V. That of the conventional LTIGBT of the same size was 105 V. Because the p+ diverter region of the proposed device was enclosed in a trench oxide layer, the electric field moved toward the trench-oxide layer, and punch-through breakdown of LTIGBT with p+ diverter occurred late. Therefore, the p+ diverter of the proposed LTIGBT had no effect on the breakdown voltage unlike the conventional LTIGBT. The latch-up current densities of the conventional LTIGBT and LTIGBT with a p+ diverter were 540 A/cm2, and 1453 A/cm2, respectively. The enhanced latch-up capability of the proposed LTIGBT with a p+ diverter was obtained due to the holes in the current directly reaching the cathode via the p+ divert region and p+ cathode layer beneath the n+ cathode layer.

The Modular Power SIP An Innovative Packaging Technique for Smartpower Integrated Circuits

The Modular Power SIP An Innovative Packaging Technique for Smartpower Integrated Circuits