Smart Buffer Research Articles

Performance-efficient integration and programming approach of DCT accelerator for HEVC in MANGO platform

ABSTRACTVideo encoding based on novel HEVC standard is an extremely computationally expensive process and achieving efficient encoding requires intelligent utilization of all available resources, from both software and hardware perspective. Profiling and analysis of the encoding process identified Discrete cosine transform (DCT) as one of the key kernels that consume most of the time in the application's runtime. Therefore, high-throughput, fully-pipelined hardware accelerator was designed in FPGA and integrated into MANGO platform. MANGO platform is heterogeneous HPC system that consists of different types of nodes, from general purpose nodes (GN) to heterogeneous nodes (HN). While executing specific kernels on GN nodes is a straight-forward process, executing kernels on accelerator-based HNs is a more complex procedure and requires specific integration to successfully exploit heterogeneous architecture. This paper presents performance-efficient integration of DCT hardware accelerator in MANGO platform, focusing on the performance of the encoder while maintaining coding efficiency and video quality of the encoded bitstream. Several approaches were considered, tested and compared; from the standalone integration where series of single tasks were offloaded to the DCT accelerator, to more complex solutions based on smart buffer utilization.

Automotive Paint Shop 4.0

This paper focuses on the research and development of a new paint shop concept for the automotive industry, based on Industry 4.0 and Digital Factory ideas. The Paint Shop 4.0 project has been carried out on behalf of a German car manufacturer, in cooperation with ProPoint Sp. z o.o. Sp. k. and industrial partners. The main goal of this research is to reduce the primary bottleneck in the operation of a paint shop, which is caused by frequent changeovers of painting guns. A new type of sequencing problem is studied from both an algorithmic and a practical point of view. The original ‘Car Sequencing Problem’ focuses on determining the sequence before production starts, without the possibility of later change to this sequence. The new problem consists of real-time car sequencing using a buffer for the purpose of considering dynamic changes. Work begins with identifying and analyzing the causes of the emerging problem. Then, using tools like Virtual Engineering and Virtual Commissioning, the following tasks are performed: modeling of an existing production line with a buffer, model validation, and the development of methods to improve the sequencing process. Two heuristics based on a set of simple rules and one more advanced heuristic are proposed. Their effectiveness has been tested during simulations, based on real data, and compared with current industry solutions. The extensive computational experiments show that heuristics-based proposal outperforms the methods known from the literature in terms of in terms of matching to industry requirements. This indicates that it is possible to improve the sequencing effectiveness, and as a result a smart buffer control system is proposed. Validating the proposed solution in a virtual environment paves the way to implement the Paint Shop 4.0 concept in a real plant in the future.

Performance evaluation of a smart buffer control at a wastewater treatment plant

Real time control (RTC) is increasingly seen as a viable method to optimise the functioning of wastewater systems. Model exercises and case studies reported in literature claim a positive impact of RTC based on results without uncertainty analysis and flawed evaluation periods. This paper describes two integrated RTC strategies at the wastewater treatment plant (WWTP) Eindhoven, the Netherlands, that aim to improve the use of the available tanks at the WWTP and storage in the contributing catchments to reduce the impact on the receiving water. For the first time it is demonstrated that a significant improvement can be achieved through the application of RTC in practice. The Storm Tank Control is evaluated based on measurements and reduces the number of storm water settling tank discharges by 44% and the discharged volume by an estimated 33%, decreasing dissolved oxygen depletion in the river. The Primary Clarifier Control is evaluated based on model simulations. The maximum event NH4 concentration in the effluent reduced on average 19% for large events, while the load reduced 20%. For all 31 events the reductions are 11 and 4% respectively. Reductions are significant taking uncertainties into account, while using representative evaluation periods.

A QFHD 30-frames/s HEVC Decoder Design

The High Efficiency Video Coding (HEVC) standard provides superior compression with large and variable-size coding units and advanced prediction modes, which leads to high buffer costs, memory bandwidth, and irregular computation for ultra high-definition video decoding hardware. Thus, this paper presents an HEVC decoder with a four-stage mixed block size pipeline to reduce the pipeline stage buffer size by approximately 91% compared with the $64\times 64$ block-based pipeline. The high memory bandwidth due to motion compensation problem was solved by $16\times 16$ block-based data access, precision-based data access, and a smart buffer to reduce the data bandwidth by 88%. In addition, for irregular computation, a reconfigurable architecture was adopted to unify the variable-size transform. A common intra-prediction module was also designed with a $4\times 4$ block-based bottom-up computation for variable-size intra prediction and modes in a regular manner. Furthermore, the corner position computation for the motion vector predictor was applied to handle variable-size motion compensation. Finally, the implementation with the TSMC 90-nm CMOS process used 467k logic gates and 15.778 kB of on-chip memory and supported $4096\times 2160$ at 30-frames/s video decoding at a 270-MHz operation frequency.

A Smart Domestic Hot Water Buffer

Demand response is seen as a key technology to help the introduction of large volumes of intermittent renewable energy and to help mitigate the effects of the increasing load on the electricity distribution grid. A large and diverse number of control mechanisms are proposed for demand response, while multiple industrial companies are designing their own proprietary solutions. This situation demands for standardized and generalized interfaces for smart devices, i.e., interfaces based on as few indicators as possible that reflect the flexibility state, while hiding all implementation details and specifics of the device. Electric domestic hot water buffers are devices that inherently contain a lot of flexibility, i.e., the charging can be shifted without impact on the comfort of the user. This article presents four key indicators for domestic hot water buffers that meet above requirements: P, the rated power, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> , the energy required to fully charge the buffer, SoC, the state of charge, and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> , the energy required before the SoC increases. The correct behavior of these key indicators has been validated by means of simulations and measurements on a lab prototype. The integration of the smart buffer into a time of use demand response system is demonstrated with a test setup and measurement results.

Efficient hardware code generation for FPGAs

The wider acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. We describe the code generation approach in ROCCC. The smart buffer is a component that reuses input data between adjacent iterations. It significantly improves the performance of the circuit and simplifies loop control. The ROCCC-generated datapath can execute one loop iteration per clock cycle when there is no loop dependency or there is only scalar recurrence variable dependency. ROCCC's approach to supporting while-loops operating on scalars makes the compiler able to move scalar iterative computation into hardware.

System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design

In this paper, a novel system-level buffer planning algorithm that can be used to customize the router design in networks-on-chip (NoCs) is presented. More precisely, given the traffic characteristics of the target application and the total budget of the available buffering space, the proposed algorithm automatically assigns the buffer depth for each input channel, in different routers across the chip, such that the overall performance is maximized. This is in deep contrast with the uniform assignment of buffering resources (currently used in NoC design), which can significantly degrade the overall system performance. Indeed, the experimental results show that while the proposed algorithm is very fast, significant performance improvements can be achieved compared to the uniform buffer allocation. For instance, for a complex audio/video application, about 80% savings in buffering resources, can be achieved by smart buffer allocation using the proposed algorithm

An automated, FPGA-based reconfigurable, low-power RFID tag

The use of radio frequency identification (RFID) technology is expanding rapidly in numerous applications such as logistics, supply chain management, transportation, healthcare and aviation. Due to the variety of the current applications, typical RFID systems use application specific hardware and proprietary protocols. These systems generally have long design times, no tolerance to changes in application or standard, and hence very high system costs. This paper describes an RFID tag specification and automated design flow for the creation of customized, low-power, active RFID tags. RFID primitives supported by the tag are enumerated with assembly like RFID macros. From these macros, the RFID pre-processor generates templates automatically. The behavior of each RFID primitive is specified using ANSI C where indicated within the template. The resulting file is compiled by the RFID compiler for the extensible tag. In order to save power, a smart buffer has been developed to sit between the transceiver and the tag controller. Because RFID packets are broadcast to everyone in range, the smart buffer contains minimal logic to detect whether incoming packets are intended for the tag. By doing so, the main controller may remain powered down to reduce system power consumption. Two System-on-a-Chip implementation strategies are presented. First, a microprocessor based system for which a C program is automatically generated and compiled for the system. The second replaces the microprocessor with a block of low-power FPGA logic. The user supplied RFID logic is specified in RFID macros and ANSI-C and automatically converted into combinational VHDL by the RFID compiler. Based on a test program, the processors required 183, 43, and 19 μJ per transaction for StrongARM, XScale, and EISC processors, respectively. By replacing the processor with a Coolrunner II, the controller can be reduced to 1.11 nJ per transaction.

A new NAND-type flash memory package with smart buffer system for spatial and temporal localities

Abstract This research is to design a high performance NAND-type flash memory package with a smart buffer cache that enhances the exploitation of spatial and temporal locality. The proposed buffer structure in a NAND flash memory package, called as a smart buffer cache, consists of three parts, i.e., a fully-associative victim buffer with a small page size, a fully-associative spatial buffer with a large page size, and a dynamic fetching unit. This new NAND-type flash memory package can achieve dramatically higher performance and lower power consumption compared with any conventional NAND-type flash memory module. Our results show that the NAND flash memory package with a smart buffer cache can reduce the miss ratio by around 70% and the average memory access time by around 67%, over the conventional NAND flash memory configuration. Also, the average miss ratio and the average memory access time of the package module with smart buffer cache for a given buffer space (e.g., 3 KB) can achieve better performance than package modules with a conventional direct-mapped buffer with eight times (e.g., 32 KB) or than a fully-associative configuration with twice as much space (e.g., 8 KB).