Small Equivalent Oxide Thickness Research Articles

Integration of Ultrathin Hafnium Oxide with a Clean van der Waals Interface for Two-Dimensional Sandwich Heterostructure Electronics.

Integrating high-κ dielectrics with a small equivalent oxide thickness (EOT) with two-dimensional (2D) semiconductors for low-power consumption van der Waals (vdW) heterostructure electronics remains challenging in meeting both interface quality and dielectric property requirements. Here, we demonstrate the integration of ultrathin amorphous HfOx sandwiched within vdW heterostructures by the selective thermal oxidation of HfSe2 precursors. The self-cleaning process ensures a high-quality interface with a low interface state density of 1011-1012 cm-2 eV-1. The synthesized HfOx displays excellent dielectric properties with an EOT of ∼1.5 nm, i.e., a high κ of ∼16, an ultralow leakage current of 10-6 A/cm2, and an impressively high breakdown field of 9.5 MV/cm. This facilitates low-power consumption vdW heterostructure MoS2 transistors, demonstrating steep switching with a low subthreshold swing of 61 mV/decade. This one-step integration of high-κ dielectrics into vdW sandwich heterostructures holds immense potential for developing low-power consumption 2D electronics while meeting comprehensive dielectric requirements.

3 V operation of pentacene-based floating-gate memory realized by the isolation process with Ar/N2-plasma nitridation for N-doped LaB6 metal and high-k LaB x Ny insulator stacked structure

In this paper, we have investigated the low-voltage operation of pentacene-based floating-gate (FG) memory utilizing nitrogen-doped (N-doped) LaB6 metal and LaB x N y insulator stacked structure. The pentacene-based FG Au/pentacene/N-doped LaB6(Metal: M)/LaB x N y (Insulator: I)/N-doped LaB6(M)/LaB x N y (I)/n+-Si(100) (Semiconductor: S) MIMIS organic field-effect transistor (OFET) was fabricated by utilizing the Ar/N2-plasma nitridation to isolate the edge region of the N-doped LaB6 FG with Au source/drain (S/D) electrodes. The Ar/N2-plasma nitridation was found to be effective in suppressing the leakage current between the Au S/D electrodes and N-doped LaB6 FG. The pentacene-based FG memory was successfully developed with the memory window (MW) of 0.71 V and the saturation mobility (μ sat) of 1.8 × 10−2 cm2/(V·s), under pulse input of ±3.4 V/10 ms due to the small equivalent oxide thickness (EOT) of 3.1 nm. Furthermore, MW of 0.4 V was obtained under minimum program/erase pulse amplitude/width of ±3 V/100 μs at the process temperature of 200 °C.

Influence of Ultra-Thin Ge₃N₄ Passivation Layer on Structural, Interfacial, and Electrical Properties of HfO₂/Ge Metal-Oxide-Semiconductor Devices.

We report the effects of the nitride passivation layer on the structural, electrical, and interfacial properties of Ge metal-oxide-semiconductor (MOS) devices with a hafnium oxide (HfO₂) gate dielectric layer deposited on p-type 〈100〉 Ge substrates. X-ray photoelectron spectroscopy analysis confirmed the chemical states and formation of HfO₂/Ge₃N₄ on Ge. The interfacial quality and thickness of the layers grown on Ge were confirmed by high-resolution transmission electron microscopy. In addition, the effects of post-deposition annealing (PDA) on the HfO₂/Ge₃N₄/Ge and HfO₂/Ge samples at 400 °C in an (FG+O₂) ambient atmosphere for 30 min were studied. After PDA, the HfO₂/Ge₃N₄/Ge MOS device showed a higher dielectric constant (k) of ~21.48 and accumulation capacitance of 1.2 nF, smaller equivalent oxide thickness (EOT) of 1.2 nm, and lower interface trap density (Dit) of 4.9×1011 cm-2 eV-1 and oxide charges (Qeff) of 7.8×1012 cm-2 than the non-annealed sample. The I-V analysis showed that the gate leakage current density of the HfO₂/Ge₃N₄/Ge sample (0.3-1 nA cm-2 at Vg = 1 V) was half of that of the HfO₂/Ge sample. Moreover, the barrier heights of the samples were extracted from the Fowler-Nordheim plots. These results indicated that nitride passivation is crucial to improving the structural, interfacial, and electrical properties of Ge-based MOS devices.

High-performance SEGISFET pH Sensor using the structure of double-gate a-IGZO TFTs with engineered gate oxides

In this paper, we propose a high-performance separative extended gate ion-sensitive field-effect transistor (SEGISFET) that consists of a tin dioxide (SnO2) SEG sensing part and a double-gate structure amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with tantalum pentoxide/silicon dioxide (Ta2O5/SiO2)-engineered top-gate oxide. To increase sensitivity, we maximized the capacitive coupling ratio by applying high-k dielectric at the top-gate oxide layer. As an engineered top-gate oxide, a stack of 25 nm-thick Ta2O5 and 10 nm-thick SiO2 layers was found to simultaneously satisfy a small equivalent oxide thickness (∼17.14 nm), a low leakage current, and a stable interfacial property. The threshold-voltage instability, which is a fundamental issue in a-IGZO TFTs, was improved by low-temperature post-deposition annealing (∼87 °C) using microwave irradiation. The double-gate structure a-IGZO TFTs with engineered top-gate oxide exhibited high mobility, small subthreshold swing, high drive current, and larger on/off current ratio. The a-IGZO SEGISFETs with a dual-gate sensing mode showed a pH sensitivity of 649.04 mV pH−1, which is far beyond the Nernst limit. The non-ideal behavior of ISFETs, hysteresis, and drift effect also improved. These results show that the double-gate structure a-IGZO TFTs with engineered top-gate oxide can be a good candidate for cheap and disposable SEGISFET sensors.

A Low-Leakage Epitaxial High-κ Gate Oxide for Germanium Metal-Oxide-Semiconductor Devices.

Germanium (Ge)-based metal-oxide-semiconductor field-effect transistors are a promising candidate for high performance, low power electronics at the 7 nm technology node and beyond. However, the availability of high quality gate oxide/Ge interfaces that provide low leakage current density and equivalent oxide thickness (EOT), robust scalability, and acceptable interface state density (D(it)) has emerged as one of the most challenging hurdles in the development of such devices. Here we demonstrate and present detailed electrical characterization of a high-κ epitaxial oxide gate stack based on crystalline SrHfO3 grown on Ge (001) by atomic layer deposition. Metal-oxide-Ge capacitor structures show extremely low gate leakage, small and scalable EOT, and good and reducible D(it). Detailed growth strategies and postgrowth annealing schemes are demonstrated to reduce Dit. The physical mechanisms behind these phenomena are studied and suggest approaches for further reduction of D(it).

Impact of Postdeposition Annealing Ambient on the Mobility of Ge nMOSFETs With 1-nm EOT Al2O3/GeOx/Ge Gate-Stacks

The impact of postdeposition annealing (PDA) ambient on electrical properties of thin equivalent oxide thickness (EOT) Al2O3/GeO x /Ge gate-stacks is investigated. It is found that the surface states inside the conduction band of Ge are significantly suppressed by 40% through PDA with atomic deuterium ambient. As a result, enhancement of the effective mobility in the Ge nMOSFETs is realized in high normal field region. The electron mobility of 396 cm2/Vs is achieved at $N_{s}$ of $10^{13}$ cm $^{-2}$ with small EOT of $\sim 1$ nm, which is similar to the highest mobility reported so far at such small EOT range.

HfO2 gate dielectric on Ge (1 1 1) with ultrathin nitride interfacial layer formed by rapid thermal NH3 treatment

Interfacial properties of the ALD deposited HfO2 over the surface nitrided germanium substrate have been studied. The formation of GeON (∼1.7nm) was confirmed by X-ray photoelectron spectroscopy (XPS) and high resolution transmission electron spectroscopy (HRTEM) over the germanium surface. The effect of post deposition annealing temperature was investigated to study the interfacial and electrical properties of hafnium oxide/germanium oxynitride gate stacks. The high-k MOS devices with ultrathin GeON layer shows the good electrical characteristics including higher k value ∼18, smaller equivalent oxide thickness (EOT) around 1.5nm and smaller hysteresis value less than 170mV. The Qeff and Dit values are somewhat greater due to the (111) orientation of the germanium and may be due to the presence of nitrogen at the interface. The Fowler–Northeim (FN) tunneling of Ge MOS devices has been studied. The barrier height ΦB extracted from the plot is ∼1eV.

Scaling Theory of Electrically Doped 2D Transistors

In this letter, it is shown that the existing scaling theories for chemically doped transistors cannot be applied to the novel class of electrically doped 2D transistors and the concept of equivalent oxide thickness (EOT) is not applicable anymore. Hence, a novel scaling theory is developed based on analytic solutions of the 2D Poisson equation. Full band atomistic quantum transport simulations verify the theory and show that the critical design parameters are the physical oxide thickness and distance between the gates. Accordingly, the most optimized electrically doped devices are those with the smallest spacing between the gates and the thinnest oxide, and not the smallest EOT.

High performance thin film transistors using low-temperature solution-processed Li-incorporated In2O3/ZrO2 stacks

We improved the performance of low-temperature solution-processed thin film transistors (TFTs) by lithium doping of In2O3/ZrO2 gate stacks. Li incorporation into In2O3 reduced interface diffusion of ZrO2 and improved channel mobility. Enhanced crystallization of Li-doped In2O3 thin films as well as the small equivalent oxide thickness of ZrO2 were determined to be key factors in the observed improvement in device performance. An increase in the [Li+]/[In3+] ratio over the optimum value resulted in performance degradation, which we attributed to the formation of higher energy barriers due to grain boundaries.

Crystalline ZrTiO4 gated p-metal–oxide–semiconductor field effect transistors with sub-nm equivalent oxide thickness featuring good electrical characteristics and reliability

ZrTiO4 crystallized in orthorhombic (o-) phase was stacked with an amorphous Yb2O3 interfacial layer as the gate dielectric for Si-based p-MOSFETs. With thermal annealing after gate electrode, the gate stack with equivalent oxide thickness (EOT) of 0.82 nm achieves high dielectric quality by showing a low interface trap density (Dit) of 2.75 × 1011 cm−2eV−1 near the midgap and low oxide traps. Crystallization of ZrTiO4 and post metal annealing are also proven to introduce very limited amount of metal induced gap states or interfacial dipole. The p-MOSFETs exhibit good sub-threshold swing of 75 mV/dec which is ascribed to the low Dit value and small EOT. Owing to the Y2O3 interfacial layer and smooth interface with Si substrate that, respectively, suppress phonon and surface roughness scattering, the p-MOSFETs also display high hole mobility of 49 cm2/V-s at 1 MV/cm. In addition, Ion/Ioff ratio larger than 106 is also observed. From the reliability evaluation by negative bias temperature instability test, after stressing with an electric field of −10 MV/cm at 85 °C for 1000 s, satisfactory threshold voltage shift of 12 mV and sub-threshold swing degradation of 3% were obtained. With these promising characteristics, the Yb2O3/o-ZrTiO4 gate stack holds the great potential for next-generation electronics.

Effect of ultrathin GeOx interfacial layer formed by thermal oxidation on Al2O3 capped Ge

We propose a modified thermal oxidation method in which an Al2O3 capping layer is used as an oxygen blocking layer (OBL) to form an ultrathin GeOx interfacial layer, and obtain a superior Al2O3/GeOx/Ge gate stack. The GeOx interfacial layer is formed in oxidation reaction by oxygen passing through the Al2O3 OBL, in which the Al2O3 layer could restrain the oxygen diffusion and suppress the GeO desorption during thermal treatment. The thickness of the GeOx interfacial layer would dramatically decrease as the thickness of Al2O3 OBL increases, which is beneficial to achieving an ultrathin GeOx interfacial layer to satisfy the demand for small equivalent oxide thickness (EOT). In addition, the thickness of the GeOx interfacial layer has little influence on the passivation effect of the Al2O3/Ge interface. Ge (100) p-channel metal–oxide–semiconductor field-effect transistors (pMOSFETs) using the Al2O3/GeOx/Ge gate stacks exhibit excellent electrical characteristics; that is, a drain current on-off (Ion/Ioff) ratio of above 1×104, a subthreshold slope of ∼ 120 mV/dec, and a peak hole mobility of 265 cm2/V·s are achieved.

New Simulation Method to Characterize the Recoverable Component of Dynamic Negative-Bias Temperature Instability in p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

We introduce a new simulation technique to investigate the recovery characteristics of dynamic negative-bias temperature instability (NBTI) in conventional silicon dioxide (SiO2) dielectric p-channel metal–oxide–semiconductor field-effect transistors (p-MOSFETs) based on the hydrogen diffusion and hole-trapping mechanisms. In this work, a sequence of train pulses on the gate terminal were applied to simulated p-MOSFETs in single and multiple runs, thus emulating repetitive cycles of stress and recovery. The effects of varying the applied stress voltages, temperatures, and durations were then analyzed. The recoverable component, R, of degradation was found to increase when the magnitudes of the applied stress voltage and temperature were increased. Moreover, the R was reduced when the recovery time was increased for a single run. In contrast, the R increased when the recovery time was increased for multiple runs. The normalized R of the simulated device was found to decrease by 0.7% and to increase by 7% with respect to the shortest recovery duration for a single run and for multiple runs, respectively. In addition, we measured the effects of equivalent oxide thickness (EOT) on the R and found that, in our study, the R for a transistor with a smaller EOT exhibited a substantial increase of 84% compared with that for a transistor with a larger EOT. These characteristics of the R of dynamic NBTI could be explained from the perspectives of the reaction–diffusion (R–D) model and hole-trapping mechanism. The results suggested that the underlying connection between these two mechanisms was the interface trap concentration, which represents the permanent components in both mechanisms.

Epitaxial growth and characterization of Gd2O3-doped HfO2 film on Ge (001) substrates with zero interface layer

The GHO (Gd2O3-doped HfO2) films were epitaxially grown on Ge (001) substrates adopting cube-on-cube mode with zero interface layer using pulsed laser deposition (PLD). Reflection high-energy electron diffraction (RHEED) and high-resolution transmission electron microscopy (HRTEM) observation revealed a sharp interface of GHO/Ge and orientation relationship corresponding to (001)GHO//(001)Ge and [011] GHO//[011]Ge. The band offset for GHO/Ge stack was evaluated to be 3.92 eV for valence band and 1.38 eV for conduction band by X-ray photoelectron spectrum. Small equivalent oxide thickness (0.49 nm) and interface state density (7×1011 cm−2) were achieved from Au/Ti/GHO/Ge/Al capacitors.

New Erase Constraint for the Junction-Less Charge-Trap Memory Array in Cylindrical Geometry

This paper presents a detailed simulation analysis of the erase performance of junction-less charge-trap memory arrays in the cylindrical geometry, showing that a saturation of the erased threshold voltage occurs as a result of incomplete inversion of the intercell regions when positive charge is stored in the cells. This erase saturation issue is investigated as a function of string and cell parameters, revealing lower erase capabilities for large cell-to-cell separation, small substrate radius, and small equivalent-oxide thickness of the gate stack. These results add new constraints to the design of cylindrical junction-less memory technologies.

Gate-first n-MOSFET with a sub-0.6-nm EOT gate stack

Self-aligned and gate-first TiLaO/La2O3n-MOSFET shows an equivalent oxide thickness (EOT) of 0.57nm.Small EOT can be reached using La silicate to suppress the formation of low-? defective interface.This low-EOT MOSFET exhibits the potential to integrate with current CMOS process. We report a self-aligned and gate-first TiLaO/La2O3n-MOSFET with an equivalent oxide thickness (EOT) of 0.57nm and low threshold voltage (Vt) of 0.3V. The small EOT MOSFET can be reached using La-based interfacial layer with strong bond enthalpy (La-O, 799kJ/mol) to suppress the formation of defect-rich low- interfacial layer and simultaneously block titanium atom inter-diffusion to avoid additional EOT increase. This gate-first low-EOT MOSFET exhibits the potential to integrate with current CMOS process.

Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO2 gate stack

We report a gate-first TiLaO/CeO2n-MOSFET with an equivalent oxide thickness (EOT) of only 0.56nm and threshold voltage (Vt) of 0.31V. This small EOT MOSFET was achieved by employing high-κ CeO2 interfacial layer with high bond enthalpy (795kJ/mol) to replace low-κ SiO2 with close bond enthalpy (800kJ/mol). The cerium silicate can aggressively scale EOT down to sub-0.6-nm EOT region without increasing gate leakage, which is urgently needed for 16nm technology node.

In0.53Ga0.47As FinFETs with self-aligned molybdenum contacts and HfO2/Al2O3 gate dielectric

InGaAs channel FinFETs with self-aligned molybdenum (Mo) contacts was demonstrated using a gate-last process. By realizing Mo contacts on in situ doped n++ InGaAs source and drain and self-aligned to channel, the FinFETs achieved series resistance of ∼250Ωμm, which is the lowest value reported-to-date for InGaAs non-planar n-MOSFETs. A FinFET with channel length of 500nm and equivalent oxide thickness (EOT) of 3nm has an on-state/off-state current ratio of ∼105 and peak extrinsic transconductance of 255μS/μm at drain voltage of 0.5V. To further reduce EOT, atomic-layer-deposited HfO2/Al2O3 high-k dielectric was integrated in InGaAs FinFETs. Good interface quality and small EOT of ∼1nm were achieved. Forming gas annealing (FGA) was used for drive current enhancement. A 300°C 30min FGA leads to ∼48% increase in drive current as well as significant reduction of subthreshold swing, probably due to an improvement of the HfO2/Al2O3/InGaAs interface quality.

Characteristics of HfLaON/SiO2 Gate Stack Prepared Using Reactive Sputtering

HfLaON is one of the most promising high-k dielectrics because of its higher crystallization temperature and ability to tune the work function of the metal gates from Si midgap to around 4eV, meeting the requirement of nMOSFETs. In this paper, HfLaON was prepared using reactive sputtering that alternates between Hf and HfLa targets in N2/Ar ambient, followed by a post-deposition anneal. Before deposition of HfLaON film, SiO2 interfacial layer was grown to improve the interface properties. HfLaON/SiO2 gate stack exhibited good physical and electrical characteristics, including good thermal stability, excellent interface properties, small equivalent oxide thickness and low gate-leakage current. Further studies found that the excellent characteristics of the gate stack have close relation to the grown method of SiO2 interfacial layer. In order to investigate their relationship, the different grown methods of SiO2 interfacial layer were adopted and compared in the fabrication of HfLaON/SiO2 gate stacks, such as oxidation in O3/H2O solution, rapid thermal anneal in N2 or N2/O2 mixed gas.

Effects of postdeposition annealing on a high-k-last/gate-last integration scheme for 20 nm nMOS and pMOS

The authors report the use of postdeposition annealing (PDA) to improve the performance of a high-k (HK)-last/gate-last integration scheme involving the use of a chemical oxide interfacial layer (IL). They find that the chemical oxide IL can form Hf-silicate at the HK/IL interface to provide a larger effective k value and a smaller equivalent oxide thickness. They also find that they can achieve a small gate leakage current density (Jg) and minimal flat-band voltage (Vfb) degradation by PDA in O2 atmosphere. Furthermore, they find that Jg and Vfb can be further improved by optimizing the metal gate stack.

Low Operation Voltage InGaZnO Thin Film Transistors with LaAlO3 Gate Dielectric Incorporation

In this paper, we report low operation voltage indium gallium zinc oxide (IGZO) thin film transistors (TFTs) incorporating a high-κ lanthanum aluminum oxide (LaAlO3) as gate dielectric. Good TFT characteristics were achieved simultaneously, including a small subthreshold swing (SS) of 98 mV/dec, a low threshold voltage (Vt) of 0.29 V, a good on-off-state drive current ratio (Ion/Ioff) of 1.1 × 105, and field effect mobility (μFE) of 5.4 cm2/V·sec. These good performances are related to the high gate capacitance density and small equivalent oxide thickness (EOT) provided by the high-κ LaAlO3 dielectric. Moreover, the effects of oxygen partial pressure during IGZO deposition process on the device characteristics were investigated. The small SS and low Vt allow the devices to be used at operation voltage as low as 1.5 V, which shows the great potential for future high speed and low power applications.