Silicon photonics offers the possibility to integrate a large number of photonic components on a small Si chip in a similar fashion as microelectronic circuits have been realized for many decades. This enables low power consumption, small footprint and low-cost mass production. Application areas for Si photonics reach from optical communication and computing to optical sensing and imaging. Monolithic germanium PIN detectors are one of the key components in photonic integrated circuits (PICs) and convert light into electrical signals. Germanium is the preferred material for photodetectors in silicon photonics as it absorbs light in the datacom and telecom wavelength range (1.2-1.7 μm) due to its small bandgap. Germanium is also tolerated in the IC-clean manufacturing lines, unlike many other potential semiconductor materials. Electron and hole mobilities in germanium are high, enabling high-bandwidth detectors. Challenges in Ge integration on silicon-on-insulator (SOI) wafers include unintentional oxidization and etching in many of the standard silicon technology processing steps, fast diffusion of n-type dopants in Ge and relatively large lattice mismatch between Ge and Si.High refractive index contrast between silicon (3.5) and silicon dioxide (1.5) is the key to achieve ultra-dense photonics integration. Most of the silicon photonics research is carried out using submicron-thick SOI waveguides and latest microelectronics fabrication technologies that involve (and require) very small wafer topography. In this paper, we present Ge photodiode integration on a 3 µm SOI platform with 3 µm thick Si waveguides. Those offer ultra-low propagation losses (~0.1 dB/cm), ultra-dense integration (μm-scale bends), small polarization dependency (down-to-zero birefringence) and ability to tolerate relatively high optical powers (>1W). One major limitation on the 3 µm SOI platform has been the lack of as fast modulators and photodetectors as those integrated on sub-µm SOI platforms. In this work, we monolithically integrated a fast horizontal PIN photodiode on the 3 µm SOI platform. The 3 dB cutoff frequency was 40 GHz and the responsivity was 1.0 A/W at -1 V bias and 1.55 µm wavelength. This high bandwidth indicates that the detector is limited by the transit time of the carriers over the i-region, rather than the junction capacitance. The electric field in the i-region at -1 V is sufficient to keep the carrier drift speed close to the maximum carriers velocity in Ge.The design of the 40 GHz PD included analytical calculations and numerical simulations. Physical dimensions of the detector were chosen so that they are compatible with the 3 µm SOI process flow and meet the bandwidth and responsivity targets. Germanium was selectively grown into cavities in the 3 µm SOI layer, leading to very low amount of stress-induced crystal defects. The Ge waveguide detector and the Si waveguides were patterned with a common hard mask to achieve self-alignment between them. The n- and p-contacts were directly made into Ge using Ti/Al metallization. The vertical sidewalls of the Ge detector were implanted in order to create a horizontal PIN structure. Due to high confinement of light into the 3 µm thick SOI and Ge waveguides, the 3 µm thick and 1 µm wide Ge detector could be made as short as 9 µm. This led to small junction capacitances. The electrical output pulse shape was not distorted by the slow diffusion current of electrons and holes because the incoming light does not enter the doped regions. The development of 40 GHz PDs was an important step in improving the feasibility of the 3 µm SOI platform in high-bandwidth applications. Figure 1
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Jul 31, 2021
Akira Nakao + 2
Open Access