Small Memory Capacity Research Articles

Optimizing quantum noise-induced reservoir computing for nonlinear and chaotic time series prediction

Quantum reservoir computing is strongly emerging for sequential and time series data prediction in quantum machine learning. We make advancements to the quantum noise-induced reservoir, in which reservoir noise is used as a resource to generate expressive, nonlinear signals that are efficiently learned with a single linear output layer. We address the need for quantum reservoir tuning with a novel and generally applicable approach to quantum circuit parameterization, in which tunable noise models are programmed to the quantum reservoir circuit to be fully controlled for effective optimization. Our systematic approach also involves reductions in quantum reservoir circuits in the number of qubits and entanglement scheme complexity. We show that with only a single noise model and small memory capacities, excellent simulation results were obtained on nonlinear benchmarks that include the Mackey-Glass system for 100 steps ahead in the challenging chaotic regime.

Microcontroller-Based PUF for Identity Authentication and Tamper Resistance of Blockchain-Compliant IoT Devices.

Blockchain-based applications necessitate the authentication of connected devices if they are employed as blockchain oracles. Alongside identity authentication, it is crucial to ensure resistance against tampering, including safeguarding against unauthorized alterations and protection against device counterfeiting or cloning. However, attaining these functionalities becomes more challenging when dealing with resource-constrained devices like low-cost IoT devices. The resources of IoT devices depend on the capabilities of the microcontroller they are built around. Low-cost devices utilize microcontrollers with limited computational power, small memory capacity, and lack advanced features such as a dedicated secure cryptographic chip. This paper proposes a method employing a Physical Unclonable Function (PUF) to authenticate identity and tamper resistance in IoT devices. The suggested PUF relies on a microcontroller's internal pull-up resistor values and, in conjunction with the microcontroller's built-in analog comparator, can also be utilized for device self-checking. A main contribution of this paper is the proposed PUF method which calculates the PUF value as the average value of many single PUF measurements, resulting in a significant increase in accuracy. The proposed PUF has been implemented successfully in a low-cost microcontroller device. Test results demonstrate that the device, specifically the microcontroller chip, can be identified with high accuracy (99.98%), and the proposed PUF method exhibits resistance against probing attempts.

HCALA: Hyperelliptic curve-based anonymous lightweight authentication scheme for Internet of Drones

A drone is often called an ”Unmanned Aerial Vehicle” or UAV. It is utilized in various civilian and military applications, including agriculture, surveillance, and delivery of packages. A promising idea for enhancing the safety and quality of drone flight is to build the Internet of Drones (IoD), in which drones are used to collect sensitive data, which is then communicated in real-time to external user (Ui) through the Ground Station Server (GSS). Before deployment, the GSS and all drones are registered with Control Room (CR), a central authority, which is a trusted authority. To ensure secure and reliable communications, an efficient and secure authentication scheme is needed to enable users and drones to authenticate each other and share a session key. Furthermore, because drones generally have small batteries and limited memory capacity, efficient and lightweight security techniques are suitable for them. Many schemes to secure IoD environments have been proposed recently; however, some were proven as insecure, and some degraded efficiency. In this work, we focus on developing a novel blockchain-based authentication scheme, called HCALA, on protecting the communication between an external user and drone utilizing Hyperelliptic Curve Cryptography (HECC). To evaluate the viability and efficacy of HCALA, We employ the extensively used Random Oracle Model (ROM) and formal security verification using a software tool called AVISPA, which is used to validate the internet security protocols. HCALA is also examined by utilizing informal security analysis techniques, demonstrating that the proposed protocol can withstand several well-known active and passive adversary attacks. It also shows that HCALA is more efficient regarding different parameters, according to the performance comparison. Compared to previous similar schemes, the security and functionality aspects are improved, and the computation, communication costs, and energy consumption are reduced.

Smart deployment of IoT-TelosB service care StreamRobot using software-defined reliability optimisation design

Intelligent service care robots have increasingly been developed in mission-critical sectors such as healthcare systems, transportation, manufacturing, and environmental applications. The major drawbacks include the open-source Internet of Things (IoT) platform vulnerabilities, node failures, computational latency, and small memory capacity in IoT sensing nodes. This article provides reliable predictive analytics with the optimisation of data transmission characteristics in StreamRobot. Software-defined reliable optimisation design is applied in the system architecture. For the IoT implementation, the edge system model formulation is presented with a focus on edge cluster log-normality distribution, reliability, and equilibrium stability considerations. A real-world scenario for accurate data streams generation from in-built TelosB sensing nodes is converged at a sink-analytic dashboard. Two-phase configurations, namely off-taker and on-demand, link-state protocols are mapped for deterministic data stream offloading. An orphan reconnection trigger mechanism is used for reliable node-to-sink resilient data transmissions. Data collection is achieved, using component-based programming in the experimental testbed. Measurement parameters are derived with TelosB IoT nodes. Reliability validations on remote monitoring and prediction processes are studied considering neural constrained software-defined networking (SDN) intelligence. An OpenFlow-SDN construct is deployed to offload traffic from the edge to the fog layer. At the core, fog detection-to-cloud predictive machine learning (FD-CPML) is used to predict real-time data streams. Prediction accuracy is validated with decision tree, logistic regression, and the proposed FD-CPML. The data streams latency gave 40.00%, 33.33%, and 26.67%, respectively. Similarly, linear predictive scalability behaviour on the network plane gave 30.12%, 33.73%, and 36.15% respectively. The results show satisfactory responses in terms of reliable communication and intelligent monitoring of node failures.

A comprehensive taxonomy of security and privacy issues in RFID

Internet of things (IoT) is made up of many devices like sensors, tags, actuators, mobile devices, and many more. These devices interact with each other without human interaction. Radio-frequency identification (RFID) devices are used to track people, assets, objects, etc. Along with the small memory capacity and low-power battery issues, these devices suffer from various security-related issues. These security threats include attacks such as replay, disclosure, tracking, offline guessing, denial of service attacks, and many more. In the last few decades, the researchers have suggested various security approaches to overcome these vulnerabilities. Hence, this paper discusses various possible attacks that can occur on an RFID system, and several security schemes that have been proposed to handle these attacks. First, the works presents the architecture of IoT in detail. Second, all possible attacks are described by categorizing them into confidentiality, integrity, and availability. Then, taxonomy of various security schemes, to deal with these attacks, is discussed under the criteria cryptography approaches, privacy, authentication, authorization, and availability. Finally, the paper describes various issues and challenges to have a better understanding of scope of the future research in the field of RFID security.

SRAM-PUF-Based Entities Authentication Scheme for Resource-Constrained IoT Devices

With the development of the cloud-based Internet of Things (IoT), people and things can request services, access data, or control actuators located thousands of miles away. The entity authentication of the remotely accessed devices is an essential part of the security systems. In this vein, physical unclonable functions (PUFs) are a hot research topic, especially for generating random, stable, and tamper-resistant fingerprints. This article proposes a lightweight, robust static random access memory (SRAM)-PUF-based entity authentication scheme to guarantee that the accessed end devices are trustable. The proposed scheme uses challenge-response pairs (CRPs) represented by reordered memory addresses as challenges and the corresponding SRAM cells' startup values as responses. The experimental results show that our scheme can efficiently authenticate resources-constrained IoT devices with a low computation overhead and small memory capacity. Furthermore, we analyze the SRAM-PUF by testing the PUF output under different environmental conditions, including temperature and magnetic field, in addition to exploring the effect of writing different values to the SRAM cells on the stability of their startup values.

Locality-Sensitive Hashing for Information Retrieval System on Multiple GPGPU Devices

It is challenging to build a real-time information retrieval system, especially for systems with high-dimensional big data. To structure big data, many hashing algorithms that map similar data items to the same bucket to advance the search have been proposed. Locality-Sensitive Hashing (LSH) is a common approach for reducing the number of dimensions of a data set, by using a family of hash functions and a hash table. The LSH hash table is an additional component that supports the indexing of hash values (keys) for the corresponding data/items. We previously proposed the Dynamic Locality-Sensitive Hashing (DLSH) algorithm with a dynamically structured hash table, optimized for storage in the main memory and General-Purpose computation on Graphics Processing Units (GPGPU) memory. This supports the handling of constantly updated data sets, such as songs, images, or text databases. The DLSH algorithm works effectively with data sets that are updated with high frequency and is compatible with parallel processing. However, the use of a single GPGPU device for processing big data is inadequate, due to the small memory capacity of GPGPU devices. When using multiple GPGPU devices for searching, we need an effective search algorithm to balance the jobs. In this paper, we propose an extension of DLSH for big data sets using multiple GPGPUs, in order to increase the capacity and performance of the information retrieval system. Different search strategies on multiple DLSH clusters are also proposed to adapt our parallelized system. With significant results in terms of performance and accuracy, we show that DLSH can be applied to real-life dynamic database systems.

PID Controller Simulator Design for Polynomials Transfer Function

PID controller is a controller used to determine precision of a system instrument employing feedback of the system. The component of PID control can be applied simultaneously or singly depends on the response we desired from a plant. However, there is problem in analyzing planned system response; how to get transfer function from a system and analyze it quickly and easily. As of today, control system engineers still encounter difficulty in analyzing system response especially for transfer function using polynomial equations of degree greater than two and employing trial and error method when analyzing response in the simulation. Thus, the writers design a simulator to solve this problem by using Graphical User Interface. The design of the program can be used for polynomial transfer function and installed directly to computer with smaller memory capacity. Hence, it is more user-friendly and not slowing down the operating system of computer. To ensure that the output of simulation correctly generated, we implemented block diagram modeling in simulink. In the future, the result of this research can be implemented as reference to easily understand the characteristics of PID controller especially for polynomials transfer function.

Numerical Study of the Lift Force, Velocities and Pressure Distribution of a Single Air Bubble and Two Interacting Air Bubbles Rising in Quiescent Liquid

The study of multiphase flow consisting of liquid and air bubbles has been attracting the interest of many researchers. Numerical methods for such a system are, however, facing difficulty in numerical accuracy and a heavy computational load. In this paper, we made corrections to the modified force-coupling method in our previous papers and applied it to the numerical studies of a single air bubble rising near a vertical wall and two interacting air bubbles rising in line in quiescent liquid. Corrections were made to the effective ranges of the force-coupling method. The calculation results showed that the lift force acting on an air bubble obtained by the experimental data was more accurately reproduced than those by our previous method. We accurately calculated the time evolution of the velocities of interacting two air bubbles rising in line obtained in the previous experiments and resolved the physical mechanism of the relative movement of two bubbles. We also found the present method is much quicker and needs much smaller memory capacity than other methods, such as the volume of fluid method.

Acquisition and Data Logging Inertial Navigation System (INS) on Combat Submarine Using Arduino-SD Card

In a combat submarine operating system, navigation device acts as a location information provider on inside or at sea level. Such information is position data provided by GPS (Global Positioning System) and data transmitted by IMU (Inertial Measurement Unit) sensor. Combining these two device is called INS (Inertial Navigation System). This inertial sensor interacts using serial communication data, however records are needed to collect, store and store incoming data in order to be processed easily. Data logging process is feasible as a recorder and data storage using SD Card. Enhancements, such as SD cards are needed because in general system is equipped with a small memory capacity. Arduino is a microcontroller that can assist in process because data obtained from sensor is processed using serial communication lines (RX and TX). Results obtained from calculation and logging data are calculation Roll, Pitch, Heading, Latitude, Longitude, Microseconds, Gyroscope on X axis, Y, Z, Accelerometer on X axis, Y, Z, Magnetometer on X, Y, Z, Velocity North, East, Down. This proves that system acceleration and data logging using Arduino and SD Card can assist in obtaining information and KTBA situations

Congestion Control in CoAP Observe Group Communication.

The Constrained Application Protocol (CoAP) is a simple and lightweight machine-to-machine (M2M) protocol for constrained devices for use in lossy networks which offers a small memory capacity and limited processing. Designed and developed by the Internet Engineering Task Force (IETF), it functions as an application layer protocol and benefits from reliable delivery and simple congestion control. It is implemented for request/response message exchanges over the User Datagram Protocol (UDP) to support the Internet of Things (IoT). CoAP also provides a basic congestion control mechanism. In dealing with its own congestion, it relies on a fixed interval retransmission timeout (RTO) and binary exponential backoff (BEB). However, the default CoAP congestion control is considered to be unable to effectively perform group communication and observe resources, and it cannot handle rapid, frequent requests. This results in buffer overflow and packet loss. To overcome these problems, we proposed a new congestion control mechanism for CoAP Observe Group Communication, namely Congestion Control Random Early Detection (CoCo-RED), consisting of (1) determining and calculating an RTO timer, (2) a Revised Random Early Detection (RevRED) algorithm which has recently been developed and primarily based on the buffer management of TCP congestion control, and (3) a Fibonacci Pre-Increment Backoff (FPB) algorithm which waits for backoff time prior to retransmission. All the aforementioned algorithms were therefore implemented instead of the default CoAP mechanism. In this study, evaluations were carried out regarding the efficiency of the developed CoCo-RED using a Cooja simulator. The congestion control mechanism can quickly handle the changing behaviors of network communication, and thus it prevents the buffer overflow that leads to congestions. The results of our experiments indicate that CoCo-RED can control congestion more effectively than the default CoAP in every condition.

The coevolution of transitive inference and memory capacity in the hawk–dove game

Transitive inference (TI) that uses known relationships to deduce unknown ones (using A > B and B > C to infer A > C given no direct interactions between A and C) to assess the opponent's strength, or resource-holding potential (RHP), is widely reported in animals living in a group. This sounds counter-intuitive because TI seems to require social cognition and larger memory capacity than other inference that does not require social cognition as much as TI; individuals need abilities to identify others, observe contests among others and keep the results in memory. We examine the coevolution of memory and transitive inference by the evolutionary simulations, using the asymmetric hawk–dove game. When a cost for losers is higher than a reward for winners, we found that the immediate inference strategy (II), which estimates the opponent's strength based on the past history of the direct fights, evolves with the large memory capacity, while the TI strategy, which estimates the unknown opponent's strength by transitive inference, evolves with the limited memory capacity. When a cost for losers is slightly higher than a reward for winners, the II strategy with the large memory capacity has an evolutionary advantage over the TI strategy with the limited memory capacity. It is because the direct fights are not so costly that more information about the fights leads to more accurate estimation of the opponent's strength and results in the accurate rank of the RHPs. When a cost for losers is much higher than a reward for winners, the TI strategy with the limited memory capacity has an evolutionary advantage. It is because a good way to avoid the costly fights is the prompt formation of the dominance hierarchy which does not necessarily reflect the actual rank of the RHPs; the TI strategy builds the dominance hierarchy much faster than the II strategy regardless of memory capacity, and the large amounts of information are not required for the TI strategy to form the dominance hierarchy promptly. Our study suggests that even smaller memory capacity is evolutionarily favored in TI. The TI strategy tends to reinforce the hierarchy once it is built, regardless of whether it is consistent with RHP or not, because results of direct fights are always counted. Smaller memory capacity allows players to adjust the hierarchy well if it does not represent RHP. These results prove that TI can evolve without a requirement for large memory.

Design and Evaluation of Compact Real-time Descriptor for Camera Motion Estimation

This paper proposes the image processing algorithm of camera motion estimation that can be used for autonomous mobile robots. Most autonomous mobile robots need to quickly recognize the surroundings so as to move to the space. Moreover, the image processing algorithm requires low computation complexity because the mobile systems need to fulfill the immediate reaction for the spatial movement. Therefore, Compact and Real-time Descriptors (CARD) was proposed in order to extract local image features for corresponding to keypoints between two images. Based on CARD, the proposed image feature descriptor has the ability of scale-invariance and rotation-invariance for extracting image features and is represented by binary description so as to use small memory capacity. Our method uses a multi-scale image pyramid to extract coordinates for keypoints and a log-polar binning pattern for a patch around the keypoints. The results of correspondence for keypoints between two images were good enough to estimate the camera motion, where comparisons to other descriptors such as SIFT, SURF, and FREAK were evaluated.

Locality based warp scheduling in GPGPUs

As the need for high performance computing continues to grow, it becomes more and more urgent to design a massive multi-core processor with high throughput and efficiency. However, when the number of cores keeps increasing, the capacity of on-chip memory is always insufficient. In a multi-core processor such as GPGPU (General Purpose Graphic Processor Unit), dozens or hundreds of SMs (Stream Multi-processor) coordinate to gain high throughput with several MB on-chip memory. Furthermore, in one SM, thousands of threads are organized as thread blocks to process instructions in a SIMT (Single Instruction Multiple Threads) manner. As all the threads share the same on-chip memory, the mismatch between large core number and small on-chip memory capacity can easily impair the performance due to excessive thread contention for cache resource.An efficient thread scheduling method is a promising way to alleviate the problems and to boost performance. From the hardware perspective, the instructions are executed by warps which are made up by a fixed number of threads. So we propose a novel warp scheduling scheme to maintain data locality and to relieve cache pollution and thrashing issues. First, to make full use of time locality, we put the disordered warps into a supervised warp queue and issue the warps from oldest to youngest. To utilize space locality and to hide computation unit stalls, we put forward a new insertion method called LPI (Locality Protected Insertion) to reorder warps in the supervised warp queue to better hide long-latency warps with short-latency warps such as ALU operations and on-chip accesses. Over a wide variety of applications, the new scheduling method gains at most 10.1% and an average of 2.2% improvements over the baseline loose round-robin scheduling.

Blurring emotional memories using eye movements: individual differences and speed of eye movements

BackgroundIn eye movement desensitization and reprocessing (EMDR), patients make eye movements (EM) while recalling traumatic memories. Making EM taxes working memory (WM), which leaves less resources available for imagery of the memory. This reduces memory vividness and emotionality during future recalls. WM theory predicts that individuals with small working memory capacities (WMCs) benefit more from low levels of taxing (i.e., slow EM) whereas individuals with large WMC benefit more from high levels of taxing (i.e., fast EM).ObjectiveWe experimentally examined and tested four prespecified hypotheses regarding the role of WMC and EM speed in reducing emotionality and vividness ratings: 1) EM—regardless of WMC and EM speed—are more effective compared to no dual task, 2) increasing EM speed only affects the decrease in memory ratings irrespective of WMC, 3) low-WMC individuals—compared to high-WMC individuals—benefit more from making either type of EM, 4) the EM intervention is most effective when—as predicted by WM theory—EM are adjusted to WMC.MethodUndergraduates with low (n=31) or high (n=35) WMC recalled three emotional memories and rated vividness and emotionality before and after each condition (recall only, recall + slow EM, and recall + fast EM).ResultsContrary to the theory, the data do not support the hypothesis that EM speed should be adjusted to WMC (hypothesis 4). However, the data show that a dual task in general is more effective in reducing memory ratings than no dual task (hypothesis 1), and that a more cognitively demanding dual task increases the intervention's effectiveness (hypothesis 2).ConclusionsAlthough adjusting EM speed to an individual's WMC seems a straightforward clinical implication, the data do not show any indication that such a titration is helpful.

Recursive maximum likelihood method for the identification of Hammerstein ARMAX system

Identification of Hammerstein nonlinear models has received much attention due to its ability to describe a wide variety of nonlinear systems. This paper considers the parameter estimation problem of ARMAX models for the Hammerstein systems. The recursive maximum likelihood method, which can be applied to online identification and occupies small memory capacity, is proposed to deal with the problem in here. It is an approximation of the maximum likelihood method. The parameters of the linear and nonlinear parts of the Hammerstein model and the noise model can be directly obtained without using the overparameterization technique. Finally, the proposed method is applied to a classic Hammerstein ARMAX system and is compared with RLS method in detail. The research results show the effectiveness of the proposed method.

A Memory-Efficient Implementation of a Plasmonics Simulation Application on SX-ACE

Since recent scientific and engineering simulations require heavy computations with large volumes of data, High-performance Computing (HPC) systems need a high computational capability with a large memory capacity. Most recent HPC systems adopt a parallel processing architecture, where the computational capability of the processors is increasing, however, the performance of the memory system is constrained. The bytes per flop (B/F), which is a ratio of the memory bandwidth to the flop/s, for the HPC systems have been reduced with the evolution of the HPC systems. To fully exploit the potential of the recent HPC systems, and to meet the increasing demand for large memory, it is necessary to optimize practical scientific and engineering applications, considering not only the parallelism of the applications, but also the limitations of the memory subsystems of the HPC systems. In this paper, we discuss a set of approaches to optimization of the memory access behavior of the applications, which enable their executions with improved performance on the recent HPC systems. Our approaches include memory optimizations through memory footprint controlling, restructuring of data structures for active elements, redundant data structure elimination through combined calculations and optimized re-calculation of data. To validate the effectiveness of our approaches, a plasmonics simulation application is evaluated on vector platforms NEC SX-ACE, NEC SX-9, and Intel Xeon based platform NEC LX 406-Re2. By applying our approaches to the implementation, the memory usage of the plasmonics simulation application can be reduced up to nearly 1/71 of the original, and its execution can be possible on a single node of a distributed parallel system with smaller memory capacity. The optimization results in 1.14 times faster execution on SX-ACE and 1.81 times faster execution on LX 406-Re2.

Compressed sensing parallel factor analysis‐based joint angle and Doppler frequency estimation for monostatic multiple‐input–multiple‐output radar

In this study, the authors discuss the topic of joint angle and Doppler frequency estimation in a monostatic multiple-input-multiple-output radar and a compressed sensing parallel factor (CS-PARAFAC) analysis-based algorithm is proposed. In this algorithm, the joint estimation problem is firstly linked to the compressed sensing trilinear model, then the estimated compressed matrix can be derived through trilinear alternating least square method and the angle and Doppler frequency are jointly estimated with sparsity from the compressed matrices. The proposed CS-PARAFAC algorithm, which can obtain automatically paired angle and Doppler frequency estimation, has very close estimation performance to the conventional parallel factor analysis algorithm. When compared to the conventional subspace-based algorithm, such as estimation of signal parameters via rotational invariance techniques, it can achieve much better joint angle and Doppler frequency estimation performance. As the compression, the proposed algorithm has much lower computational complexity and smaller memory capacity meanwhile. Numerical simulations verify the efficiency and illustrate performance improvement of the proposed algorithm.

Dynamic optimization facilitated by the memory tree

Memorizing the past information for later environments is an effective and widely employed approach to optimize dynamic problems. Although the existing explicit memories for dynamic optimization differ widely in the literature, all of them organize memory entries in a linear list. This naive structure leads to problems, such as heavy computational overhead and small memory capacity, and thus restricts the performance of the memories. In this paper, the binary space partition tree is adopted to organize the memory entries, and then a memory tree is constructed. The memory tree partitions the search space into regions. In order to make use of the memory tree, a neighbor shift strategy is proposed. When a new individual is generated in a region that has never been visited since the last change, the new individual is shifted to the neighboring memory individual of that region, if it is less fit than the memory individual. The proposed approach can be easily combined with many population-based algorithms for dynamic optimization in the real space. As examples, the proposed approach was combined with a basic particle swarm optimizer and two state-of-the-art dynamic optimizers. The experimental results showed that it significantly enhanced the performance of the three optimizers on various test problems. The proposed approach demonstrates the importance of memory structure in memory approaches.

컨벌루션 채널코딩 기능의 센서노드 구현

무선 센서 네트워크에서 센서 노드는 주변 환경을 감시하고 데이터를 수집하는 용도로 사용되고 있다. 여러 센서 노드들로 구성된 센서 네트워크는 유비쿼터스 컴퓨팅 분야에 핵심 기술로 주목 받고 있다. 센서 노드는 수집된 정보를 처리하기 위한 MCU와 작은 용량의 메모리를 가지고 있다. 배터리로 동작하는 센서 노드는 한번 배치되면 추가적인 에너지 공급이 불가능하기 때문에 전원 관리 능력이 반드시 필요하다. 또한 ISM 밴드 대역의 주파수를 사용하고 다수의 센서 노드들이 배치된 장소에서 동작하여야 하기 때문에 같은 센서 노드와 같은 대역을 사용하는 이종 기기간의 전파 간섭이 발생하는 열악한 통신환경에서 가지고 있다. 본 논문에서는 무선 센서 네트워크의 오류 제어 기법으로 사용되는 ARQ 기법의 문제점인 오류가 발생 했을 시 재전송으로 인한 추가적인 에너지 소비를 줄이기 위해 오류정정기법인 컨벌루션 부호의 적용을 제안하였다. 제안된 컨벌루션 부호를 센서 네트워크 OS를 통하여 센서 노드에 적용하여 전송전력 -19.2dbm과 -25dbm 에서 거리를 10m, 15m, 20m로 두고 BER을 측정하였다. 측정된 BER을 통해 패킷손실률과 평균 재전송 횟수를 계산하여 컨벌루션 부호를 적용하였을 때 그 성능을 분석하였다. 실험결과 -19.2dbm에서는 9~12%의 평균 재전송 횟수 이득을 -25dbm에서는 12%~19%의 이득을 얻을 수 있음을 확인하였다. Sensor nodes are used for monitoring and collecting the environmental data via wireless sensor network. The wireless sensor network with various sensor nodes draws attention as a key technology in ubiquitous computing. Sensor nodes has very small memory capacity and limited power resource. Thus, it is essential to have energy efficient strategy for the sensor nodes. Since the sensor nodes are operating on the same frequency bands with ISM frequency bands, the interference by the devices operating on the ISM band degrades the quality of communication integrity. In this paper, the convolutional code is proposed instead of ARQ for the error control for the sensor network. The proposed convolutional code was implemented and the BER performance is measured. For the fixed transmitting powers of -19.2 dBm and -25dBm, the BER with various communication distances are measured. The packet loss rate and the retransmission rate are calculated from the measured BER. It is shown that the porposed method obtained about 9~12% and 12-19% reduction in retransmission rate for -19.2 dBm and -25 dBm respectively.