Small Loop Bandwidth Research Articles

Linear CMOS $LC$ -VCO Based on Triple-Coupled Inductors and Its Application to 40-GHz Phase-Locked Loop

A linear CMOS $LC$ voltage-controlled oscillator (VCO) utilizing triple-coupled inductors and a 40-GHz integer-N phase-locked loop (PLL) are fabricated in a standard 90-nm CMOS process. The VCO utilizes triple-coupled inductors to couple varactor pairs, which compensate each other to linearize the VCO gain. The triple-coupled $LC$ tank is theoretically analyzed using equivalent circuit models. With the triple-coupled inductors, there is no need for tuning-voltage shifting circuits or dc-block capacitors, suitable for high-performance millimeter-wave (mm-wave) VCO design. A 40-GHz PLL has also been design and built around this linear $LC$ -VCO to demonstrate a stable PLL with small loop bandwidth variations. The measured tuning bandwidth, phase noise, and figure of merit (FOM $_{T}$ ) of the linear VCO is 15.8%, −100.7 dBc/Hz at 1-MHz offset, and −181.8 dBc/Hz, respectively. Utilizing the linear VCO, the experimental PLL is stably locked from 38.61 to 44.55 GHz. The PLL without output buffer consumes 76 mW from 1.5/1.0 V supplies. The measured in-band and out-band phase noise of the 40-GHz PLL are −81 dBc/Hz at 100-kHz offset, and −114.5 dBc/Hz at 10-MHz offset, respectively. Thanks to the proposed linearization method, the VCO gain shows very small variations, compared with reported works. The implemented PLL demonstrates good stabilities with small loop bandwidth variations across the operation frequency range.

Optoelectronic Feedback Loop for Phase Noise Suppression in THz Self-Heterodyne Detection

A novel terahertz (THz) self-heterodyne detection system using an optoelectronic feedback loop is proposed. Conventional THz self-heterodyne detection system is inherently vulnerable to phase noise associated with the optical path length difference between the laser sources and the photomixer. The proposed THz self-heterodyne detection system utilizes the optoelectronic feedback loop to suppress the phase noise of the intermediate frequency signal at the output of the photomixer. The optoelectronic feedback loop requires a feedback loop with a relatively small loop bandwidth and thus is implemented without using rather sophisticated integrated photonics technology. The proposed THz self-heterodyne detection system with the optoelectronic feedback loop suppresses the phase noise by more than 25 dB.

2.5 Gbps clock data recovery using 1/4th-rate quadricorrelator frequency detector and skew-calibrated multi-phase clock generator

Abstract. A Gb/s clock and data recovery (CDR) circuit using 1/4th-rate digital quadricorrelator frequency detector and skew-calibrated multi-phase voltage-controlled oscillator is presented. With 1/4th-rate clock architecture, the coil-free oscillator can have lower operation frequency providing sufficient low-jitter operation. Moreover, it is an inherent 1-to-4 DEMUX. The skew calibration scheme is applied to reduce phase offset in multi-phase clock generator. The CDR with frequency detector can have small loop bandwidth, wide pull-in range and can operate without the need for a local reference clock. This 1/4th-rate CDR is implemented in standard 0.18 μm CMOS technology. It has an active area of 0.7 mm2 and consumes 100 mW at 1.8 V supply. The CDR has low jitter operation in a wide frequency range from 1–2.25 Gb/s. Measurement of Bit-Error Rate is less than 10−12 for 2.25 Gb/s incoming data 27−1 PRBS, jitter peak-to-peak of 0.7 unit interval (UI) modulation at 10 MHz.

The effect of non‐ideal interpolation on symbol synchronizer performance

AbstractThis contribution deals with the symbol synchronizer performance of a fully digitally implemented receiver, operating on a narrowband M‐PSK signal (one‐sided bandwidth not exceeding the symbol rate). The considered digital receiver operates on samples of the complex envelope r(t) of the received signal, taken by a fixed clock which is not synchronized to the transmitter clock. The synchronized samples required for the symbol synchronization algorithm are computed by interpolating between the available non‐synchronized samples. Because of finite memory, interpolation is non‐ideal; hence, some amount of distortion is introduced, which affects the performance of the symbol synchronizer. By means of theoretical analysis, we investigate the tracking performance of a specific decision‐directed feedback synchronizer, assuming interpolation of orders zero, one and two. We show that non‐ideal interpolation gives rise to a loop noise spectrum containing spectral lines, that mainly occur near/= 0 when the number of samples per symbol is close to an integer. Unless a sufficiently small loop bandwidth is chosen, the contribution of these spectral lines could dominate the timing error variance, which then becomes much larger than for synchronized sampling.