Small Lookup Table Research Articles

Lookup Table Merging for FPGA Technology Mapping

Higher logic density is a key goal pursued by Field Programmable Gate Arrays (FPGA). The higher the logic density is, the lower the cost of the circuit spends, and the shorter the line length of the circuit is, the less power is required. Technology mapping is used to map technology-independent logic gates into a lookup table (LUT) netlist. A big problem with the 6-input LUT used in the FPAG at the present stage is that the utilization rate of the lookup table is insufficient. Modern FPGA architectures have good support for dual-output LUTs. We can merge two small LUTs into a new dual-output LUT, if the total number of inputs of the two small LUTs is not greater than the input limit specified by the LUT, thereby reducing the area, that is, reducing the number of LUTs. In this paper, the dual-output LUTs are merged in the technology mapping stage, and a new method of merging single-output LUTs into dual-output LUTs is proposed. The experimental results show that the algorithm used in this paper has an average reduction of 10.21 % in the number of LUTs without worsening delay.

Research and Implementation of a Numerical Control Oscillator with Improved Pipelined CORDIC Algorithm

As the recognized core of electronic systems, frequency synthesizers have been applied in many communication fields. NC oscillator (NCO) is the main component of the frequency synthesizer. It helps to generate high-precision and high-frequency signals, so it has been widely used. NCO implementation methods include table lookup method, polynomial expansion method, coordinate rotation digital computer (CORDIC) algorithm, etc. CORDIC algorithm is one of many commonly used methods in trigonometric function calculation and digital signal processing, and is often used as the core of DDS (direct digital synthesis) to generate signals. Compared with table lookup and polynomial expansion, CORDIC algorithm has higher efficiency in signal generation and hardware utilization. In view of the disadvantages of traditional CORDIC algorithm, which takes up large resources and has relatively slow calculation speed, in order to improve the output efficiency, this paper uses an efficient 12-stage pipelined CORDIC architecture and a very small lookup table (LUT) to implement a sine wave generator. The system is coded and simulated in Quartus and ModelSim. The results show that the proposed structure can increase the operating speed of the system from 217.77 MHz to 291.04 MHz, and improve the output efficiency of the system.

Uplink Signal Detection via Look-Up Table-Based AMP for Massive MIMO Systems

We propose a novel look-up table (LUT)-based multi-user detection (MUD) algorithm to imitate approximate message passing (AMP) for uplink signal detection in massive multi-user multi-input multi-output (MU-MIMO) systems. When AMP is implemented with double-precision arithmetic, the dramatic increase in power consumption and process latency becomes a major barrier to practical application, as the system scale expands. To circumvent this issue, we design a novel referential AMP detector composed of many small LUTs cascaded hierarchically, where only informative integer-valued messages are exchanged on a factor graph (FG). Our method tracks the discrete distribution of the LUT outputs according to the multi-layer structure, and successively determines non-uniform quantization thresholds of the LUTs, using an unsupervised learning approach. Specifically, the thresholds at each level of the hierarchy, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i.e</i> ., layer, are optimized by clustering with the Lloyd-Max algorithm with initial values given by the k-means++ method, in order to minimize the performance degradation caused by quantization errors. The efficacy of the proposed referential AMP detector is confirmed by numerical simulations, which show that the proposed method significantly outperforms the state-of-the-art (SotA) in terms of the bit error rate (BER) performance in various channel models. The results also indicate the referential AMP is robust to changes in wireless channels, and then clarify the reason in terms of the algorithmic structure.

Non-iterative division circuit design with accuracy and performance trade-off based on mixed integer linear programming approach

A wide range of applications such as image/video processing involve arithmetic division and demand high computing performance but can tolerate some degree of errors or allow small deviations from their theoretical results. This paper presents an approach for non-iterative arithmetic division circuit design, leveraging computation accuracy for high performance. The quotient is modeled as a curved surface and the surface is partitioned into many small rectangular planar stripes for linearity. Mixed integer linear programming is adopted to optimize the worst case error due to approximation in each stripe. As a result, an architecture for the division circuits consisting of simple additions and a small look-up table is achieved. The accuracy achieved in terms of the maximum absolute error percentage (MAEP) ranges from 0.44% to 0.11%. Comparing the proposed designs with the existing counterparts with similar MAEP, the area-delay product (ADP) is reduced by more than 40%. Compared to the counterpart with the closest ADP by the single stage logarithmic method, the proposed circuit has a smaller MAEP with 45% reduction. Comparing with the existing non-iterative division circuit by the curve fitting method, the proposed circuit has lowered MAEP and ADP by 21% and 27% respectively.

Ultrafast line detector

This article introduces the fastest line detector so far published in the literature. This algorithm is 14.88 times faster than the next fastest line detector, the EDLines, and 94.7 times faster than the line segment detector. It is hundreds of times faster and more reliable than the Standard Hough Transform. The article also introduces an ingeniously simple method for detecting and combining patterns. The algorithm takes advantage of several look-up tables to recognize and fit straight-line patterns. As the first step, it recognizes any possible 4 × 4 pixel line patterns among the binary edge pixels and then uses several small look-up tables to decide whether the connected patterns form a line or not. It is specially designed for real-time processing of the high-resolution images such as the ones used in computer vision applications.

A 0.61-μJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using Convolutional Non-Linear Neural Network

A pipelined wired-logic deep neural network (DNN) processor implemented in a 16-nm field-programmable gate array (FPGA) is presented. The latency and power required for memory access are minimized by utilizing the wired-logic architecture, thus enabling low power and high throughput operation. One technical issue with the wired-logic architecture is that it requires a lot of hardware resources. To reduce them, two core technologies are developed: (1) a convolutional non-linear neural network (CNNN) and (2) a pipeline-type neuron cell. The CNNN optimizes both the network structure and the non-linear activation function of each neuron by using a newly developed back-propagation-based training method. While conventional reinforcement learning can train only a small size network thus limiting its application to handwritten number recognition, the proposed CNNN enables a larger network size making it applicable to object recognition. The pipeline-type neuron cell has a small look-up table (LUT) to process non-linear functions using only a small amount of hardware resources. These two technologies enable the implementation of the entire network on a single FPGA chip with the wired-logic architecture. Three types of CNNN trained on the CIFAR-10 dataset are implemented in 16-nm FPGAs. An energy efficiency of 0.09, 0.12, and <inline-formula> <tex-math notation="LaTeX">$0.61~\mu \text{J}$ </tex-math></inline-formula>/frame is achieved with 70&#x0025;, 75&#x0025;, and 82&#x0025; accuracy, respectively. Compared with a state-of-the-art accelerator using a binary neural network (BNN), the energy efficiency is improved by more than two orders of magnitude.

Efficient Encoding of Constrained Block Codes

We present coding methods for generating $\ell$ -symbol constrained codewords taken from a set, $\mathcal{\mathcal { S }}$ , of allowed codewords. In standard practice, the size of the set $\mathcal{S}$ , denoted by $M=|\mathcal{S}|$ , is truncated to an integer power of two, which may lead to a serious waste of capacity. We present an efficient and low-complexity coding method for avoiding the truncation loss, where the encoding is accomplished in two steps: first, a series of binary input (user) data is translated into a series of $M$ -ary symbols in the alphabet $\mathbb{M}=\{0, \ldots, M-1\}$ . Then, in the second step, the $M$ -ary symbols are translated into a series of admissible $\ell$ -symbol words in $\mathcal{S}$ by using a small look-up table. The presented construction of Pearson codes and fixed-weight codes offers a rate close to capacity. For example, a 255B320B balanced code, where 255 source bits are translated into 32 10-bit balanced codewords, has a rate 0.1% below capacity.

A simplified variant of tabled asymmetric numeral systems with a smaller look-up table

Data storage is an indispensable part of data management system. Asymmetric numeral systems (ANS) is a widely used compression algorithm. A number of implementations, such as range asymmetric numeral systems (rANS) and tabled asymmetric numeral systems (tANS), were proposed. However, rANS requires some costly arithmetic operations (integer additions, multiplications and divisions), and tANS requires large space to store the entire behavior in a look-up table. When the integer addition is allowed, this paper proposes a variant of tANS, that requires much smaller look-up table than the conventional tANS. In addition, a decoding algorithm to decode multiple symbols at once is proposed. The simulation shows that with a slight loss of compression ratio (approximately $$0.5\%$$ lower), the proposed method has up to a $$25\%$$ ( $$60\%$$ ) better throughput than rANS in encoding (decoding).

Convergence verification of the Collatz problem

This article presents a new algorithmic approach for computational convergence verification of the Collatz problem. The main contribution of the paper is the replacement of huge precomputed tables containing $$O(2^N)$$ entries with small lookup tables comprising just O(N) elements. Our single-threaded CPU implementation can verify $$4.2 \times 10^9$$ 128-bit numbers per second on Intel Xeon Gold 5218 CPU computer, and our parallel OpenCL implementation reaches the speed of $$2.2 \times 10^{11}$$ 128-bit numbers per second on NVIDIA GeForce RTX 2080. Besides the convergence verification, our program also checks for path records during the convergence test.

A Crossbar-Based In-Memory Computing Architecture

To address the von Neumann bottleneck that leads to both energy and speed degradations, in-memory processing architectures have been proposed as a promising alternative for future computing applications. In this paper, we present an in-memory computing system based on resistive random-access memory (RRAM) crossbar arrays that is reconfigurable and can potentially perform parallel and general computing tasks. The system consists of small look-up tables (LUTs), a memory block, and two search auxiliary blocks, all implemented in the same RRAM crossbar array. External data access and data conversions are eliminated to allow operations fully in-memory. Details of addition, AND logic and multiplication operations are discussed on the basis of search and writeback steps. A compact instruction set consisting of 10 instructions is demonstrated on this architecture through circuit level simulations. Performance evaluations show that the proposed in-memory computing architecture is suitable for handling data-intensive problems. The average power consumption of the crossbar chip is estimated to be 45μW.

High-Performance Hardware Design of Block LMS Adaptive Noise Canceller for In-Ear Headphones

This article presents a high-performance hardware design of block least mean square adaptive noise canceller (ANC) for in-ear headphones applications. It is based on distributed arithmetic, which stores filter partial products in look-up table (LUT). The proposed technique splits LUTs into two smaller LUTs and stores the filter partial products in offset-binary-coding form. Furthermore, the splitted LUTs are shared to compute the filter output and coefficient-increment terms. A novel strategy is also presented to update LUT contents. Compared with the best existing design, the proposed ANC for 32nd filter order requires 50% less LUT words, 5.31% less adders, 28.57% high-throughput, and relatively less critical path-delay. From the implementation results, it is found that the logic utilization of the proposed design is significantly reduced while achieving better noise cancelling performance. For example, the proposed ANC for 32nd filter order provides noise reduction of about 6–20 dB and utilizes 1.80 times less LUTs and 1.71 times less flip-flops over the best existing design.

A lightweight BLASTP and its implementation on CUDA GPUs

The BLAST server in the National Center for Biotechnology Information in the USA receives tens of thousands of queries per day on average. However, the service is always the same for every query even though query lengths vary significantly. In fact, the lengths of a large portion of protein sequences are less than 500. On the other hand, the hit detection process consumes the most of the execution time of BLAST and its core architecture is a lookup table. Following the above reasons, we propose a lightweight BLASTP for servicing not-too-long queries, where a hybrid query-index table is proposed accordingly. Each table entry consists of four bytes that can store up to three query positions. Therefore, a sequence word usually requires only one memory fetch to retrieve its hit information. Furthermore, additional dummy entries are embedded into the table and interleaved with original entries. The entries without any hits and dummy entries both can be used to buffer spilled query positions. The above features result in a much smaller lookup table with a higher utilization rate and a lower cache miss ratio. Experimental results show that the lightweight BLASTP outperforms CUDA-BLASTP with speedups ranging from 1.82 to 3.37 based on the first two critical phases.

Simplified double switching SVPWM implementation for three‐level VSI

A generalised space vector pulse width modulation (SVPWM) framework for the realisation of all double switching states with a memory-optimised method is proposed to reduce the total harmonic distortion (THD) and to provide neutral point voltage balancing for three-level NPC voltage source inverter (VSI). The proposal provides an efficient SVPWM implementationwith reduced hardware requirement and zero increase in software complexity in comparison to the existing schemes. Microcontroller analogue-to-digital converter (ADC) hardware replaces multichannel ADC and associated Field programmable gate array hardware in this proposal. The proposed method follows digital control architecture and eliminates the need to sample phase voltages separately. The proposed algorithm samples rms voltage of one phase and generates eight bit modulation index command by a suitable compensation algorithm. The implemented SVPWM algorithm takes the modulation index command value and generates phase voltage values by multiplying with the stored sine angle values. Gate pulses are generated in the proposed implementation by the hardware pulse width modulation (PWM) block and there is no need for digital-to-analogue converter. The proposed strategy is validated with a fundamental frequency of 50 Hz on a 2 KVA three-phase three-level insulated gate bipolar transistor-based VSI using low-cost PIC microcontroller. The superiority of the proposed method lies in providing an efficient three-level SVPWM implementation with reduced THD, neutral point voltage balancing, reduced hardware requirement, small lookup table and zero increase in the software computing overhead.

Effect of center voltage vectors (CVVs) of three-level space plane on the performance of dual inverter fed open end winding induction motor drive

Dual inverter fed open end winding induction motor (IM) drive offers many advantages over other multilevel inverter fed IM drives. Pulse width modulation (PWM) techniques are employed for the control of output voltage and frequency. Space vector base PWM techniques are popular among all the PWM techniques. A simplified space vector PWM method with simple and small look-up table approach is presented for dual inverter configuration. Moreover the proposed space vector based PWM technique provides freedom in selecting the center voltage vector (CVV) by which different PWM techniques will be derived. The implementation of all these PWM techniques is generalized by using a constant a <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> . The derived PWM techniques show superior performance in reducing the zero sequence voltage (ZSV) by maintaining the same quality of output voltage. The performance of all these PWM techniques are evaluated theoretically and verified in real time through dSPACE 1104 control board.

A 2.2-GHz Configurable Direct Digital Frequency Synthesizer Based on LUT and Rotation

This paper proposes a configurable direct digital frequency synthesizer (DDFS) based on the lookup-table (LUT)- rotation architecture. To break through the limitation of the single mode, the proposed DDFS is the first attempt which supports four-mode switching on chip. Taking the advantages of small LUT size and pipelined rotation, the DDFS achieves both high-speed and high-resolution properties. The multi-bit rotation tree is helpful to reduce the latency and register usage, which improves the agility and energy efficiency of the DDFS. A partition problem is raised in this paper, and we estimate the optimal solution through both the theory and experiment. Based on the partition, an output can achieve the highest spurious-free dynamic range (SFDR) with as small as possible LUT size. The functionality of the proposed DDFS has been validated in a Xilinx ZedBoard field-programmable gate array. The synthesis and layout results show that the chip achieves maximum 102-dBc SFDR and 2.2-GHz clock frequency. The power consumption and latency cycles reach minimum 6.9 mW/GHz and 7 cycles, which are 20% and 30% reduction compared with the state-of-the-art DDFS.

A reduced size look up table for sinusoidal wave generation in digital modulators applications

Digital Modulators is one of the areas that have received great attention recently due to the tremendous developments in Radio Frequency (RF) frond ends and system on chips (soc) architecture in general. Building any kind of digital modulators using soc type Field Programmable Gate Array (FPGA), like ZYBO, depends heavily on how the carrier signal got generated since it consumes a lot of utilization recourses. This paper presents a new method of generating sinusoidal carrier signal based on Direct Digital Synthesizer (DDS) concept using small size Look Up Table (LUT). 64 samples of a quarter period of the sine wave signal were stored in a fixed point format in small LUT to generate the carrier at the desire frequency. The paper used Very high speed integrated circuit Hardware Descriptive Language (VHDL) without the help of DSP Builder Tools or XILINX System Generator. The suggested method was tested by building simple modulators like On-Off Keying (OOK) and Amplitude Shift Keying (ASK). Low utilization was achieved as compared to other implementation methods.

Exploiting error control in matrix coding-based data hiding over lossy channel

A steganographic scheme, matrix coding-based data hiding (MCDH), is constructed from covering function to enhance embedding efficiency, and, meanwhile, decrease the required changed bits. However, the MCDH may be compromised when using it as steganography over lossy channel. In this paper, we consider the so-called error spreading problem that one-bit error in MCDH may give rise to multi-bit errors when extracting the hidden data. In this paper, we present new MCDH to overcome error spreading problem based on constant weight code. Our new approach uses small lookup table to reduce embedding/extracting complexity. Experimental results demonstrate a better performance than previously proposed MCDHs in terms of spreading errors against lossy channel.

Hardware Division by Small Integer Constants

This article studies the design of custom circuits for division by a small positive constant. Such circuits can be useful for specific FPGA and ASIC applications. The first problem studied is the Euclidean division of an unsigned integer by a constant, computing a quotient and remainder. Several new solutions are proposed and compared against the state-of-the-art. As the proposed solutions use small look-up tables, they match well with the hardware resources of an FPGA. The article then studies whether the division by the product of two constants is better implemented as two successive dividers or as one atomic divider. It also considers the case when only a quotient or only a remainder is needed. Finally, it addresses the correct rounding of the division of a floating-point number by a small integer constant. All these solutions, and the previous state-of-the-art, are compared in terms of timing, area, and area-timing product. In general, the relevance domains of the various techniques are different on FPGA and on ASIC.

An adaptive point sampler on a regular lattice

We present a framework to distribute point samples with controlled spectral properties using a regular lattice of tiles with a single sample per tile. We employ a word-based identification scheme to identify individual tiles in the lattice. Our scheme is recursive, permitting tiles to be subdivided into smaller tiles that use the same set of IDs. The corresponding framework offers a very simple setup for optimization towards different spectral properties. Small lookup tables are sufficient to store all the information needed to produce different point sets. For blue noise with varying densities, we employ the bit-reversal principle to recursively traverse sub-tiles. Our framework is also capable of delivering multi-class blue noise samples. It is well-suited for different sampling scenarios in rendering, including area-light sampling (uniform and adaptive), and importance sampling. Other applications include stippling and distributing objects.

Efficient 3-D Model-Based Reconstruction Scheme for Arbitrary Optoacoustic Acquisition Geometries.

Optimal optoacoustic tomographic sampling is often hindered by the frequency-dependent directivity of ultrasound sensors, which can only be accounted for with an accurate 3-D model. Herein, we introduce a 3-D model-based reconstruction method applicable to optoacoustic imaging systems employing detection elements with arbitrary size and shape. The computational complexity and memory requirements are mitigated by introducing an efficient graphic processing unit (GPU)-based implementation of the iterative inversion. On-the-fly calculation of the entries of the model-matrix via a small look-up table avoids otherwise unfeasible storage of matrices typically occupying more than 300GB of memory. Superior imaging performance of the suggested method with respect to standard optoacoustic image reconstruction methods is first validated quantitatively using tissue-mimicking phantoms. Significant improvements in the spatial resolution, contrast to noise ratio and overall 3-D image quality are also reported in real tissues by imaging the finger of a healthy volunteer with a hand-held volumetric optoacoustic imaging system.