Small Lookup Table Research Articles

Distributed Arithmetic based Low-Power LMS Adaptive FIR Filter Design

filtering forms a significant class of DSP algorithms employed in several hand held mobile devices for applications like echo cancellation, signal de-noising, and channel equalization. This paper presents a different pipelined architecture for low-power implementation of Adaptive filter based on distributed arithmetic (DA). The traditional adder- based shift accumulation for Distributed Arithmetic based computation of inner-product is swapped by conditional signed carry-save accumulation. A fast bit clock is employed only for carry-save accumulation which results in reduction of power consumption in the proposed design, while use of a much slower bit clock is used for rest of the operations. It contains the smaller Look-Up Table (LUT), same quantity of multiplexers and almost half the number of adders in comparison to the existing Distributed Arithmetic-based design. By changing the inner block, a reduction in power consumption is aimed at. So the previous DA-based adaptive filter in average for filter lengths N=4 and N=16 have been implemented.

An Area-Efficient Unified Architecture for Multi-Functional Double-Precision Floating-Point Computation

In this paper, we propose a unified architecture for computation of double-precision floating-point division, reciprocal, square root, inverse square root and multiplication with a significant area reduction. First, a double-precision multiplication-based divider, the common datapath shared with these arithmetic computations, is optimized by a modified Goldschmidt algorithm to achieve better area efficiency. In this algorithm, a linear-degree minimax approximation instead of second-degree is used to obtain a 15-bit precision estimate of the reciprocal so that we can get a rather small lookup table (LUT) as well as reduced amount of computation when accumulating the partial products. Two Goldschmidt iterations specially designed for hardware reuse are performed to gain the final accurate result of division. By virtue of the pipelined processing, the time cost for the two iterations is minimized. Second, a reconfigurable datapath with a little extra area cost is introduced to dynamically support multiple double-precision computations by executing the optimized divider iteratively. The design is finally implemented and synthesized in SMIC 0.13-μm CMOS process. The experimental results show that the proposed design can achieve a speed of 400 MHz with area of 61.6 K logic gates and 9-Kb LUT. Compared with other works, the area efficiency (performance/area ratio) of the proposed unified architecture is increased by about 20% in average, which is a better performance-area trade-off for embedded microprocessors.

<inline-formula> <tex-math notation="TeX">$(M,p,k)$</tex-math></inline-formula>-Friendly Points: A Table-Based Method to Evaluate Trigonometric Function

Linear (order-1) function evaluation schemes, such as bipartite and multipartite tables, are usually effective for low- precision approximations. For high-output precision, the lookup table size is often too large for practical use. This brief investigates the so-called (M,p,k) scheme that reduces the range of an input argument to a very small interval so that trigonometric functions can be approximated with very small lookup tables and a few additions/subtractions. An optimized hardware architecture is presented and implemented in both a field-programmable gate array device and standard-cell-based technology. Experimental results show that the proposed scheme achieves more than a 50% reduction in total chip area compared with the best linear approach for a 24-bit evaluation.

Fast decoding of the binary (31, 16, 7) quadratic residue code

A fast and efficient table-lookup decoding algorithm, called message-syndrome decoding algorithm (MSDA), is proposed to correct all patterns of three or fewer errors in the binary systematic (31, 16, 7) quadratic residue code. The decoding technique of the MSDA is based on the properties of the cyclic codes, the one-error syndrome in the message part, the weight of syndrome, and the weight of syndrome difference. Thus, the size of the lookup table and computational complexity in the finite field can be significantly reduced. The MSDA merely needs a very small message-syndrome lookup table (MSLT) which consists of 16 syndromes. The memory size of the MSLT is the smallest compared with other existing lookup tables and the simulation results show that the decoding speed of the MSDA exceeds other proposed table-lookup decoding algorithms.

Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic

This brief presents a novel pipelined architecture for low-power, high-throughput, and low-area implementation of adaptive filter based on distributed arithmetic (DA). The throughput rate of the proposed design is significantly increased by parallel lookup table (LUT) update and concurrent implementation of filtering and weight-update operations. The conventional adder-based shift accumulation for DA-based inner-product computation is replaced by conditional signed carry-save accumulation in order to reduce the sampling period and area complexity. Reduction of power consumption is achieved in the proposed design by using a fast bit clock for carry-save accumulation but a much slower clock for all other operations. It involves the same number of multiplexors, smaller LUT, and nearly half the number of adders compared to the existing DA-based design. From synthesis results, it is found that the proposed design consumes 13% less power and 29% less area-delay product (ADP) over our previous DA-based adaptive filter in average for filter lengths N = 16 and 32. Compared to the best of other existing designs, our proposed architecture provides 9.5 times less power and 4.6 times less ADP.

From cryptography to hardware: analyzing and protecting embedded Xilinx BRAM for cryptographic applications

The design of cryptographic applications needs special care. For instance, physical attacks like side-channel analysis (SCA) are able to recover the secret key, just by observing the activity of the computation, even for mathematically robust algorithms like AES. SCA considers the “leakage” of a well chosen intermediate variable correlated with the secret. Field programmable gate-arrays (FPGA) are often used for hardware implementations for low to medium volume productions or when flexibility is needed. They offer many possibilities for the computation, like small look-up tables (LUT) and embedded block memories (BRAM). Certain countermeasures can be deployed, like dual-rail logic or masking, to resist SCA on FPGA. However to design an effective countermeasure, it is of prime importance for a designer to know the main leakage sources of the device. In this paper, we analyze the leakage source of a Xilinx Virtex V FPGA by studying three different AES architectures. The analysis is based on real measurements by using specific leakage models of the sensitive variable, adapted to each architecture. Our results demonstrate that, BRAM which were considered to leak less traditionally, are found to be equally vulnerable if we change the attack target from address register to output latch. We also show that if the leakage model is known, simple countermeasures with only 16 % overhead can be deployed to overcome the leakage.

ALMmap: Technology Mapping for FPGAs With Adaptive Logic Modules

Modern field programmable gate arrays like Altera's Stratix Series have adopted the adaptive logic module (ALM) structure due to its potential performance and area advantages. An ALM can implement a single logic function or can be fractured into two smaller lookup tables (LUTs). In this paper, we propose an ALM mapping algorithm, ALMmap, for area minimization with bounded depth. We revamp the traditional iterative cut-based mapping flow and introduce a procedure for bounded depth mapping generation with dynamic area recovery that effectively combines cut selection, mapping, and area recovery together. In addition, we introduce a new procedure for computing cut set for ALM minimization under a depth constraint. The notion of area flow which has been used successfully for cut selection to reduce LUT count is revised for cut selection to reduce ALM count. ALMmap obtains depth optimal solutions that are 25.6% and 11.6% smaller, on average, than those produced by a classical mapper and WireMap, respectively.

Ellipse Expanding Method for Minimum Distance-Based MIMO Precoder

This letter proposes a new MIMO precoding method for dual-stream data transmission based on the criterion of minimum Euclidean distance. The problem is optimally solved by expanding an ellipse within a 2-dimensional lattice to the maximum extent. A closed-form expression of minimum Euclidean distance is derived for square quadrature amplitude modulation (QAM) constellations. The ellipse expanding method (EEM) allows for very efficient implementation by checking a small lookup table with respect to the condition number of channel matrix. Illustrative examples validate the promising performance of the proposed method in comparison with existing schemes.

Efficient Real-Time Generation of Bit-Wise Parallel Representations of Oversampled Carrier Replicas

An algorithm has been developed that efficiently generates in-phase and quadrature carrier replicas over a range of Doppler shift frequencies and initial phase offsets. This algorithm provides a new method that aids in bit-wise parallel baseband mixing of signals in software radios, specifically targeted at GNSS radios. Bit-wise parallel correlation, of which one step is baseband mixing, provides a processing time speed-up when correlating signals that are digitized to a low number of bits, as opposed to the standard multiply-and-accumulate correlation. The new algorithm makes use of the small phase differences between a set of signals that have a large ratio of the IF to the Doppler shift frequency. It uses specially-designed look-up tables to generate carrier replicas on-the-fly. This new algorithm can efficiently generate bit-packed carrier replicas using a small look-up table (10-100 s of kBytes).

New high resolution and low distortion coherent sweep oscillators

In this paper, a new coherent digital sweep oscillator is proposed and its performance is evaluated. The proposed oscillator employs piecewise parabolic interpolation to decrease the look-up-table (LUT) size and system complexity while maintaining excellent spectral performance. The interpolation coefficients are predetermined in such a way that optimizes the spectral performance of the oscillator and are stored in the LUT. The interpolator generates the sample values of the sine wave using the optimized predetermined interpolation coefficients from the calculated phase. Hence, a few reference sample values and the optimized coefficients are stored in a small LUT. The complexity of the oscillator structure is decreased by eliminating one of the two multipliers needed to implement the interpolator. The proposed oscillator is simulated using optimized coefficients for different number of quarter sine wave segments. A comparison between the new oscillator and previously reported sweep oscillators indicates its superior performance and hardware efficiency. The ratio of the LUT size needed for the new oscillator is found to be 1:128 when compared with that of Pedersen oscillator with 12-bit address lines and 14-bit word length.

A posteriori inclusion of parton density functions in NLO QCD final-state calculations at hadron colliders: the APPLGRID project

A method to facilitate the consistent inclusion of cross-section measurements based on complex final-states from HERA, TEVATRON and the LHC in proton parton density function (PDF) fits has been developed. This can be used to increase the sensitivity of LHC data to deviations from Standard Model predictions. The method stores perturbative coefficients of NLO QCD calculations of final-state observables measured in hadron colliders in look-up tables. This allows the a posteriori inclusion of parton density functions (PDFs), and of the strong coupling, as well as the a posteriori variation of the renormalisation and factorisation scales in cross-section calculations. The main novelties in comparison to original work on the subject are the use of higher-order interpolation of Lagrangian form, which substantially improves the trade-off between accuracy and memory use, and a CPU and computer memory optimised way to construct and store the look-up table using modern software tools. It is demonstrated that a sufficient accuracy on the cross-section calculation can be achieved with reasonably small look-up table size by using the examples of jet production and electro-weak boson (Z, W) production in proton-proton collisions at a center-of-mass energy of 14 TeV at the LHC. The use of this technique in PDF fitting is demonstrated in a PDF-fit to HERA data and simulated LHC jet cross-sections as well as in a study of the jet cross-section uncertainties at various centre-of-mass energies.

Digital Synthesizer/Mixer With Hybrid CORDIC–Multiplier Architecture: Error Analysis and Optimization

This paper describes a novel architecture for digital synthesizer/mixer (DSM). The operation performed by a DSM corresponds to a rotation of the input vector in the complex plane. The proposed architecture divides this rotation into three subrotations. The first one uses a few CORDIC stages, in which the rotation directions are in parallel computed with the help of a small lookup table. The CORDIC algorithm is employed also in the second subrotation, where the rotation directions are readily available after a simple recoding of the bits of the residual angle. The final rotation is multiplier based to reduce circuit latency and increase performances. A detailed error analysis and sizing methodology is given in this paper. It is shown that different versions of the architecture can be conceived by varying the dimensions of the second block and the topology of the third block. The proposed architecture exhibits very good performances, owing to the efficient carry-save implementation of CORDIC datapaths, the reduced lookup table, and the small size of multipliers. Implementations in a 0.25- mum CMOS technology are presented in order to demonstrate the design methodology and to investigate the implementation tradeoffs.

Medium-Grain Cells for Reconfigurable DSP Hardware

Reconfigurable hardware contains an array of programmable cells and interconnection structures. Field-programmable gate arrays use fine-grain cells that implement simple logic functions. Some proposed reconfigurable architectures for digital signal processing (DSP) use coarse-grain cells that perform 16-b or 32-b operations. A third alternative is to use medium-grain cells with a word length of 4 or 8 b. This approach combines high flexibility with inherent support for binary arithmetic such as multiplication. This paper presents two medium-grain cells for reconfigurable DSP hardware. Both cells contain an array of small lookup tables, or ldquoelementsrdquo, that can assume two structures. In memory mode, the elements act as a random-access memory. In mathematics mode, the elements implement 4-b arithmetic operations. The first design uses a matrix of 4 times 4 elements and operates in bit-parallel fashion. The second design uses an array of five elements and computes arithmetic functions in bit-serial fashion. Layout simulations in 180-nm CMOS indicate that the parallel cell operates at 267 MHz, whereas the serial cell runs at 167 MHz. However, the parallel design requires over twice the area. The proposed medium-grain cells provide the performance and flexibility needed to implement DSP. To evaluate the designs, the paper estimates the execution time and resource utilization for common benchmarks such as the fast Fourier transform. The architecture model used in this analysis combines the cells with a pipelined hierarchical interconnection network. The end results show great promise compared to other devices, including field-programmable gate arrays.

A 630 MHz, 76 mW Direct Digital Frequency Synthesizer Using Enhanced ROM Compression Technique

The paper presents a detailed description of a direct digital frequency synthesizer (DDFS) based on a Multipartite Table Method (MTM) which is a salient lookup table compression technique. A novel algorithm to find the optimal MTM decomposition which minimizes the ROM size while archiving a target spurious free dynamic range (SFDR) is presented in the paper. The DDFS designed with the proposed technique is ideally suited for a high clock frequency operation, requiring small lookup tables and simple multi-operand adders. Low-power operation is achieved through a power-driven synthesis, by using in the circuit two flip-flop topologies (with different power and delay performances). A test chip has been realized in 0.25 mum, 2.5 V technology. The circuit achieves a 90 dBc SFDR and operates at a maximum clock frequency of 630 MHz, with 76 mW power dissipation. By reducing the power supply at 1.8 V, a maximum operating frequency of 430 MHz was measured, with a total power dissipation as low as 24.9 mW

A new Mixed Radix Conversion algorithm MRC-II

In this paper, we present an efficient and simplified algorithm for the Residue Number System (RNS) conversion to weighted number system which in turn will simplify the implementation of RNS sign detection, magnitude comparison, and overflow detection. The algorithm is based on the Mixed Radix Conversion (MRC). The new algorithm simplifies the hardware implementation and improves the speed of conversion by replacing a number of multiplication operations with small look-up tables. The algorithm requires less ROM size compared to those required by existing algorithms. For a moduli set consisting of eight moduli, the new algorithm requires seven tables to do the conversion with a total table size of 519bits, while Szabo and Tanaka MRC algorithm [N.S. Szabo, R.I. Tanaka, Residue Arithmetic and its Application to Computer Technology, McGraw-Hill, New York, 1967; C.H. Huang, A fully parallel mixed-radix conversion algorithm for residue number applications, IEEE Transactions on Computers c-32 (4) (1983)] requires 28 tables with a total table size of 8960bits; and Huang MRC algorithm (Huang, 1983) requires 36 tables with a total table size of 5760bits.

Spectral Interpolation on 3×3 Stencils for Prediction and Compression

Many scientific, imaging, and geospatial applications produce large high-precision scalar fields sampled on a regular grid. Lossless compression of such data is commonly done using predictive coding, in which weighted combinations of previously coded samples known to both encoder and decoder are used to predict subsequent nearby samples. In hierarchical, incremental, or selective transmission, the spatial pattern of the known neighbors is often irregular and varies from one sample to the next, which precludes prediction based on a single stencil and fixed set of weights. To handle such situations and make the best use of available neighboring samples, we propose a local spectral predictor that offers optimal prediction by tailoring the weights to each configuration of known nearby samples. These weights may be precomputed and stored in a small lookup table. We show through several applications that predictive coding using our spectral predictor improves compression for various sources of high-precision data.

Generic nonsinusoidal phase error correction for three-dimensional shape measurement using a digital video projector

A structured light system using a digital video projector is widely used for 3D shape measurement. However, the nonlinear gamma of the projector causes the projected fringe patterns to be nonsinusoidal, which results in phase error and therefore measurement error. It has been shown that, by using a small look-up table (LUT), this type of phase error can be reduced significantly for a three-step phase-shifting algorithm. We prove that this algorithm is generic for any phase-shifting algorithm. Moreover, we propose a new LUT generation method by analyzing the captured fringe image of a flat board directly. Experiments show that this error compensation algorithm can reduce the phase error to at least 13 times smaller.

Box-minus operation and application in sum–product algorithm

A new expression for box-minus operation, i.e. the inverse of box-plus operation, is derived, with which the box-minus operation can be implemented by a small look-up table. Its application in the sum–product algorithm is investigated.

High Radix BKM Algorithm

In this paper, a high radix implementation of the BKM algorithm is introduced. The BKM algorithm is a shift-and-add CORDIC-like algorithm that performs fast computation of complex exponential and logarithm without any scalling factor. The proposed implementation reduces the number of iterations needed for the calculation. Compared to previous implementations of high radix BKM algorithm, it needs smaller lookup tables.

A low complexity design of psycho-acoustic model for MPEG-2/4 advanced audio coding

The paper presents a new low complexity design of psycho-acoustic model (PAM), which is the key technology for MPEG-2/4 advanced audio coding (AAC) encoding. The real-time constraint of MPEG AAC leads to a heavy computational bottleneck on today's portable devices. To overcome this problem, design analysis and optimization of PAM are addressed at the algorithmic level. First, the dominant calculation of spreading function is replaced with small look-up tables. Second, modified-discrete-cosine-transform-based (MDCT-based) PAM with block type decision in frequency domain is proposed to reduce the overall AAC encoder complexity and maintain the quality. This technique is different from the traditional methods. The computational complexity of PAM is reduced by 82% in total. The proposed design could be implemented in a real-time MPEG-2/4 AAC stereo encoder at low complexity profile and bit rate 128 kb/s with computational complexity of less than 20 MOPS while maintaining CD quality.