Small Gate Voltage Research Articles

Peculiarities of the SCLC Effect in Gate‐All‐Around Silicon Nanowire Field‐Effect Transistor Biosensors

AbstractHigh‐quality liquid gate‐all‐around (LGAA) silicon nanowire (NW) field‐effect transistor (FET) biosensors are fabricated and studied their properties in 1 mm phosphate‐buffered saline solution with pH = 7.4 using transport and noise spectroscopy. At small VDS, the conventional current behavior of FET with a linear dependence on voltage is registered in the output current‐voltage (I‐VM) characteristics with M = 1. At drain‐source voltage VDS > 0.6 V, the I‐V characteristics with stronger power M are revealed. It is shown that the current in LGAA NW FETs follows current proportional to voltage in power M = 4 dependence on small liquid gate voltages. Transport and noise spectroscopy analyses demonstrate that the obtained results are associated with the space‐charge‐limited current (SCLC) effect. Moreover, a strong two‐level random telegraph signal (RTS) is found in the region corresponding to SCLC at VDS values exceeding 0.6 V. The RTS related to single trap phenomena results in a well‐resolved Lorentzian component of noise spectra. The results demonstrate that the SCLC and two‐level RTS phenomenon are correlated effects. They should be taken into account during the development of single‐trap‐based devices, including biosensors.

Atomistic designing of 2D quantum materials heterostructures CdF/CrI3 for Berry curvature driven tunable intrinsic anomalous Hall state

The coupling between topology and magnetism can explore rich physics with fundamental interest. Passing through the phase of Bismuth-based topological insulators magnetized by the 3d/4f transition metal doping, currently the fabrication of quantum heterostructures by suitable new-generation 2D materials, has emerged as a prospective alternative. Following the current trends, the present investigation deals with the atomistic designing and investigation of the quantum heterostructures of the newly predicted massive Dirac semimetal CdF and well-known layered ferromagnetic insulator CrI3 using the first-principles density functional theory calculations supplemented by the low energy tight-binding model Hamiltonian. The designed strategy ensures the lattice mismatch should be within the permissible range. We have addressed the physical characteristics of heterostructures in terms of the non-trivial topological band inversion between Cd-5s and I-2p orbitals. Proximity effect induces magnetic interactions, breaks the time-reversal symmetry at the interface, and leads to Berry curvature-driven tunable intrinsic anomalous Hall conductance (AHC) at the Fermi energy. Our analysis reveals the electrons with high Fermi velocity (106 m s−1) in the heterostructures and the band topology at the Fermi level can be tuned effectively using very small external gate voltage or homogeneous electric field. Our investigation can open up new avenues for designing new topological phases in the heterostructure community and possible tailoring routes of the intrinsic AHC in moderate temperature.

The fundamental 1/f noise in monolayer graphene

A lower bound on the voltage noise power spectrum set by quantum indeterminacy exists in any conducting material. This bound is calculated explicitly for monolayer graphene taking into account graphene pseudospin/valley band structure. It is found to be of the form characteristic of the observed [Formula: see text] noise. It is shown that the deviation of [Formula: see text] from unity is a result of the piezoelectric interaction of charge carriers with acoustic phonons. A comparison with the measured [Formula: see text] noise in graphene and graphene-based heterostructures shows that the observed noise intensity is near the quantum bound. It is demonstrated that the recently observed sharp peak in [Formula: see text] at small gate voltages in the field-effect transistors based on graphene/boron nitride heterostructure is well reproduced by the theory, and is to be attributed to the out-of-plane piezoelectric activity in this heterostructure. A simple kinetic model is proposed to describe the effect of the charge carrier trapping on [Formula: see text].

Ambipolar Nonvolatile Memory Behavior and Reversible Type‐Conversion in MoSe2/MoSe2 Transistors with Modified Stack Interface

Abstract2D semiconductor devices have been studied due to their unique potential in architecture and properties. As one of the unique devices approaches, 2D hetero‐stack channel field‐effect transistors (FETs) have recently been reported, but homo‐stack FETs are rare to find. Here, MoSe2/MoSe2 homo‐stack transistors are rather fabricated for study. Unlike the equivalently‐thick single MoSe2 FET, homo‐stack FETs show n‐type memory behavior that originates from stack interface‐induced traps. Particularly, when their stack interfaces are engineered by surface oxidation of bottom MoSe2, more stable nonvolatile memory behavior turns out. Short‐term ultraviolet ozone (UVO)‐induced oxidation only results in n‐type memory, but 15 min‐long oxidation surprisingly enables both n‐ and p‐type nonvolatile memory behavior due to nm‐thin MoOx embedded between upper and lower MoSe2. Furthermore, by alternating gate voltage pulse to the 15 min‐long UVO‐treated FETs, channel polarity conversion appears reversible in a small gate voltage (VGS) sweep range, which means that the channel type of a transistor can be reversibly modulated via stack interface engineering. It is believed that homo‐stack interface engineering must be one of the approaches to maximize the potential of 2D devices.

Near‐Infrared Reflection Modulation Through Electrical Tuning of Hybrid Graphene Metasurfaces

AbstractGraphene, a 2D material with tunable optical properties, has recently attracted intense interest for reconfigurable metasurfaces. So far, the working wavelength of graphene‐based or hybrid graphene metasurfaces has been limited in the mid‐infrared and terahertz spectra. In this paper, by combining graphene with Au nanostructures, the authors demonstrate a near‐infrared tunable metasurface with decent modulation efficiency, weak dependence on graphene's carrier mobility, and small gate voltages, attributing to the unique interband transition of graphene. The experimental results agree well with numerical simulations. It is also shown that by properly designing the structural parameters of Au nanostructures, the hybrid graphene metasurface can be tunable in both near‐infrared and mid‐infrared regions.

Finding out square root of an integer number using Single Electron Transistor

The single-electron transistor (SET) attracts the researchers, scientists or technologists to design and construct large scale circuits for the sake of the consumption of ultra-low power and its small size. All the incidences in a SET-based circuit happen when only a single electron tunnels through the transistors under the proper applied bias voltage and a small gate voltage or multiple gate voltages. The oscillatory conduction as the function of the variable-multiple /single gate voltage is exhibited by SET. This uncommon characteristic provides the ability of executing the functions of AND, OR, XOR, Inverter and some combinational circuits like multiplexer, subtractor etc. For implementing a square root circuit, SET would be a best candidate to fulfil the requirements. The processing speed of SET based devices will be nearly close to electronic speed. Noise during processing gets ultra-low when the circuits is built with SETs. The square root circuit is presented here for sixteen bit input numbers. The input bit numbers can be increased with the increasing of the depth of the pattern very easily. And this will provide us the greater accuracy about the squared root value. Power consumption in the single electron circuit is low irrespective of bipolar junction transistor (BJT) or Complementary Metal Oxide Semiconductor (CMOS) circuits. Reducing the numbers of nodes, the power consumption is reduced.

Parasitic Capacitance Modeling of Si-Bulk FinFET-Based pMOS

FinFET architecture has witnessed great success at commercial 22-nm node and beyond due to its natural immunity of short-channel effects (SCEs) since the past decade. As the critical size scales down further, the parasitic capacitance becomes a crucial bottleneck to gain the device performance. In this article, analytical parasitic capacitance models (including eight components) are established based on real Si-bulk FinFET pMOS. Compared with the prior works, first, the electric field distribution with a small gate voltage perturbation is employed to reveal the capacitance origin and distribution. Second, except for widely studied parameters (spacer thickness and overlap), the key parameters [source and drain (S/D) recess depth, spacer height, and embedded-SiGe (e-SiGe) cavity overfill] are also studied. The later parameters are seldom considered, but they are widely selected as key in-line monitor items in manufacturing due to their sensitivity to device current and parasitic capacitance. In addition, the geometric dependence on parasitic capacitance is performed and verified well by the 3-D Sentaurus Technology Computer Aided Design (TCAD) simulator. The result shows that the analytical capacitance model can capture geometric behavior well, which finally is understood by the breakdown of the total parasitic capacitance.

A Scheme of Quantum Tunnel Field Effect Transistor Based on Armchair Graphene Nano-Ribbon

We proposed a scheme of armchair graphene nanoribbon (AGNR) based tunnel field-effect transistor (TFET). The simulated device consists of two (AGNR) electrodes with zigzag termination that are separated by a narrow gap. The Fermi level of two electrodes is controlled with a common back gate. The main idea is based on taking advantage of the electronic effects of smooth edge atoms of (AGNR) and investigating the effect of applied small uniaxial tensile strain and gate voltage on the output characteristics of simulated TFET. Our analysis shows that the simulated device will have a pronounced negative differential conductance high peak to valley ratio at room temperature. We see that by applying the uniaxial tensile strain, this ratio upgrades to 70 for (AGNR) with width N = 13.

Measuring of an unknown voltage by using single electron transistor based voltmeter

In engineering and science, high operating speed, low power consumption, and high integration density equipment are financially indispensable. Single electron device (SED) is one such equipment. SEDs are capable of controlling the transport of only one electron through the tunneling transistor. It is single electron that is sufficient to store information in SED. Power consumed in the single electron circuit is very low in comparison with CMOS circuits. The processing speed of single electron transistor (SET) based device will be nearly close to electronic speed. SET attracts the researchers, scientists or technologists to design and implement large scale circuits for the sake of the consumption of ultra-low power and its small size. All the incidences for the case of a SET-based circuit happen when only a single electron tunnels through the transistors under the proper applied bias voltage and a small gate voltage or multiple gate voltages. For implementing a single electron transistor based voltmeter circuit, SET would be the best candidate to fulfil the requirements of it. Ultra-low noise is generated during tunneling SEDs. A D Flip-Flop is implemented and based on this, two kinds of registers like sequence register and сode register are made.

Impacts of HfZrO thickness and anneal temperature on performance of MoS2 negative-capacitance field-effect transistors

The MoS2 negative-capacitance field-effect transistor (NCFET) with the ultra-thin (3 nm) HfZrO (HZO) as NC layer and 2 nm Al2O3 as dielectric layer is successfully fabricated by optimizing the annealing temperature and the HZO thickness. Excellent subthreshold swing (SS = 33.1 mV dec−1) is achieved, with an on/off current ratio of 1.16 × 107. The relevant negative-drain-induced barrier lowing effect and the negative differential resistance effect are observed in the MoS2 NCFET. Such low SS implies that only a small gate-voltage increment can transfer the transistor from off state to on state, i.e. an excellent switching and low power-consumption characteristics. The involved mechanisms lie in a suitable anneal temperature for ferroelectric phase transition and a reasonably ultra-thin HZO thickness for the optimum capacitance matching.

Influence of Fundamental Parameters on the Intrinsic Voltage Gain of Organic Thin Film Transistors

The intrinsic gain is a key metric in analog electronics, it is the highest gain that can be obtained for an amplifier in the transistor configuration. However, there lack the demonstration of the intrinsic gain with different parameters comprehensively, they often focus on one or two features. In this work, we fabricated organic thin film transistors (OTFTs) with two types of semiconducting material to compare the effect of mobility on intrinsic gain and varied structural parameters such as active layer thickness and channel length to explore the impacts of those factors. We found that the intrinsic gain does not have much correlation with the mobility and the contact resistance. In addition, the intrinsic gain decreases as the channel length decreases, the increment of the gate voltage, and the decrease of the thickness of the active layer. The better understanding of different impacts on the intrinsic gain on OTFTs could provide indication for its real application design of organic circuit to obtain higher gain value, which is needed in the future amplifier processing. We fabricated organic thin film transistors (OTFTs) with indacenodithiophene-co-benzothiadiazole (IDTBT) and Poly(N,N′-bis-4-butylphenyl-N,N′-bisphenyl)benzidine (Poly-TPD) in order to investigate influences of fundamental parameters on intrinsic gain. We varied structural parameters such as active layer thickness and channel length on fabrication of devices. The mobility has extracted and compared with fundamental parameters. Even though devices with Poly-TPD showed lower mobility, but it has higher intrinsic gain. While, IDTBT-based devices showed lower intrinsic gain, even though they have much higher mobility than Poly-TPD-based device. As a result, we confirmed that thick active layer, long channel length, and small gate voltage are favorable to obtaining high intrinsic gain in OTFTs. We suggest that OTFT is a suitable configuration for exploration the intrinsic gain.

Investigation of Different Conduction States on the Performance of NMOS-Based Power Clamp ESD Device

This article investigates the effects of different gate coupling voltage and gate voltage duration on electro-static discharge (ESD) performance of several NMOS-based power rail protection devices. Through simulation and transmission line pulse (TLP) test, it is found that there are two modes in the conduction process of the main clamping NMOS: channel conduction state and parasitic NPN conduction state. Different gate voltage and duration bring the two conduction states different proportions in the whole working process, which give the device very different robustness. The results show that under the condition of small gate voltage and long duration and the condition of large gate voltage and short duration, the device can achieve optimal performance because the trigger voltage can be reduced, and the parasitic NPN can be turned on in time to release most of the current.

Ionic liquid gating of single-walled carbon nanotube devices with ultra-short channel length down to 10 nm

Ionic liquids enable efficient gating of materials with nanoscale morphology due to the formation of a nanoscale double layer that can also follow strongly vaulted surfaces. On carbon nanotubes, this can lead to the formation of a cylindrical gate layer, allowing an ideal control of the drain current even at small gate voltages. In this work, we apply ionic liquid gating to chirality-sorted (9, 8) carbon nanotubes bridging metallic electrodes with gap sizes of 20 nm and 10 nm. The single-tube devices exhibit diameter-normalized current densities of up to 2.57 mA/μm, on-off ratios up to 104, and a subthreshold swing down to 100 mV/dec. Measurements after long vacuum storage indicate that the hysteresis of ionic liquid gated devices depends not only on the gate voltage sweep rate and the polarization dynamics but also on charge traps in the vicinity of the carbon nanotube, which, in turn, might act as trap states for the ionic liquid ions. The ambipolar transfer characteristics are compared with calculations based on the Landauer–Büttiker formalism. Qualitative agreement is demonstrated, and the possible reasons for quantitative deviations and possible improvements to the model are discussed. Besides being of fundamental interest, the results have potential relevance for biosensing applications employing high-density device arrays.

Multibit non-volatile memory based on WS2 transistor with engineered gate stack

In this work, a prototype of a charge-trapping memory device based on two-dimensional WS2 has been fabricated with an engineered gate stack for multilevel non-volatile memory application. A Si/SiO2/ITO/Al2O3/Ta2O5/Al2O3 stack has been successfully integrated with optimized layer thicknesses for enhanced gate control over the WS2 channel and memory performance. The memory cells exhibited a sufficient memory window, fast programming and erasing speed, and excellent memory retention and endurance. Moreover, stable and discrete memory states have been achieved at small gate voltages. Such excellent memory characteristics originated from the intrinsic properties of the atomically thin WS2 material and the engineered gate stack with clean and robust interfaces. The better thermal stability, higher permittivity, deeper trap level, and relatively smaller bandgap of the Ta2O5 dielectric than other commonly used dielectrics such as SiO2 and Al2O3 also contribute to the memory reliability, which is very attractive for future information and data storage applications.

Electrical and electrothermal properties of few-layer 2D devices

While two-dimensional (2D) materials have emerged as a new platform for nanoelectronic devices with improved electronic, optical, and thermal properties, and their heightened sensitivity to electrostatic and mechanical interactions with their environment has proved to be a bottleneck. Few-layer (FL) 2D devices retain the desirable thinness of their monolayer cousins while boosting carrier mobility. Here, we employ an electrothermal model to study FL field-effect devices made from transition metal dichalcogenides MoS2 and WSe2 and examine the effect of both electrical and thermal interlayer resistances, as well as the thermal boundary resistance to the substrate, on device performance. We show that overall conductance improves with increasing thickness (number of layers) at small gate voltages, but exhibits a peak for large gate voltages. Joule heating impacts performance due to relatively poor thermal conductance to the substrate and this impact, along with the location of the hot spot in the FL stack, varies with carrier screening length of the material. We conclude that coupled electrothermal simulation can be employed to design FL 2D devices with improved performance.

2D-MoS2/BMN Ceramic Hybrid Structure Flexible TFTs with Tunable Device Properties.

Two-dimensional (2D) layered semiconductor materials have emerged as prospective channel materials in flexible thin-film field effect transistors (TFTs) recently because of their unique electrical and mechanical characteristics. Meanwhile, high-quality ceramics, with outstanding dielectric property and fabrication process compatible with low-cost flexible substrates, have become one of the best candidates of gate dielectric layers in flexible TFTs. In this work, 2D MoS2 and dielectric ceramic Bi2MgNb2O9 (BMN) were utilized to fabricate flexible TFTs on low-cost polyethylene terephthalate substrates. The MoS2/BMN hybrid structure exhibited good quality by Raman, X-ray photoelectron spectroscopy, and atomic force microscopy characterizations. In addition, the flexible MoS2/BMN TFTs indicated good performances with a small gate voltage. More importantly, with the modulation of gate voltage, the flexible TFTs surprisingly exhibited three different device types, that is, multilayer MoS2/BMN n-type TFT (device type 1), homojunction MoS2/BMN TFT (device type 2), and thick MoS2/BMN p-type TFT (device type 3). In particular, with different bias conditions, the homojunction TFT showed bipolarity of transfer characteristics and forward/backward rectifications of output characteristics similar to p-n/n-n junctions. The high dielectric constant and high quality of the BMN ceramic layer enabled the gate to effectively modulate these different structures of MoS2 channels. The operation mechanisms of these three types of flexible TFTs were investigated. Additionally, the flexible MoS2/BMN TFTs showed good flexibility and performance stability with external strains. The results prove the great potential of integration of 2D materials, high-quality dielectric ceramics, and low-cost plastic substrates for high-performance flexible TFTs and further applications of flexible electronics.

Graphene field effect transistors using TiO2 as the dielectric layer

In this work, we report the electron mobility and electron density of three graphene field effect transistors using a 280 nm titanium dioxide dielectric layer and a graphene channel of area 300 × 300 μm2. We achieve electron mobilities up to 1877 cm2/V and the Dirac point appears in small gate voltages, as compared to similar SiO2 transistors. Also, we obtain the TiO2 surface roughness through profilometry and confirm that electron mobility is inversely proportional to the channel's surface roughness.

Solution-processed ITO thin-film transistors with doping of gallium oxide show high on-off ratios and work at 1 mV drain voltage

Indium tin oxide (ITO) is generally used as an electrode material but has recently been demonstrated to be a competitive candidate for use in semiconductor layers in high-performance thin-film transistors (TFTs), due to its high mobility and strong resistance to wet-etching. Here, we demonstrate TFTs using solution-processed, ultra-thin ITO films with outstanding switching performance. These devices exhibit a mobility of up to 15 cm2 V−1 s−1 and a high on-off ratio of 108. Because the device exhibits significant instability under stress tests, moderate doping with Ga as a dopant is introduced to form Ga-doped ITO TFTs. The resulting device has much enhanced stability, near-zero turn-on voltage, and a high on-off current ratio of 108. Through further involvement of an AlOx dielectric layer, the Ga-doped ITO TFTs exhibit a high apparent mobility of more than 40 cm2 V−1 s−1 and operate at small gate voltages (3 V). Remarkably, the device maintains an on-off ratio of over 104 at drain voltages as small as 1 mV.

Highly sensitive ultraviolet photodetectors based on single wall carbon nanotube-graphene hybrid films

An ultraviolet (UV) photodetector was fabricated by depositing single wall carbon nanotubes (SWCNTs) on the surface of a graphene field-effect transistor (GFET) with buried gate electrode structure. A photoresponsivity with a value as high as 204.5 A/W was obtained under a 365-nm LED light illumination with an incident power of 3.9 μW. The photoresponsivity of our photodetector is about four orders higher in magnitude than that of a recently reported UV photodetector, which is based on CNTs/graphene hybrid films with a photoresponsivity of 2.3 × 10−2 A/W. With increasing the source-drain voltage of the SWCNTs modified GFET, the photoresponsivity can be further enhanced. In addition, the photoresponsivity can also be tuned by applying a small gate voltage. This work provides a simple and feasible method to create highly sensitive UV photodetectors based on all-carbon hybrid films, which are important in many applications such as military surveillance, biomedical instrumentation and environmental monitoring.

Exceptional mechano-electronic properties in the HfN2 monolayer: a promising candidate in low-power flexible electronics, memory devices and photocatalysis.

The response of the electronic properties of the HfN2 monolayer to external perturbation, such as strain and electric fields, has been extensively investigated using density functional theory calculations for its device-based applications and photocatalysis. The HfN2 monolayer is found to be a semiconductor showing a direct band gap of 1.44 eV, which is widely tunable by 0.9 eV via application of biaxial strain. Furthermore, the tunability in the band edges of the HfN2 monolayer straddling the water redox potential under a biaxial strain of ±10% makes it suitable for solar energy harvesting via photocatalytic applications over a wide range (0-7) of pH. The band gap can be decreased by 29.8% under a biaxial tensile strain of 10%. Upon incorporation of spin orbit coupling (SOC) a large spin splitting at the conduction band (Δc ∼ 314 meV) and a small splitting at the valence band (Δv ∼ 32 meV) are noted, which is attributable to the orbital composition of the band edges. The spin splitting in the band edges is found to be adjustable via biaxial compressive strain. The strain dependent mechanical properties and stability reveal the ability of the HfN2 monolayer to withstand a large magnitude of strain of up to ±10%, thereby bringing about a giant tunability in its Young modulus (Y) from 66 N m-1 to 283 N m-1, which is gainfully exploitable in flexible electronics. The tunability in Y over such a wide range has not been observed in other 2D materials. Moreover, the HfN2 monolayer undergoes a transition from a semiconducting to a metallic state under the application of a normal electric field or gate voltage of 0.48 V Å-1, which may potentially serve as the OFF (semiconducting) and ON (metallic) state in devices. Interestingly, an electric field of such intensity has been realized experimentally using pulsed ac field technology. Such a small gate voltage will greatly lower its power consumption. The electronic origin of this transition from the OFF to the ON state is found to arise from unoccupied NFEG (Nearly Free Electron Gas) states. A HfN2 monolayer based tunnel field effect transistor (t-FET) is proposed herewith as a model device for low-power digital data storage, thereby paving new avenues in flexible electronics and memory devices.