Impacts of HfZrO thickness and anneal temperature on performance of MoS2 negative-capacitance field-effect transistors

Abstract

The MoS2 negative-capacitance field-effect transistor (NCFET) with the ultra-thin (3 nm) HfZrO (HZO) as NC layer and 2 nm Al2O3 as dielectric layer is successfully fabricated by optimizing the annealing temperature and the HZO thickness. Excellent subthreshold swing (SS = 33.1 mV dec−1) is achieved, with an on/off current ratio of 1.16 × 107. The relevant negative-drain-induced barrier lowing effect and the negative differential resistance effect are observed in the MoS2 NCFET. Such low SS implies that only a small gate-voltage increment can transfer the transistor from off state to on state, i.e. an excellent switching and low power-consumption characteristics. The involved mechanisms lie in a suitable anneal temperature for ferroelectric phase transition and a reasonably ultra-thin HZO thickness for the optimum capacitance matching.