Small Fan-in Research Articles

Localizability of the approximation method

We use the approximation method of Razborov to analyze the locality barrier which arose from the investigation of the hardness magnification approach to complexity lower bounds. Adapting a limitation of the approximation method obtained by Razborov, we show that in many cases it is not possible to combine the approximation method with typical (localizable) hardness magnification theorems to derive strong circuit lower bounds. In particular, one cannot use the approximation method to derive an extremely strong constant-depth circuit lower bound and then magnify it to an NC1\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ extsf{NC}^{1}$$\\end{document} lower bound for an explicit function. To prove this, we show that lower bounds obtained by the approximation method are in many cases localizable in the sense that they imply lower bounds for circuits which are allowed to use arbitrarily powerful oracles with small fan-in.

Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells

Vertical tunnel field-effect transistors (VTFETs) have been extensively explored to overcome the scaling limits and to improve on-current ( I ON ) compared to standard lateral device structures for the future technologies. The benefits in terms of reduced footprint, high I ON and feasibility of fabrication have been demonstrated in several works. Among various VTFETs, the asymmetric heterojunction vertical tunnel FETs (HVTFETs) have emerged as one of the promising alternatives to standard transistors for low-voltage applications. However, while such device-level benefits without parasitics have been widely investigated, logic-gate design with parasitics and layout implications are not clear. In this article, we investigate and compare the layouts and parasitic capacitances and resistances of HVTFETs with FinFETs. Due to the vertical device structure of HVTFETs, a smaller footprint is observed compared to FinFETs in cells with small fan-in. However, for high fan-in cells, HVTFETs exhibit area overheads due to infeasibility of contact sharing in parallel and series transistors. These area overheads also lead to approximately 48% higher parasitic capacitance and resistance compared to FinFETs when the number of parallel and series connections increases. Further, in order to analyze the impact of parasitics, we modeled the analytical parasitics in SPICE. The models for both HVTFETs and FinFETs with parasitics were used to simulate a 15-stage inverter-based ring oscillator (RO) in order to compare the delay and energy. Our simulation results clearly show that HVTFETs exhibit less delay at a V DD < 0.45 V and higher energy efficiency for V DDs in the range of 0.3V--0.7V, albeit at the cost of 8% performance degradation.

Decomposition of threshold functions into bounded fan-in threshold functions

This paper obtains explicit decomposition of threshold functions into bounded fan-in threshold functions. A small fan-in is important to satisfy technology constraints for large scale integration. By employing the concept of error in the threshold function, we are able to decompose functions in LTˆ1 into a network of size O(nc/M2) and depth O(log2n/logM) where n is the number of inputs of the function and M is the fan-in bound. The proposed construction enables one to trade-off the size and depth of the decomposition with the fan-in bound. Combined with the work on small weight threshold functions, this implies polynomial size, log2 depth bounded fan-in decompositions for arbitrary threshold functions in LTd. These results compare favorably with the classical decomposition which has a size O(2n−M) and depth O(n−M).We also show that the decomposition size and depth can be significantly reduced by exploiting the relationships between the input weights. As examples of this strategy, we demonstrate an O(n2/M) size decomposition of the majority function and, O(n/M) size decompositions of an error tolerant pattern matching function and the comparison function. In all these examples, except for the first level, all other levels use only majority functions.

The Size of the Largest Strongly Connected Component of a Random Digraph with a Given Degree Sequence

We give results on the strong connectivity for spaces of sparse random digraphs specified by degree sequence. A full characterization is provided, in probability, of the fan-in and fan-out of all vertices including the number of vertices with small () fan-in or fan-out. We also give the size of the giant strongly connected component, if any, and the structure of the bow-tie digraph induced by the vertices with large fan-in or fan-out. Our results follow a direct analogy of the extinction probabilities of classical branching processes.

Deeper Sparsely Nets can be Optimal

The starting points of this paper are two size-optimal solutions: (i) one for implementing arbitrary Boolean functions [1]; and (ii) another one for implementing certain sub-classes of Boolean functions [2]. Because VLSI implementations do not cope well with highly interconnected nets – the area of a chip grows with the cube of the fan-in [3] – this paper will analyse the influence of limited fan-in on the size optimality for the two solutions mentioned. First, we will extend a result from Horne & Hush [1] valid for fan-ins D = 2 to arbitrary fan-in. Second, we will prove that size-optimal solutions are obtained for small constant fan-in for both constructions, while relative minimum size solutions can be obtained for fan-ins strictly lower than linear. These results are in agreement with similar ones proving that for small constant fan-ins (D = 6 ... 9), there exist VLSI-optimal (i.e., minimising AT2) solutions [4], while there are similar small constants relating to our capacity of processing information [5].

On the correlation of symmetric functions

Thecorrelation between two Boolean functions ofn inputs is defined as the number of times the functions agree minus the number of times they disagree, all divided by 2 n . In this paper we compute, in closed form, the correlation between any twosymmetric Boolean functions. As a consequence of our main result, we get that every symmetric Boolean function having an odd period has anexponentially small correlation (inn) with the parity function. This improves a result of Smolensky [12] restricted to symmetric Boolean functions: the correlation between parity and any circuit consisting of a Mod q gate over AND gates of small fan-in, whereq is odd and the function computed by the sum of the AND gates is symmetric, is bounded by 2−Ω(n).

A note on the complexity of reliability in neural networks

It is shown that in a standard discrete neural network model with small fan-in, tolerance to random malicious faults can be achieved with a log-linear increase in the number of neurons and a constant factor increase in parallel time, provided fan-in can increase arbitrarily. A similar result is obtained for a nonstandard but closely related model with no restriction on fan-in.

A symmetric CMOS NOR gate for high-speed applications

A novel CMOS n-input NOR gate is proposed, having n parallel NMOS pull-downs to V/sub ss/ and n parallel PMOS pull-ups to V/sub cc/. The structure, which consumes DC power, is approximately twice as fast as a conventional full-CMOS NOR gate, and is slightly faster than a CMOS inverter. For gates with small fan-in (n<or=3), the proposed circuit is also faster than the grounded-PMOS NOR gate when operated at equal DC power levels.<<ETX>>

Digital optical computing with one-rule cellular automata

Symbolic substitution is a parallel technique for applying pattern transformation rules to an array of ON/OFF cells. A single pattern transformation rule that requires a small fan-in and fan-out is shown to be sufficient for all computing. A simple optical architecture that makes use of optically nonlinear arrays and spaceinvariant imaging can implement the rule. Configurations of cells are arranged to realize dual-rail logic operators and connection primitives. Circuits are created by customizing a fixed 2-D mask to image light onto selected cells of the array. The presented techniques are intended to provide a foundation for work on digital optical computers.