Small Contact Resistance Research Articles

Combined Microstructural and Electrical Characterization of Metallization Layers in Industrial Solar Cells

Abstract Screen printed front side contacts of textured, mono-crystalline p-type silicon solar cells with n-type emitters were investigated. The different pastes (FSP1 and 2) and the different crystallographic orientations of the Si surfaces studied strongly affected the contact resistance. The microstructure of the contacts was analyzed in plan-view and cross-section by combined scanning and analytical transmission electron microscopy. A controlled grinding process rather than a chemical etching process was applied for the plan-view sample preparation. For textured cells processed with different pastes, pronounced differences were seen in the contact resistances (FSP1: efficiency 16.9% and contact resistance 20 mΩ cm 2 , FSP2: 17.8% and 2 ). A discontinuous glass layer was found for FSP1 but a continuous glass layer was found for FSP2, yielding a smaller contact resistance. Glass layers contained (Si 2 Pb)O x as a main constituent but different mole fractions of Zn, Ti, P, and B as minor constituents, varying for the different pastes. Glass layers were up to 500 nm thick and revealed inhomogeneously distributed spherical Ag colloids 5-200 nm in size. Planar cells were also studied and served as model systems: planar 〈111〉 oriented Si surfaces yielded specifically lower contact resistance as compared to planar 〈100〉 orientation. Pyramidal Ag crystallites were only observed for 〈100〉 oriented Si surfaces not for 〈111〉 surfaces. Therefore, it is concluded that pyramidal Ag crystallites are not necessary for contacts yielding low contact resistance. Instead, lens shaped Ag precipitates together with a high density of Ag colloids in the glass layer yield low contact resistance, as found for oriented Si surfaces. A percolative current path including charge transport via Ag colloids in the glass layer is proposed. For textured cells, in accordance with these results, pyramidal Ag crystallites were only observed at step edges of {111} faces or at the edges of the Si pyramids.

Low operation voltage of GaN-based LEDs with Al-doped ZnO upper contact directly on p-type GaN without insert layer

Al-doped ZnO (AZO) film was evaporated on double-side polished sapphire, p-GaN layers, n+-InGaN–GaN short-period superlattice (SPS) structures, and GaN-based light-emitting diodes (LEDs) by e-beam. The AZO film on the p-GaN layer after thermal annealing exhibited an extremely high transparency (98% at 450nm) and a small specific contact resistance of 2.19×10−2Ωcm2, which was almost the same as that of as-deposited AZO on n+-SPS structure. With 20mA injection current, the forward voltages were 3.30 and 3.27V, whereas the output powers were 4.32 and 4.07mW for the LED with AZO on insert n+-SPS upper contact and the LED with AZO on p-GaN upper contact (without insert layer), respectively. The small specific contact resistance and low operation voltage of LED with AZO on p-GaN upper contact was achieved by rapid thermal annealing (RTA) process.

Study on contact resistance in single-contact and multi-contact MEMS switches

In this paper, contact resistance in single-contact and multi-contact switches, fabricated using MEMSCAP’s Metal Multi-User MEMS Process (MetalMUMPs), is characterized, compared, and discussed. The experimental results show that the single-contact switch has a lower contact on-resistance compared to the multi-contact switch. Also, under high carrying current operation of 0.85A, the contact resistances are 0.426 and 0.155Ω in the multi-contact switch and the single-contact switch, respectively. The contact pressure is here proved to be the key factor in determining the contact resistance. A smaller nominal contact area can introduce more contact pressure under the same contact force, and therefore a great fraction of surface is actually contacted. Smaller contact resistance can thus be achieved.

Contacting Moderately Doped Phosphorous Emitters of Silicon Solar Cells With Dopant Segregation During Nickel Silicidation

Emitter performance is crucial for the efficiency of solar cells. A further increase of efficiency requires reducing recombination losses while keeping parasitic resistances and shadowing at a minimum. In silicon solar cells, recombination can be lowered by decreasing the emitter doping concentration; however, this comes at the cost of increasing contact and sheet resistances. Dopant segregation during nickel silicidation resolves this tradeoff since it allows ohmic contact formation to emitters with almost arbitrary doping profile and concentration. Here, we elaborate on using dopant segregation during silicidation and demonstrate contact formation, as well as a substantial performance improvement of silicon solar cells exhibiting a lowly doped emitter with a peak doping concentration of 6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">18</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> . Furthermore, we show that the small achievable contact resistances in principle allow a strong reduction of the contact area. In turn, this enables lowering the shadowing while, at the same time, decreasing the sheet resistance due to a larger number of front contacts that can be placed close to each other. Using PC1D simulations, we study the solar cell performance as a function of the emitter dopant concentration estimating the achievable efficiency increase when employing dopant segregation.

What Does Annealing Do to Metal–Graphene Contacts?

Annealing is a postprocessing treatment commonly used to improve metal-graphene contacts with the assumption that resist residues sandwiched at the metal-graphene contacts are removed during annealing. Here, we examine this assumption by undertaking a systematic study to understand mechanisms that lead to the contact enhancement brought about by annealing. Using a soft shadow-mask, we fabricated residue-free metal-graphene contacts with the same dimensions as lithographically defined metal-graphene contacts on the same graphene flake. Both cases show comparable contact enhancement for nickel-graphene contacts after annealing treatment signifying that removal of resist residues is not the main factor for contact enhancement. It is found instead that carbon dissolves from graphene into the metal at chemisorbed Ni- and Co-graphene interfaces and leads to many end-contacts being formed between the metal and the dangling carbon bonds in the graphene, which contributes to much smaller contact resistance.

Vibration interference analysis and verification of micro-fluidic inertial switch

The micro-fluidic inertial switch based on liquid metal utilizes the moving mercury droplet to close the switch under the action of acceleration, which is characterized by no moving parts, small contact resistance, long service life and large current. In addition to the requirement of response time, accuracy and reliability, the micro-fluidic inertial switch needs to overcome the impact of the ambient vibration. The influence of the ambient vibration on the performance of switch is investigated by loading pulse or sinusoidal interference signals in the X, Y and Z direction. The numerical results suggest that the performance of micro-fluidic inertial switch is greatly affected by impact interference signal in X sensitive direction as compared with low frequency harmonic signal. If the impact signal with high amplitude lasts only for a short time, the wrong operation might also occur. The interference signals in insensitive direction have a relatively small impact on the performance of switch, and the impact of interference signal can be reduced by reasonable structural design. Finally, anodic bonding, deep reactive ion etching (DRIE) and sputtering technique are adopted to fabricate the micro-fluidic inertial switch. The acceleration threshold of the prototype is tested. The experiment results agree with the numerical results, which indicate that the simulation method is valid.

A Test Structure to Characterize Nano-Scale Ohmic Contacts in III-V MOSFETs

We propose and demonstrate a novel test structure to characterize the electrical properties of nano-scale metal-semiconductor contacts. The structure is in essence a two-port transmission line model (TLM) with contacts in the nanometer regime. Unlike the conventional TLM, two types of Kelvin measurements are possible. When performed on devices with different contact spacing, this allows the extraction of the contact resistance, the semiconductor sheet resistance, and the metal sheet resistance. For this, a 2-D distributed resistive network model has been developed. We demonstrate this technique in Mo/n+-InGaAs contacts with contact lengths from 19 to 450 nm where we have measured an average contact resistivity of 0.69±0.3 Ω·μm2. For relatively long contacts , this corresponds to an extremely small contact resistance of 6.6±1.6 Ω·μm.

Charge Injection in Regioregular Poly-(3-Hexythiophene) Organic Field-Effect Transistors with Different Metal Electrodes

Here we report on regioregular poly-(3-hexythiophene) (P3HT) organic field-effect transistors (OFETs) with various metal electrodes: pristine Au, pristine Cr, and Cr/Au. Compared to the performance of OFETs using different electrodes, the OFETs with Au electrode have better mobility (μ = 0.0090 cm2/Vs) and larger current at the same source-drain voltage and gate voltage. The enhancement of the device performance with Au electrode can be attributed to a small contact resistance and a small barrier height to P3HT for hole carrier injection.

High-mobility organic thin-film transistors based on a small-molecule semiconductor deposited in vacuum and by solution shearing

The small-molecule organic semiconductor 2,9-di-decyl-dinaphtho-[2,3-b:2′,3′-f]-thieno-[3,2-b]-thiophene (C10-DNTT) was used to fabricate bottom-gate, top-contact thin-film transistors (TFTs) in which the semiconductor layer was prepared either by vacuum deposition or by solution shearing. The maximum effective charge-carrier mobility of TFTs with vacuum-deposited C10-DNTT is 8.5cm2/Vs for a nominal semiconductor thickness of 10nm and a substrate temperature during the semiconductor deposition of 80°C. Scanning electron microscopy analysis reveals the growth of small, isolated islands that begin to coalesce into a flat conducting layer when the nominal thickness exceeds 4nm. The morphology of the vacuum-deposited semiconductor layers is dominated by tall lamellae that are formed during the deposition, except at very high substrate temperatures. Atomic force microscopy and X-ray diffraction measurements indicate that the C10-DNTT molecules stand approximately upright with respect to the substrate surface, both in the flat conducting layer near the surface and within the lamellae. Using the transmission line method on TFTs with channel lengths ranging from 10 to 100μm, a relatively small contact resistance of 0.33kΩcm was determined. TFTs with the C10-DNTT layer prepared by solution shearing exhibit a pronounced anisotropy of the electrical performance: TFTs with the channel oriented parallel to the shearing direction have an average carrier mobility of (2.8±0.3)cm2/Vs, while TFTs with the channel oriented perpendicular to the shearing direction have a somewhat smaller average mobility of (1.3±0.1)cm2/Vs.

A monodispersed nano-hexahedral LiFePO4 with improved power capability by carbon-coatings

Abstract A monodispersed nano-sized hexahedral LiFePO4 of regular angularity was prepared through hydrothermal process. Different carbon precursors were employed to create carbon-coating layers onto the nano-particles to improve the electrochemical performances of the material. Structure and morphology of the LiFePO4 material without and with carbon-coating layer were studied using a combination of X-ray diffraction, scanning electron microscopy, transmission electron microscopy, and Raman spectroscopy. It confirms that carbon-coating plays an important role inhibiting the agglomeration of the nanoparticles. A uniform carbon-coating layer of higher graphitization degree was developed on the LiFePO4 particles with sucrose precursor. The electrode exhibits discharge capacities of 148.3 mA h g−1, 138.7 mA h g−1, 117.8 mA h g−1 at 0.1 C, 1 C and 10 C, respectively. Very close Li ion diffusion coefficient of around 8 × 10−14 cm2 s−1 for all the LiFePO4/C composites with different carbon sources implies that the improved power capability is mainly attributed to the small particle size and low contact resistance between the LiFePO4 nanoparticles.

Feasible homopolar dynamo with sliding liquid-metal contacts

We present a feasible homopolar dynamo design consisting of a flat, multi-arm spiral coil, which is placed above a fast-spinning metal ring and connected to the latter by sliding liquid-metal electrical contacts. Using a simple, analytically solvable axisymmetric model, we determine the optimal design of such a setup. For small contact resistance, the lowest magnetic Reynolds number, Rm~34.6, at which the dynamo can work, is attained at the optimal ratio of the outer and inner radii of the rings Ri/Ro~0.36 and the spiral pitch angle 54.7 degrees. In a setup of two copper rings with the thickness of 3 cm, Ri=10 cm and Ro=30 cm, self-excitation of the magnetic field is expected at a critical rotation frequency around 10 Hz.

Role of Metal Contacts in Designing High-Performance Monolayer n-Type WSe2 Field Effect Transistors

This work presents a systematic study toward the design and first demonstration of high-performance n-type monolayer tungsten diselenide (WSe2) field effect transistors (FET) by selecting the contact metal based on understanding the physics of contact between metal and monolayer WSe2. Device measurements supported by ab initio density functional theory (DFT) calculations indicate that the d-orbitals of the contact metal play a key role in forming low resistance ohmic contacts with monolayer WSe2. On the basis of this understanding, indium (In) leads to small ohmic contact resistance with WSe2 and consequently, back-gated In-WSe2 FETs attained a record ON-current of 210 μA/μm, which is the highest value achieved in any monolayer transition-metal dichalcogenide- (TMD) based FET to date. An electron mobility of 142 cm(2)/V·s (with an ON/OFF current ratio exceeding 10(6)) is also achieved with In-WSe2 FETs at room temperature. This is the highest electron mobility reported for any back gated monolayer TMD material till date. The performance of n-type monolayer WSe2 FET was further improved by Al2O3 deposition on top of WSe2 to suppress the Coulomb scattering. Under the high-κ dielectric environment, electron mobility of Ag-WSe2 FET reached ~202 cm(2)/V·s with an ON/OFF ratio of over 10(6) and a high ON-current of 205 μA/μm. In tandem with a recent report of p-type monolayer WSe2 FET ( Fang , H . et al. Nano Lett. 2012 , 12 , ( 7 ), 3788 - 3792 ), this demonstration of a high-performance n-type monolayer WSe2 FET corroborates the superb potential of WSe2 for complementary digital logic applications.

Controlled Fabrication of Core–Shell TiO2/C and TiC/C Nanofibers on Ti Foils and Their Field-Emission Properties

Core-shell TiO(2)/C and TiC/C nanofibers are fabricated in situ on Ti and Al ion-implanted Ti substrates by a thermochemical reaction in acetone and the growth mechanism is described. Implantation of Al into Ti leads to in situ growth of TiC/C in lieu of TiO(2)/C nanofibers. This is because Al has a higher affinity to oxygen than Ti and Ti reacts preferentially with C to form TiC. The Ti foil serves as both the Ti source and substrate for the core-shell TiO(2)/C and TiC/C NFs to ensure strong bonding and small contact resistance between the Ti substrate and the core-shell field emitters. The core-shell TiC/C and TiO(2)/C nanofibers have similar morphology and structure, but the TiC/C nanofibers possess better field emission properties with a turn on field (E(to)) of 2.2 V/μm compared to an E(to) of 3.2 V/μm measured from the TiO(2)/C nanofibers. The enhanced field-emission property of the TiC/C nanofibers is attributed to the high electrical and thermal conductivity of the TiC inner core, which provides a more effective electron transfer pathway between the cathode and C shell emitters.

Suppression of bias stress-induced degradation of pentacene-TFT using MoO x interlayer

The bias stress effect in pentacene thin-film transistors (TFTs) with and without MoO x interlayer was characterized. The device without MoO x interlayer showed a large threshold voltage shift of 5.1 V after stressing with a constant gate-source voltage of −40 V for 10000 s, while at the same condition, the device with MoO x interlayer showed a low threshold voltage shift of 1.9 V. The results can be attributed to the stable interface between MoO x/pentacene and small contact resistance change for the device with MoO x/Cu electrode. Pentacene-TFTs with MoO x interlayer showed a high field-effect mobility of 0.61 cm 2/V s and excellent bias stability, which could be a significant step toward the commercialization of OTFT technology.

Facile fabrication of all-SWNT field-effect transistors

Field-effect transistors (FETs) have been fabricated using as-grown single-walled carbon nanotubes (SWNTs) for the channel as well as both source and drain electrodes. The underlying Si substrate was employed as the back-gate electrode. Fabrication consisted of patterned catalyst deposition by surface modification followed by dip-coating and synthesis of SWNTs by alcohol chemical vapor deposition (CVD). The electrodes and channel were grown simultaneously in one CVD process. The resulting FETs exhibited excellent performance, with an ION/IOFF ratio of 106 and a maximum ON-state current (ION) exceeding 13 μA. The large ION is attributed to SWNT bundles connecting the SWNT channel with the SWNT electrodes. Bundling creates a large contact area, which results in a small contact resistance despite the presence of Schottky barriers at metallic-semiconducting interfaces. The approach described here demonstrates a significant step toward the realization of metal-free electronics. Open image in new window

High speeds complementary integrated circuits fabricated with all‐printed polymeric semiconductors

AbstractInkjet‐printed high speed polymeric complementary circuits are fabricated using an n‐type ([poly{[N,N′‐bis(2‐octyldodecyl)‐naphthalene‐1,4,5,8‐bis(dicarboximide)‐2,6‐diyl]‐alt‐5,5′‐(2,2′‐dithiophene)} [P(NDI2OD‐T2), Polyera ActivInk N2200] and two p‐type polymers [poly(3‐hexylthiophene) (P3HT) and a dithiophene‐based polymer (Polyera ActivInk P2100)]. The top‐gate/bottom‐contact (TG/BC) organic field‐effect transistors (OFETs) exhibit well‐balanced and very‐high hole and electron mobilities (μFET) of 0.2–0.5 cm2/Vs, which were enabled by optimization of the inkjet‐printed active features, small contact resistance both of electron and hole injections, and effective control over gate dielectrics and its orthogonal solvent effect (selection of poly(methyl methacrylate) and 2‐ethoxyethanol). Our first demonstrated inkjet‐printed polymeric complementary devices have been integrated to high‐performance complementary inverters (gain &gt;30) and ring oscillators (oscillation frequency ∼50 kHz). We believe that the operating frequency of printable organic circuits can be further improved more than 10 MHz by fine‐tuning of the device architecture and optimization of the p‐ and n‐channel semiconductor processing. © 2010 Wiley Periodicals, Inc. J Polym Sci Part B: Polym Phys, 2010

Binder-free porous core–shell structured Ni/NiO configuration for application of high performance lithium ion batteries

An interwoven core–shell structured Ni/NiO anode for lithium ion batteries was created by a simple oxidation of Ni foam. As-prepared configuration has a high specific discharge capacity of 701 mAh g − 1 at the 2nd cycle. Its electrochemical performance at subsequent cycles shows good energy capacity of 646 mAh g − 1 at the 65th cycle as well as good rate capability. The porous core–shell structure not only buffers the volume change during cycling but also effectively increases the contact among anode, current collector and electrolyte. The small contact resistance between NiO and Ni facilitates enhanced intrinsic kinetics from conversion reaction.

Optimized Process of Thermal Treatment of Au/CdZnTe Contacts

Abstract Effects of thermal treatment temperatures from 323 K to 473 K in air atmosphere on the Au/CdZnTe contacts fabricated by thermal vacuum evaporation was investigated systematically. The results show that the optimized performances of the Au/CdZnTe contacts after thermal treatment in air at a range of 353-373 K can be obtained, that is, the contacts possess lower barrier height, smaller contact resistance and better ohmic coefficient, without damaging bulk CdZnTe properties. Nevertheless, performing thermal treatment over 400 K, the deposited surface of Au electrodes will grow worse apparently, and the leakage current of CdZnTe samples enhances significantly. This might be attributed to the increase of the Cd vacancies produced by Cd sublimation from the CdZnTe into air atmosphere with the increase of temperature.

Low-voltage InGaZnO thin-film transistors with Al2O3 gate insulator grown by atomic layer deposition

We report on low-voltage, high-performance amorphous indium gallium zinc oxide n-channel thin-film transistors fabricated using 100-nm-thick Al2O3 grown by atomic layer deposition as the gate dielectric layer. The Al2O3 gate dielectric shows very small current densities and has a capacitance density of 81±1 nF/cm2. Due to a very small contact resistance, transistors with channel lengths ranging from 100 μm down to 5 μm yield a channel-independent, field-effect mobility of 8±1 cm2/V s, subthreshold slopes of 0.1±0.01 V/decade, low threshold voltages of 0.4±0.1 V, and high on-off current ratios up to 6×107 (W/L=400/5 μm) at 5 V.

High-performance InGaZnO thin-film transistors with high-k amorphous Ba0.5Sr0.5TiO3 gate insulator

We report on high-performance n-channel thin-film transistors (TFTs) fabricated using amorphous indium gallium zinc oxide (a-IGZO) and amorphous Ba0.5Sr0.5TiO3 (a-BST) as the channel and gate dielectric layers, respectively. a-BST∕a-IGZO TFTs achieve low-voltage operation with a high saturation mobility value of 10±1cm2∕Vs, excellent subthreshold slopes of 0.06±0.01V/decade, a low threshold voltage of 0.5±0.1V, and a high on-off current ratio up to 8×107 (W∕L=1000μm∕5μm) at 3V. The high capacitance density of a-BST (145±2nF∕cm2) and the small contact resistance, smaller than the channel resistance, are responsible for the high performance of these TFTs.