Small Circuit Size Research Articles

Design of New Quad-Channel Diplexer With Compact Circuit Size

New compact quad-channel diplexer (1.5/2 GHz and 2.4/3.5 GHz) using the coupled stepped impedance resonators (SIRs) is proposed. The quad-channel diplexer is composed of two pairs of coupled SIRs with impedance ratio $({\rm K} > 1)$ and the source-load coupling lines. By tuning the impedance ratio and length ratio $(\alpha)$ of SIRs, the resonant modes can be easily determined so as to implement a two-order bandpass filter with very close dual-passbands. The source-load coupling lines are designed to correspond to the quarter-wavelength at the center frequency of first passband for each output port. The proposed quad-channel diplexer is showing a simple configuration, an effective design method and a small circuit size.

A COMPACT MICROSTRIP QUADRUPLEXER USING SLOTLINE STEPPED IMPEDANCE STUB LOADED RESONATORS

In this paper, a novel compact quadruplexer is imple- mented by using slotline stepped impedance stub loaded resonators (SISLRs) in ground plane. Four folded dual-mode slotline SISLRs with one input and four output coupled line structures are designed at difier- ent frequencies for the quadruplexer operation. By properly adjusting the geometrical parameters of a single dual-mode slotline SISLR, its flrst two resonant frequencies can be controlled, and thus it can be uti- lized to implement a second-order bandpass fllter when these resonant frequencies are suitably assigned. Furthermore, because the proposed quadruplexer utilizes the distributed coupling technique, a small circuit size can be obtained. As a result, the proposed quadruplexer occupies an extremely small area, i.e., 0:22‚0£0:25‚0 (0:36‚g£0:41‚g). Finally, good agreement between measurement and EM simulation verifles the design method successfully.

Application of Zero-Vector Control to Three-Phase Inverter

In this paper, a new application of three-phase inverter using zero-vector control is proposed. In order to control the amplitude of output current, the d-q axis coordinate transformation, hysteresis controller and space vector strategy are adopted. Besides, the frequency of output current also can be adjusted by zero-vector control. Therefore, the proposed inverter has lower switching loss, higher system efficiency and better dynamic response. Use VisSim simulation software and TI TMS320F28335 chip to implement the proposed control strategy. The controller has several advantages such as easier to control, smaller circuit size and fully digital design etc. Finally, the experimental results are compared with the proposed theory for verifications.

Single-Magnetic Cell-to-Cell Charge Equalization Converter With Reduced Number of Transformer Windings

In this paper, a new cell-to-cell charge equalization converter using a multiwinding transformer is proposed. The proposed scheme achieves the direct cell-to-cell charge transportation by buck-boost and flyback operation. In this operation, the adjacent two cells share either a current path or a tap of multiwinding transformer. Therefore, the number of windings ia cut in half in comparison to the number of batteries, resulting in a small circuit size. To verify the operation of the proposed charge equalization converter, an experiment with a lithium-ion battery stack is performed.

A 5.9 GHz Low Power and Wide Tuning Range CMOS Current-controlled Ring Oscillator

Designing low power, low noise, wide tuning range and small size circuit in one single chip is very challenging. This paper describe a low power, wide tuning range three-stage current-controlled ring oscillator (CCO) designed on 0.18um CMOS technology. The CCO circuit has tuning range from 251 MHz to 5.5 GHz or 183% wide. It consumes only 144 uA to 9.76mA by using 1.8V power supply. Phase noise is -104 dBc /Hz at 5.5 GHz and 4 Mhz offset frequency. Calculated FoM is -154.4 dBc /Hz which is the best among published counterpart papers. The size of the core oscillator circuits without bonding pads is only 0.0003 mm2. DOI: http://dx.doi.org/10.11591/ijece.v2i3.229

Ultra wideband filter using dumbbell-etched stepped impedance resonator

In this article, an ultra wideband bandpass filter using the dumbbell-etched stepped impedance resonator (SIR) is presented. The filter consists of a dumbbell-etched SIR with an impedance ratio K > 1 and the enhanced coupled input/output lines. The SIR is folded into a dumbbell shape to achieve a smaller circuit size than the filter with conventional SIR. The bandwidth can be analysed using the image-parameter method to obtain the proper dimension of the coupled lines and verified using electromagnetic simulation. The measured 3 dB fractional bandwidth of 110% and insertion loss |S 21| less than 3 dB over the entire passband are achieved.

Design of Compact Quadruplexer Based on the Tri-Mode Net-Type Resonators

A compact size and high isolation microstrip quadruplexer based on the tri-mode net-type resonators is proposed in this letter. The quadruplexer is composed of four folded tri-mode net-type resonator filters with one input and four output coupled-line structures. By adjusting the structural parameters of a single tri-mode net-type resonator, its first three resonant frequencies can be controlled and, thus, it can be utilized to implement a third-order bandpass filter when these resonant frequencies are suitably assigned. The proposed third-order bandpass quadruplexer is constructed by only four tri-mode resonators, showing a small circuit size. In addition, no additional five-pole matching junction is needed for the quadruplexer design. As a result, the proposed quadruplexer occupies an extremely small area, i.e., 0.27 λ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> by 0.09 λ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> (0.42 λ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</i> by 0.13 λ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</i> ), while still keeping good isolation better than 40 dB for each channel.

Noise Analysis and Design of Low-Noise Bias-Offset MOS Transconductor

High integration and low power operation of integrated circuits make noise sensitivity high. Therefore, it is important to reduce noise of circuits. A bias-offset transconductor is known as a linear transconductor. It is expected that noise sensitivity of the transconductor becomes higher due to improvement of linearity and reduction of power dissipation. This paper proposes a design method to reduce noise considering high linearity, reduction of power dissipation and small circuit size.

A Fast Heuristic Algorithm for Multidomain Clock Skew Scheduling

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> In the most general form, clock skew scheduling (CSS) generates a dedicated clock delay for each individual sequential component in the clock distribution network in order to minimize the clock period. Multidomain CSS (MDCSS) relieves this requirement. Instead, sequential components are grouped into several clusters (called clock domains), each of which has a uniform clock delay for all registers within that domain. The skew values of clock domains are provided by a set of deskew buffers with electrically programmable phase shifts and injected after the chip is manufactured. This technique is attractive since, due to process variations, it is becoming overwhelmingly difficult to create precise clock network delays for all sequential elements in a design globally. In this paper, we present a fast algorithm for determining the minimum number of clock domains to be used by MDCSS. The exact solution to this problem cannot be found within a reasonable time if the number of clock domains increases beyond three domains. We show that, even with a small-size circuit, in order to obtain the minimum clock period, more than three clock domains may be required. Therefore, a fast heuristic algorithm is needed to identify these domains. To the best of our knowledge, we present the first efficient heuristic algorithm for this problem. For large benchmark circuits, we solve the problem within 14.7 min on average (as high as 31.7 min for the worst case), while a commercial mixed-integer linear program solver cannot finish in over 5 h. Furthermore, our results show that, for 19 out of 21 small- and medium-size benchmarks, our algorithm yields the optimal solution. </para>

A Compact Dual-Band Bandpass Filter with High Band Selectivity using Cross-Coupled Asymmetric Sirs for Wlans

In this paper, we have proposed the design of novel compact dual-band bandpass filter (BPF) with high band selectivity by using only two asymmetric stepped impedance resonators (SIRs) with one step discontinuity. By arranging the cross-coupled SIRs, three transmission zeros near the passband edges and a high isolation between two passbands are introduced to improve the band selectivity of the proposed filter. The dual-band frequencies of this BPF is implemented by properly selecting the impedance ratio (R) and physical length ratio of the asymmetric SIRs. The bandwidths and the coupling coefficients of the two passbands (2.4/5.2 GHz) can be designed by adjusting the coupling gap between the resonators. The proposed BPF has a smaller circuit size in comparison with previous works using conventional direct-coupling SIRs. The measured results are in good agreement with the full-wave simulation ones.

Hardness-Randomness Tradeoffs for Bounded Depth Arithmetic Circuits

In this paper we show that lower bounds for bounded depth arithmetic circuits imply derandomization of polynomial identity testing for bounded depth arithmetic circuits. More formally, if there exists an explicit polynomial f that cannot be computed by a depth d arithmetic circuit of small size, then there exists an efficient deterministic black-box algorithm to test whether a given depth $d-5$ circuit that computes a polynomial of relatively small individual degrees is identically zero or not. In particular, if we are guaranteed that the tested circuit computes a multilinear polynomial, then we can perform the identity test efficiently. To the best of our knowledge this is the first hardness-randomness tradeoff for bounded depth arithmetic circuits. The above results are obtained using the arithmetic Nisan–Wigderson generator of Kabanets and Impagliazzo together with a new theorem on bounded depth circuits, which is the main technical contribution of our work. This theorem deals with polynomial equations of the form $P(x_1,\dots,x_n,y)\equiv0$ and shows that if P has a circuit of depth d and size s and if the polynomial $f(x_1,\dots,x_n)$ satisfies $P(x_1,\dots,x_n,f)\equiv0$, then f has a circuit of depth $d+3$ and size $\mathrm{poly}(s,m^r)$, where m is the total degree of f and r is the degree of y in P. This circuit for f can be found probabilistically in time $\mathrm{poly}(s,m^r)$. In the other direction we observe that the methods of Kabanets and Impagliazzo can be used to show that derandomizing identity testing for bounded depth circuits implies lower bounds for the same class of circuits. More formally, if we can derandomize polynomial identity testing for bounded depth circuits, then NEXP does not have bounded depth arithmetic circuits. That is, either $\mathrm{NEXP}\not\subseteq P/\mathrm{poly}$ or the Permanent is not computable by polynomial size bounded depth arithmetic circuits.

Galvanic Coupling Enabling Wireless Implant Communications

Galvanic coupling has been shown to be the best method for low-power on-body data transmission. This approach has been extended toward wireless communication between implanted devices, building a real intrabody sensor network. To show the feasibility, a test system has been developed and implemented. The measurements are compared with the numerical simulations. The prototype offers four concurrent channels with a throughput of 4.8 kb/s. The main focus is the future implantability of such a miniaturized system for the medical long-term surveillance of patients. To achieve this goal, small circuit size, low power consumption, and electrical safety have to carefully be considered.

A High-Throughput Single-Flux Quantum Floating-Point Serial Divider Using the Signed-Digit Representation

We propose a floating-point serial divider for a single-flux quantum (SFQ) logic implementation based on a hardware algorithm of division using subtract and shift operations. Fast serial calculations are performed by utilizing the signed-digit representation. The divider is implemented with a regularly aligned pipeline structure called a systolic array. The processing element of the systolic array is designed using several logic gates unique to the SFQ circuits, to reduce the number of pipeline stages. As a result, high throughput and low latency is achieved with a small circuit size. The throughput approaches the maximum throughput of serial processing. A 4-bit divider was fabricated using the 2.5-kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> niobium process technology, and successful operation up to 19 GHz was demonstrated.

Design of dual‐band SIR bandpass filter with a broad upper rejection band for WLANs

AbstractIn this letter, we proposed the design of novel dual‐band bandpass filter (BPF) with a broad upper rejection band using only two asymmetric stepped impedance resonators (SIRs), which has a smaller circuit size in comparison of previous works. The feature of the asymmetric SIR is only one‐step discontinuity, which is different from the conventional SIR with two‐step discontinuities. By selecting properly the impedance ratio (R) and physical length ratio (α) of the proposed asymmetric SIRs, the low loss dual‐band BPF centered at 2.4/5.2 GHz with a wide upper rejection band from 6 to 14 GHz can be implemented perfectly. The bandwidths and the coupling coefficients of the two passbands can be tunable by adjusting the coupling gap distance between the resonators, which are calculated by using full‐wave simulator IE3D. Good agreement between the electromagnetic (EM) simulation and measurement is reported. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1143–1146, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24227

Design of Band-Notched UWB BPF with Very Wide Upper Stopband Using Combined λ/4 TSSIR

In this paper, a new band-notched UWB BPF with a very wide upper stopband is designed using a λ/4-type multi-mode resonator (MMR). The proposed MMR, being formed by combining two identical λ/4 tri-section stepped-impedance resonators (TSSIRs) in a structure-shared fashion, exhibits both λ/4 and embedded λ/2 types of resonance with a relatively smaller circuit size. By properly locating the first four resonant modes of the MMR and the coupling peaks of the input/output parallel-coupled lines, a five-transmission-pole UWB BPF is realized with a favorable uniform in-band UWB response. Besides the good UWB performance, a 5-GHz notched band is created by embedding in the output feed line a T-shape lumped-element bandstop structure to reject the influence from WLAN signals. Also, a very wide upper stopband is achieved by implementing a compact bandstop filter structure in the input feed line together with the properly located transmission zeros generated by the input/output interdigital-coupled lines and the second harmonic of the T-shape bandstop structure. A prototype of the proposed UWB BPF was fabricated and measured for performance verification. The measured results show a return loss of higher than 10 dB, a minimum insertion loss of 0.41 dB, and a group delay variation of less than 0.11 ns in the UWB passband except the notch. The notched band has a 3-dB bandwidth of 18%. The measured upper-end –20-dB stopband ranges from 11.94 to 30.56 GHz, with a bandwidth of 18.62 GHz.

A compact wideband bandpass filter using single asymmetric SIR with low loss and high selectivity

AbstractIn this letter, a novel compact wideband bandpass filter (BPF) using single asymmetric stepped‐impedance resonator with one‐step discontinuity is designed and fabricated. The first two resonant modes of the asymmetric SIR are coupled together and applied to create a wide passband. The proposed filter at center frequency f0 of 4.2 GHz has very good measured characteristics including the bandwidth of 2.9–5.05 GHz (3‐dB fractional bandwidth of 52%), average low insertion loss of 0.2 dB, and sharp rejection of 53 and 88 dB/GHz in lower and higher passband edges. Additionally, the wideband BPF has a smaller circuit size in comparison of previous works. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 242–244, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24023

A novel compact dual‐band bandpass filter using asymmetric SIRs for WLANS

AbstractIn this article, a novel compact dual‐band bandpass filter (BPF) using asymmetric stepped impedance resonators (SIRs) has been presented for the first time. The feature of the proposed asymmetric SIR is only one step discontinuity, which is different from the conventional SIR with two step discontinuities. The frequency response of the dual‐band at 2.4/5.2 GHz can be achieved by determining the impedance ratio (K) and physical length ratio (α) of the asymmetric SIR. The coupling coefficient between the coupled asymmetric SIRs is calculated by using full‐wave simulator IE3D. A dual band BPF is designed, fabricated, and measured. The measured results are in good agreement with the full‐wave simulation results. Additionally, the BPF has a smaller circuit size in comparison of previous works. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1237–1240, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23339

Design of spur‐line‐loaded cross‐coupled dual‐band bandpass filter with wide upper‐end stopband

AbstractThis article presents the design of a compact fourth‐order cross‐coupled dual‐band bandpass filter (BPF) having a wide upper‐end stopband. Quarter‐wavelength (λ/4) stepped‐impedance resonators (SIRs) were employed to construct the BPF to have a relatively small circuit size and high spurious harmonics, as compared with the BPF using half‐wavelength (λ/2) SIRs. The resonators tapped by the input and output feeding lines were loaded by a spur‐line to suppress the first spurious passband so as to further broaden the upper‐end stopband. BPFs with and without the embedded spur‐lines were both simulated to compare their frequency responses. Very good agreement between the simulated and measured results was observed. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 691–694, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23186

Novel compact net-type resonators and their applications to microstrip bandpass filters

Novel compact net-type resonators and their practical applications to microstrip bandpass filters have been presented in this paper. Three kinds of filters are designed and fabricated to demonstrate the practicality of the proposed compact net-type resonators. In addition, by adjusting the structural parameters of the net-type resonators, the spurious frequencies can be properly shifted to higher frequencies. As a result, a three-pole Chebyshev net-type resonator filter with a fractional bandwidth (FBW) of 6.8% has a spurious resonance of up to 4.1f/sub 0/, and it has more than 80% size reduction in comparison with the conventional U-shaped resonator filter. A four-pole quasi-elliptic net-type resonator filter with a FBW of 3.5% has a spurious resonance of up to 5f/sub 0/, and it has approximately 67% size reduction in comparison with the cross-coupled open-loop resonator filter. A three-pole trisection net-type resonator filter with a FBW of 4.7% has a spurious resonance of up to 6.5f/sub 0/, and its size is reduced by 68% in comparison with the trisection open-loop resonator filter. Consequently, each of the designed filters occupies a very small circuit size and has a good stopband response. The measured results are in good agreement with the full-wave simulation results by IE3D.

Injection-locked balanced oscillator-doubler

A sub-harmonic injection-locked balanced microwave oscillator-doubler configuration is presented. A highly stabilised signal with low harmonic distortion and high fundamental signal rejection is produced without using any balun. The integrated approach results in a small circuit size and low power consumption requirement.