Small Capacitance Research Articles

Comprehensive Analysis and Improvement Methods of Noise Immunity of Desat Protection for High Voltage SiC MOSFETs With High DV/DT

This paper comprehensively analyzes desaturation (desat) protection for high voltage (>3.3 kV) silicon carbide (SiC) MOSFETs and especially how to build in noise immunity under high <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> . This study establishes a solid foundation for understanding the trade-offs between noise immunity and response speed of desat protection. Two implementations of the desat protection for high voltage SiC MOSFETs are examined, including desat protection based on discrete components and desat protection realized with a gate driver integrated circuit (IC). Both positive <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> and negative <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> are investigated. Analysis results show that the high <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> with long duration caused by high voltage SiC MOSFETs’ switching results in strong noise interference in the desat protection circuitry. The impact of numerous influencing factors is investigated analytically, such as parasitic capacitances, parasitic inductance, damping resistance, and clamping impedance. Under high positive <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> , extremely small parasitic capacitances (<0.01 pF) between the drain terminal and protection circuitry could still compromise noise immunity of the desat protection circuitry that has a high-impedance voltage divider. Comprehensive design guidelines are summarized to boost the noise immunity, including circuit design, component selection, and PCB layout. The noise immunity margin under the positive <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> is also derived quantitatively to guide the noise immunity improvement. The noise immunity analysis results and noise immunity improvement methods are validated with simulation and experimental results obtained from a phase leg based on 10 kV/20 A SiC MOSFETs.

Reliability Study of 1T1C FeRAM Arrays With Hf0.5Zr0.5O₂ Thickness Scaling

We have reported that film thickness scaling of ferroelectric Hf0.5Zr0.5O2 (HZO) allows hafnium-based one-transistor and one-capacitor (1T1C) ferroelectric random-access memory (FeRAM) to obtain higher cycling tolerance for hard breakdown with lower voltage operation in prior reports. This paper is an extension of the previous works including a review of recent works on FeRAM-related devices from a film thickness scaling point of view. We experimentally verified the cycling tolerance advantage of film thickness scaling by 1T1C FeRAM array with different HZO thicknesses of 8 nm and 10 nm using different small capacitors areas (0.20, 0.40, and 1.00 lm2) at practical operation conditions for the first time, demonstrating higher reliability at the 8-nm sample with smaller capacitance area. To support the result, time zero dielectric breakdown (TZDB) and time dependent dielectric breakdown (TDDB) were conducted for both 8-nm and 10a-nm samples.

Dielectric Elastomer Generator with a Voltage-Difference-Type Output Circuit Considering Leakage Currents

The use of environmental vibrations as a power source for IoT devices has been attracting increasing attention. Dielectric elastomer generators (DEG) convert the mechanical energy to the electrical one by utilizing the capacitance change according to its deformation, and are expected for the generators for low-frequency vibrations. The self-priming circuit (SPC) that boosts the voltage of the DEG is widely used. For the power source for the IoT devices, voltage step-down elements such as Zener diodes can be introduced, however, the energy loss will deteriorate the efficiency. Moreover, for quick voltage boosts, the use of small capacitance condensers in the SPC is required, which will make the generators sensitive to the leakage currents. This study proposes a DEG circuit that utilizes a rectifier as the output circuit elements connected between the DEG and SPC, instead of the step-down elements connected parallel to them. The current flow to the load is governed by the voltage difference between the DEG and SPC, thus, we can choose larger capacitance condensers for the SPC. We first derive the formulae for the charge increments in a cycle, then the properties of the proposed circuit are precisely discussed. To see the property under the existence of the leakage current, experiments are conducted, which show the effectiveness of the proposed circuit.

An Energy-Efficient Low-Area Double-Node-Upset-Hardened Latch Design

The energy-efficient circuits, though important in IoT and biomedical applications, are vulnerable to soft errors due to their low voltages and small node capacitances. This paper presents an energy-efficient low-area double-node-upset-hardened latch (EEDHL). The proposed latch enhances the radiation hardness by employing a restorer circuit based on a Muller C-element and a memory element. The post-layout simulations show that the EEDHL improves the area–energy–delay product (AEDP) by [Formula: see text]80% compared to the newly reported double-node-upset-resilient latch (DNURL) in STMicroelectronics 65-nm CMOS technology. Synopsys TCAD mixed-mode simulations in 32-nm CMOS technology framework are also used to validate the proposed DNU-hardened latch. The proposed EEDHL effectively mitigates the DNU at the strike with a linear energy transfer (LET) equal to 160[Formula: see text][Formula: see text]/mg in 32-nm CMOS technology.

An Input-Series Output-Parallel Modular Three-Phase AC–AC Capacitive-Link Power Converter

Modular converters with stackable cells are widely used in high-power applications, where the voltages and/or currents are beyond the ratings of the commercially available switches. Majority of existing modular converter topologies are based on dc-link converters that require several electrolytic capacitors with large capacitances, which reduce the lifetime of the power converter and increase size and volume. This article proposes an input-series output-parallel modular three-phase ac-ac universal power converter, which is formed by three identical and stackable capacitive-link modules that do not require electrolytic capacitors for power conversion. Exclusion of the electrolytic capacitors is achieved by operating the modules in discontinuous capacitor voltage mode. Each module requires two film capacitors with very small capacitances for transferring the power and provides galvanic isolation through high-frequency transformers. Utilization of film capacitors with small capacitances enhances the reliability. Furthermore, the proposed stackable capacitive-link modules enable a scalable and modular design. In this article, power cells are connected in series at the input and in parallel at the output to form a modular universal power converter that can share voltage/current among the power cells in an ac-ac power conversion system. Frequency transformation and voltage step-up/-down are among the other features of the proposed converter. The details of the operation principles along with design considerations are discussed in this article. Moreover, the proposed modular power converter with two power cells is evaluated through simulations and experiments.

Discontinuous Space Vector Modulation for Three-Phase Five-Levels Packed-U-Cell Converter

This article proposes an optimal 3D space vector modulation algorithm for the three-phase five-levels packed U-cell converter. The algorithm consists of selecting a common-mode voltage that results in discontinuous modulation, as a result, the reference voltage vector is clamped to the external faces of the 3D space vector diagram and there is always a phase that does not switch for a certain period. Hence, the search for nearest vectors is reduced to a 2D plane and there are no redundancies in the abc coordinates. Moreover, the switching sequence is defined online in order to reduce the converter phase voltage transitions while ensuring half-wave symmetry. In addition, a cost function is proposed to optimize the number of commutations and maintain the capacitor voltages balanced. The proposed algorithm presents advantages when compared to other strategies, such as low computational effort, reduced switching losses, and smaller capacitors. Simulation results demonstrate the good performance and effectiveness of the proposed modulation compared to works previously published in the literature. Finally, experimental results from 2-kVA three-phase five-levels packed-U-cell converter are given to support the theoretical developments.

Variable DC-Link Voltage Regulation of Single-Phase MMC Battery Energy-Storage System for Reducing Additional Charge Throughput

Battery energy-storage system (BESS) based on the modular multilevel converter (MMC) can flexibly manage the battery packs integrated into submodules, where the battery pack can directly or through a small capacitor connect to the rear-end half-bridge circuit for reducing cost and volume caused by an additional dc-dc converter. But the alternating current ripples will cause substantial additional charge throughput for battery packs and, consequently, reduce the battery lifetime in theory. Therefore, this article proposes a variable dc-link voltage regulation method for a single-phase MMC-BESS. In specific, the phase disposition (PD) modulation scheme is improved to properly bypass the gating signals with unnecessary conduction during operation and the modified gating signals will be rearranged for balancing the states-of-charge and states-of-health. Doing so, the additional charge throughput could be significantly reduced compared with the traditional phase-shift modulation and PD modulation. Even comparing with the ideal dc current charging/discharging, the proposed method will only increase slight additional charge throughput and nearly negligible capacity loss. The experimental results of a 6.6 kW/6.6 kWh single-phase MMC-BESS prototype verified the performance of the proposed method.

A New Approach to Designing High-Sensitivity Low-Dimensional Photodetectors

Photodetectors fabricated from low-dimensional materials such as quantum dots, nanowires, and two-dimensional materials show tremendous promise based on reports of very high responsivities. However, it is not generally appreciated that maximizing the internal gain may compromise the detector performance at low light levels, reducing its sensitivity. Here, we show that for most low-dimensional photodetectors with internal gain the sensitivity is determined by the junction capacitance. Thanks to their extremely small junction capacitances and reduced charge screening, low-dimensional materials and devices provide clear advantages over bulk semiconductors in the pursuit of high-sensitivity photodetectors. This mini-review describes and validates a method to estimate the capacitance from external photoresponse measurements, providing a straightforward approach to extract the device sensitivity and benchmark against physical limits. This improved physical understanding can guide the design of low-dimensional photodetectors to effectively leverage their unique advantage and achieve sensitivities that can exceed that of the best existing photodetectors.

A side‐effect‐free method of reducing capacitance requirement for modular multilevel converters

In modular multilevel converters (MMCs), the huge capacitor almost takes over half of the cost and weight of a submodule; as a result, the capacitance requirement reduction has attracted wide attention for using smaller capacitors. However, the existing methods have side effects, such as increasing the arm current and adding additional semiconductors, which restrict their practical applications. Thus, a side-effect-free capacitance requirement reduction (CRR) method is proposed in this paper. In the method, the capacitor voltage can be decreased by injecting a specific dc signal into the original control system; and the specific dc signal is outputted from the proposed CRR controller according to the transmitted power of the MMC. For ensuring the safe operation, the extent to which the capacitor voltage can be reduced is also studied; and an optimisation model is presented to obtain the minimum allowed capacitor voltage and the safety domain of CRR. The effectiveness of the proposed method is proved by both simulation and experiment. The results show that the capacitance requirement can be reduced by 32.4% without neither increasing the arm current nor adding additional semiconductors.

GaN-based power devices: Physics, reliability, and perspectives

Over the last decade, gallium nitride (GaN) has emerged as an excellent material for the fabrication of power devices. Among the semiconductors for which power devices are already available in the market, GaN has the widest energy gap, the largest critical field, and the highest saturation velocity, thus representing an excellent material for the fabrication of high-speed/high-voltage components. The presence of spontaneous and piezoelectric polarization allows us to create a two-dimensional electron gas, with high mobility and large channel density, in the absence of any doping, thanks to the use of AlGaN/GaN heterostructures. This contributes to minimize resistive losses; at the same time, for GaN transistors, switching losses are very low, thanks to the small parasitic capacitances and switching charges. Device scaling and monolithic integration enable a high-frequency operation, with consequent advantages in terms of miniaturization. For high power/high-voltage operation, vertical device architectures are being proposed and investigated, and three-dimensional structures—fin-shaped, trench-structured, nanowire-based—are demonstrating great potential. Contrary to Si, GaN is a relatively young material: trapping and degradation processes must be understood and described in detail, with the aim of optimizing device stability and reliability. This Tutorial describes the physics, technology, and reliability of GaN-based power devices: in the first part of the article, starting from a discussion of the main properties of the material, the characteristics of lateral and vertical GaN transistors are discussed in detail to provide guidance in this complex and interesting field. The second part of the paper focuses on trapping and reliability aspects: the physical origin of traps in GaN and the main degradation mechanisms are discussed in detail. The wide set of referenced papers and the insight into the most relevant aspects gives the reader a comprehensive overview on the present and next-generation GaN electronics.

Characteristics of Series‐Connected Resonant Tunneling Diode‐Pair Configuration for High Output Power Operation

Herein, a series‐connected resonant tunneling diode (RTD)‐pair configuration is characterized using the dynamic capacitance characteristics of the RTD. To achieve enhanced output power characteristics, the RTD‐pair cell is utilized in the RTD oscillator design to increase the voltage span and current span of the negative differential conductance (NDC) region. The results indicate that not only the output power can be significantly improved compared with the single‐RTD oscillator, but also it operates at a small capacitance region, making the RTD‐pair oscillator beneficial for high frequency and high output power operation.

Convergence of Levenberg-Marquardt Estimates of Nonlinear Parameters in EIS Analysis of Coated Aluminum Panels

Equivalent circuit models are frequently employed to analyze electrochemical impedance spectroscopy (EIS) data. However, aside from some simple cases in which the equivalent circuit element parameters can be estimated directly from a plot of the data, the parameters for each of the equivalent circuit elements must often be estimated through the implementation of a nonlinear least-squares regression method. One frequently-used approach is the powerful Levenberg-Marquardt algorithm. This algorithm functions as a damped least-squares method that performs an interpolation between the steepest-descent and the Gauss-Newton methods for estimating nonlinear parameters. However, there are several challenges to using a Levenberg-Marquardt algorithm to model EIS data. The nonlinear nature of the impedance equations along with the difference in the magnitude of the parameter values can result in the algorithm failing to converge to a local minimum in the parameter space. This convergence challenge can be seen in determining equivalent circuit values for undamaged coating systems that have a high pore resistance, a small capacitance, as well as contributions from the underlying metal substrate. A Levenberg-Marquardt algorithm, along with a heuristic approach to use the raw data to improve the initial parameter estimates, is implemented that provides an improved approach for nonlinear regression fits of equivalent circuit models. A comparison of three equivalent circuit models fits, with residuals, for a two-layer coating system on an aluminum substrate is shown in the attached figure.Figure caption: Plot of EIS data (+ symbols) from a cured coating system prior to any environmental exposures compared with 3 equivalent circuit model fits (solid lines). The model fits were obtained using an NRL-developed Levenberg-Marquardt nonlinear regression fitting routine.The Department of Defense Strategic Environmental Research and Development Program (SERDP) sponsored this project under work unit 5399. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of the Office of Naval Research, the U.S. Navy, the Department of Defense, or the U.S. government. Figure 1

A capacitance measurement circuit with current injection compensation

The capacitive touch screen measurement system mainly realizes the conversion of capacitance to digital signal, but the parasitic capacitance existing on the chip IO and PCB board will seriously affect the measurement accuracy of the small inductive capacitance in the capacitance measurement circuit. To solve this problem, a capacitance measurement circuit with adjustable compensation time based on current injection is proposed.The mismatch error in the circuit is analyzed in detail, and the measurement accuracy of capacitance is further improved. The dynamic range of capacitance measurement can be effectively improved by appropriately changing the parameter value of the relevant quantity in the circuit. The circuit design is based on the SMIC 0.18 μm standard CMOS process, and the overall layout area is about 0.21 mm2. The circuit is simulated using Spectre tool, and the results show that the capacitance measurement circuit inductive capacitance of 0 ~ 1 pF in the temperature range of -40 ℃ to 125 ℃, the conversion time is about 50 μs, and the resolution can reach 1 fF, the signal to noise ratio of the converted 12 bit digital signal is 70.1 dB, the effective number of bits is 11.56 bits, the power supply voltage is 1.8 V, and the total power consumption is 0.19 mW.

A programmable gain and bandwidth amplifier based on tunable UGBW rail-to-rail CMOS op-amps suitable for different bio-medical signal detection systems

This work presents a bio-medical amplifier with programmable Gain and Bandwidth. The bandwidth of the proposed amplifier is controlled by tuning the unity-gain bandwidth (UGBW) of a rail-to-rail CMOS operational amplifier. The amplifier gain is controlled by changing the input capacitors keeping the bandwidth unchanged. The proposed bio-medical amplifier capable to accommodate different signals with a bandwidth ranging from 50 Hz up to 10 kHz to detect different bio-potential signals: EEG, ECG, EMG, PCG, and Aps, using fixed and small load capacitance. The proposed bio-medical amplifier consists of two stages each one designed with Tera ohm CMOS pseudo-resistors used in the amplifier feedback. The lower cutoff frequency of the bio-medical amplifier is tuned using two biasing currents in the CMOS pseudo-resistors, while two biasing voltages in the CMOS op-amps tune the higher cutoff frequency. The gain of the proposed bio-medical amplifier is ranging from 44.3 dB to 65.1 dB. High stability of the CMOS based op-amps (phase margin ≥60°) over the whole Gain and Bandwidth ranges is achieved. The overall power consumption of the bio-medical amplifier is less than 3.28 μW at the maximum gain settings of 65 dB and a maximum bandwidth of 10 k Hz. The total harmonic distortion of the proposed amplifier less than 1.21% for an input amplitude of 1 mVpk-pk over the entire bandwidth. The Input referred noise spectral density is 426 nV/Hz @1 kHz for the maximum bandwidth settings. The proposed bio-medical amplifier achieves an IIP3 value of 19.44 dBm for the amplifier gain of 54.9 dB. The simulation results show that the proposed bio-medical amplifier is robust against the PVT variations. LT-spice simulations using the standard 90 nm CMOS technology under 1 V supply voltage are performed to validate the theoretical results of the proposed amplifier.

Performance Investigation of Switched Reluctance Motor Driven by Quasi-Z-Source Integrated Multiport Converter with Different Switching Algorithms

Switched reluctance machines (SRMs) have received increasing attention for their many potential uses, such as for wind power and electric vehicle (EV) drive systems. The Quasi-Z-source Integrated Multiport Converter (QZIMPC) was recently introduced to improve the reliability of the SRM driver through small capacitance values. It is not possible, however, to simultaneously energize and deenergize two SRM phases in QZIMPC. This phenomenon can significantly increase the commutation period which, in turn, degrades the performance of SRM; in addition, this causes high-voltage ripples on the converter’s capacitors. Two switching algorithms are introduced and applied in this paper, and their performance with SRM is investigated in terms of torque ripple and peak phase current. The algorithms are based on prioritizing the control command in the on-going and off-going phases to fulfill the required load torque, as well as to accelerate the commutation process where possible. This is achieved without the interference of high-level controllers, which include speed controllers and/or torque ripple minimization. Through the simulation results, a comparison between the two switching algorithms is presented to determine their potential to improve the SRM drive system’s performance.

High PSRR Wide Supply Range Dual-Voltage Reference Circuit for Bio-Implantable Applications

On-chip systems are challenging owing to the limited size of the components, such as the capacitor bank in the rectifier. With a small on-chip capacitor, the output voltage of the rectifier might ring if the circuit experiences significant changes in current. The reference circuit is the first block after the rectifier, and the entire system relies on its robustness. A fully integrated dual-voltage reference circuit for bio-implantable applications is presented. The proposed circuit utilizes nonlinear current compensation techniques that significantly decrease supply variations and reject high-supply ripples for various frequencies. The reference circuit was verified using a 0.35 µm complementary metal-oxide semiconductor (CMOS) process. Maximum PSRR values of −112 dB and −128 dB were obtained. With a supply range from 2.8 to 12 V, the proposed design achieves 0.916 and 1.5 mV/V line regulation for the positive and negative reference circuits, respectively.

A 59 pA/V and 62 nW Differential OTA with 0.35% THD for Biomedical Applications

This paper presents a novel differential pA/V Operational Transconductance Amplifier (OTA) topology. The circuit is suitable for the implementation of fully integrated operational transconductance amplifier-capacitance (OTA-C) filters with small feature size capacitors, suited for electrophysiological signal acquisition and conditioning. Unlike typical OTA-Cs, the proposed topology consists of transconductance reduction technique based on unbalanced output branches thatallow current subtraction thus enabling transconductances in the order of pA/V. The technique is demonstrated through the design of a 59pA/V transconductor, which is very suited for designing long-time-constant filters. This OTA-C achieved a worst-case 0.35% THD with just 61.7nW average power consumption, which allows its applicability to biomedical implants. Simulations were carried out with STMicroelectronics 0.13µm HCMOS9 node using Cadence’s IC design tools. Weemployed the OTA in a design of a fourth-order bandpass filter with a narrow bandwidth of 12.5–21.8Hz. Similar results to the ideal transfer function, turn the proposed OTA ideal for biosensing-based applications.

A high-precision current measurement platform applied for statistical measurement of discharge current transient spectroscopy of traps in SiN dielectrics

This paper presents a current measurement platform to measure current across dielectrics with a high-precision of 10−17 A from a large number of small capacitors at high speed. The developed platform consists of a common readout circuit part and a dielectric part formed on the circuit part by a simple process. A platform chip with 10 μm pitch 384H × 360V cells was fabricated using a 0.18 μm CMOS technology and silicon nitride (SiN) films were formed by plasma-enhanced CVD (PECVD) as a measurement target. The trap property of SiN films in metal–insulator–metal (MIM) capacitors was statistically measured by discharge current transient spectroscopy (DCTS) using the developed platform. The measured average energy levels of traps (E c –E t ) were 0.21–0.25 eV, which is in good agreement with that of the discrete samples. The distributions of energy levels and densities of traps measured with different film thicknesses and areas are also presented and discussed.

Singular Perturbation Method Applied to Power Factor Correction Converter Application

A linear discrete stable control system is considered. The Power Factor Correction (PFC) converter to allow independent control of current and voltage. It converter are fast and slow states to inheres sty present small parameters inductor and capacitor its computes stiffness and to include switching ripple effects. As an alternative a Singular Perturbation Method (SPM) is presented Initial Value Problem (IVP) and Boundary Value Problem (BVP). It is applied to two state switching power converters to provide rigorous justification of the time scale separation. It is modeled as a one parameter singularly perturbed system. SPM consists of an outer series solution and one boundary layer correction (BLC) solution. A boundary layer correction is required to recover the initial conditions lost in the process of degeneration and to improve the solution. SPM is carried out up to second-order approximate solution for the PFC converter model for IVP and BVP. The results are compared with the exact solution (between with and without parameters). The results substantiate the application.

A zinc ion hybrid capacitor based on sharpened pencil-like hierarchically porous carbon derived from metal–organic framework

Aqueous zinc ion hybrid capacitors (ZIHCs) are an emerging class of energy storage devices with the merits of high-energy-power density, low cost and high safety. But the energy density still is behind the expectation due to the low voltage output and small specific capacitance. Seeking high performance capacitive-type carbon material are the one choice to capture these challenges. Herein, a high performance ZIHC device in aqueous electrolyte was assembled by using a sharpened pencil-like hierarchically porous carbon rod derived from the metal–organic framework. Thanks to the high specific surface area, fairish pore size distribution and rich oxygen-containing functional groups of carbon cathode, the excellent specific capacitance and high energy density were demonstrated. The assembled ZIHC device could achieve a high energy density of 130.1 W h kg−1 at power output of 180.3 W kg−1 under a relatively wide operation voltage of 0–1.8 V, and remain 59 W h kg−1 even at high power density of 7.8 kW kg−1. Meanwhile, this device also exhibited an excellent cycling life up to 10 000 cycles at 10 A g−1 with capacity retention of 96.7%. This research provides a new idea for the application of MOF-derived carbon materials in zinc ion hybrid capacitors.