Small Capacitive Load Research Articles

Dynamic resistivity of Pb(Zr0.95Ti0.05)O3 depolarized ferroelectric under shock wave compression

Explosive-driven ferroelectric generator (EDFEG) has important applications due to its excellent properties of high energy density and small volume. The output of EDFEG is based on the depolarization of ferroelectric during shock wave compression. In a normal mode configuration, a planar shock wave propagates in a direction perpendicular to the polarization axis. If the resulting depolarizing current passes through a large resistive load or a small capacitive load, high electric fields can be produced within the ferroelectric sample. In this case, a portion of the depolarizing charges are lost in the sample due to finite resistivity of shocked ferroelectrics during shock wave transit. But it is very difficult to accurately measure the resistivity of shocked ferroelectric during shock wave compression, due to high pressure and short duration time. In previous studies, the value of the resistivity of shocked Pb(Zr0.95Ti0.05)O3 (PZT95/5) ferroelectric was obtained from the experimental output charge difference for different large resistive loads or by fitting the experimental current histories. However, the current leakage was not observed directly in experiment in the past. Furthermore, the value of the resistivity obtained in each of all these studies was a time-averaged value. In the present work, a new experiment method is developed to investigate dynamic resistivity of PZT95/5 under shock wave compression, in which a pulse capacitor is used as an output load. The current leakage in shocked PZT95/5 is observed in the experiment at a shock stress of 3.5 GPa after the depolarization of all ferroelectrics. This current leakage is just related to the resistance of shocked PZT95/5 and the voltage applied. The experimental results show that the resistivity of shocked PZT95/5 continuously changes in a range of 2.2104 cm-3.5104 cm for time more than the shock transit time of the sample. Based on the experimental results, a dynamic resistance model is established to analyze the resistivity of depolarized PZT95/5 ferroelectric ceramic during shock wave transit in ferroelectric. The simulation results reveal dynamic characteristic of the resistivity of depolarized PZT95/5 ferroelectric ceramic under shock wave compression. The further analysis of experimental results shows that the resistivity continuously changes between 2.0104 cm and 8.0104 cm during shock transit in ferroelectrics. It is believed that dynamic characteristic of the resistivity of shocked PZT95/5 ferroelectric ceramic is related to pressure, electrical field applied and the defects in the material. The dynamic resistivity of shocked PZT95/5 obtained in this paper and its dynamic resistance model will be helpful for designing EDFEGs and their applications in the future.

Broadband linear high-voltage amplifier for radio frequency ion traps.

We developed a linear high-voltage amplifier for small capacitive loads consisting of a high-voltage power supply and a transistor amplifier. With this cost-effective circuit including only standard parts sinusoidal signals with a few volts can be amplified to 1.7 kVpp over a usable frequency range at large-signal response spanning four orders of magnitude from 20 Hz to 100 kHz under a load of 10 pF. For smaller output voltages the maximum frequency shifts up to megahertz. We test different capacitive loads to probe the influence on the performance. The presented amplifier is sustained short-circuit proof on the output side, which is a significant advantage over other amplifier concepts. The amplifier can be used to drive radio frequency ion traps for single charged nano- and microparticles, which will be presented in brief.

A 12.5 Gb/s 6.6 mW receiver with analog equalizer and 1-tap DFE

This paper presents a compact, low power 12.5Gb/s backplane receiver in a 90nm CMOS technology. The receiver incorporates an analog equalizer, which is designed using active inductor circuit, and a 1-tap speculative decision-feedback- equalizer (DFE). The proposed active inductor circuit provides wider tuning range and higher inductive impedance with respect to the previous reported topologies, using negative impedance implemented by a cross coupled transistor pair, at the output nodes of active inductor circuit. The DFE is designed in half rate architecture utilizing an improved front end sample and hold to speculate the first feedback tap while consuming low power and imposing small capacitive load on the analog equalizer block. The input capacitance of the DFE block is alleviated more by changing the place of multiplexer in the DFE architecture. Furthermore power consumption reduction in DFE architecture is achieved by using a novel high speed slicer with rail-to-rail swing in the output to avoid implementing latches and MUXs in the next stages in CML topology. The receiver consumes 6.6mW from a 1.2V supply while delivering 12.5Gb/s data over 5″ NELCO 4000-6 channel in the presence of two aggressor far-end-crosstalk (FEXT) signals.

ACTIVE-FEEDBACK SINGLE MILLER CAPACITOR FREQUENCY COMPENSATION TECHNIQUES FOR THREE-STAGE AMPLIFIERS

This paper presents two novel active-feedback single Miller capacitor frequency compensation techniques for low-power three-stage amplifiers. These techniques include the active-feedback single Miller capacitor frequency compensation (AFSMC) and the dual active-feedback single Miller capacitor frequency compensation (DAFSMC). In the proposed techniques, only one Miller capacitor in series with a current buffer is utilized. The main advantages of the proposed three-stage amplifiers are the enhanced unity-gain bandwidth and the reduced silicon area. Small-signal analyses are performed and the design equations are obtained. Extensive HSPICE simulation results are provided to show the usefulness of the proposed AFSMC and DAFSMC amplifiers in both large and small capacitive loads.

Design criterion for high-speed low-power SC circuits

The settling behavior of switched-capacitor (SC) circuits is investigated in this paper. The analysis is performed for typical SC circuits employing two-stage Miller-compensated operational amplifiers (op-amps). It aims to evaluate the real effectiveness of the conventional design approach for the optimization of op-amp settling performances. It is demonstrated that the classical strategy is quite inaccurate in typical situations in which the load capacitance to be driven by the SC circuit is small. The presented study allows a new settling optimization strategy based on an advanced circuit model to be defined. As shown by design examples in a commercial 0.35- µm CMOS technology, the proposed approach guarantees a significant settling time reduction with respect to the existing settling optimization strategy, especially in the presence of small capacitive loads to be driven by the SC circuit. Copyright © 2010 John Wiley & Sons, Ltd.

Single-Capacitor Active-Feedback Compensation for Small-Capacitive-Load Three-Stage Amplifiers

This brief presents a single-capacitor active-feedback compensation (SCAFC) scheme for three-stage internal amplifiers driving small capacitive loads. The proposed SCAFC scheme can stabilize the three-stage amplifier by using only a single small-value compensation capacitor, thereby significantly reducing the amplifier implementation area. With the small-value compensation capacitor, the wide gain-bandwidth product (GBW) of the SCAFC amplifier can also be achieved under low-power conditions. Implemented in a standard 0.35-mum CMOS process, the proposed three-stage SCAFC amplifier achieves over 100-dB dc gain, 9.6-MHz GBW, and 6.1-V/mus average slew rate, by only dissipating 90 muW at 1.5 V and using a 1-pF compensation capacitor, when driving a 500-kOmega // 20-pF load. The proposed SCAFC amplifier experimentally improves both bandwidth-to-power and slew-rate-to-power efficiencies by more than 14 times and 9 times, respectively, as compared to a conventional three-stage nested-Miller-compensated amplifier.

Optimal Capacitive Load Matching of Micro Electret Power Generators

This paper presents a model of micro-electret power generators. This model uses two capacitors with fixed charge density and variable area to model the actual micro electret power generator. Simulations of power output with capacitive loads and resistive loads are presented. The power output decreases as the load capacitance increases while it increases as the resistive load increases. To verify the model and simulation results, power output generation experiments are performed and the results confirm the simulation. To collect useful energy from the power generator, a small capacitive load, rather than a resistive load, is required.

A 200-v high-voltage amplifier using a parasitic field-oxide transistor for voltage feedback

A 200-V high-voltage amplifier with a 50-kHz bandwidth is built in a 10-V trench-isolated CMOS process with complementary high-voltage transistors. The high-voltage amplifier uses parasitic field-oxide transistors to dc stabilize the input-output voltage transfer characteristic. Use of parasitic field-oxide transistors for output voltage sensing provides only a small capacitive output load and eliminates the need for high-voltage resistor feedback networks. By removing resistor feedback networks, compact and low-power high-voltage amplifiers may be realized for a certain class of applications.