Small Capacitance Research Articles

12b 500MS/s successive‐approximation‐register‐assisted pipeline analogue‐to‐digital convertor using a four‐stage ring amplifier with coarse‐analogue‐to‐digital convertor embedded

AbstractThis article presents a 12b 500MS/s successive‐approximation‐register‐assisted pipeline analogue‐to‐digital converter. By adopting a new auto‐zero scheme, a calibration‐free four‐stage ring residue amplifier with a small offset cancellation capacitor is proposed. In addition, the coarse‐analogue‐to‐digital converter of the second stage is embedded into the amplification phase, which relaxes the comparison periods of the first and second stages by 25.0% and 17.4%, respectively. Post‐simulated in 28‐nm CMOS technology with a 0.9 V supply, the analogue‐to‐digital converter achieves 62.2 dB SNDR and 78.1 dB SFDR. It consumes 8.45 mW with an on‐chip reference voltage buffer, resulting in Schreier's figure of merit (FoMS) of 166.9 dB.

A soft-start scheme based on mismatch of OPA for DC-DC converters

Aiming at output voltage overshoot during start-up period, a soft-start scheme for dc-dc converters with the features of a small on-chip capacitor is adopted in this article. The proposed soft-start method utilizes the mismatch characteristics of operational amplifiers (OPAs) to generate a small current for charging the capacitor, thereby reducing the capacitor size. The experimental results reveal that the proposed soft-start scheme is implemented in 0.18 μm BCD process and occupies an area size of 0.018 mm2. The proposed soft-start period of 500μs is achieved with an on-chip capacitor of 10.8 pF. Besides, the peak efficiency of the dc-dc converter that employing proposed soft-start scheme can reach 94.86 % and the deviation of the output voltage is within ±2.25 %.

Quadratic Boost Converter with Optimized Switching Ripple Based on the Selection of Passive Components

This work introduces a boost converter with quadratic gain. Its main advantage compared to well-known similar quadratic boost converters is that it requires capacitors with a relatively small capacitance and inductors with small inductance, leading to a reduction in the size or stored energy while performing a power conversion of similar power rating and the same switching ripples in both the input current and the output voltage. It is inspired by the recently introduced ISB converter and uses a specific PWM method. This results in achieving switching ripple constraints while using smaller energy storage elements (capacitors and inductors). The updated converter offers the same voltage gain compared to the conventional quadratic boost topology with the benefit of compact component sizes. While it has more passive elements, they are of reduced size. An analysis of energy storage revealed that this new converter uses only half the energy in inductors and 14% in capacitors when compared to specific design parameters.

Design and analysis of power decoupling based microinverter considering parasitic parameters

With fossil energy reducing year by year, more and more attention to the new energy sources greatly promotes the development of the distributed power generation system, especially the low-power photovoltaic system. However, the power injected into the single-phase grid is time-varying, an electrolytic capacitor with large bulk should be paralleled with PV to balance the input and output power ripple. But the electrolytic capacitor has a very short lifetime, which could shorten the whole inverter’s lifetime. In this paper, the operational principle of the power decoupling based microinverter considering parasitic parameters is proposed, in which a film capacitor with small capacitance value replaces the electrolytic capacitor to improve the lifetime of the inverter. Further, the operating mode of the transformer and the decoupling capability is analyzed, and obtains the reasons affecting the inverter steady-state performance. Finally, the simulation and experiment validation of the proposed microinverter have been accomplished. Base on the analysis method proposed in this paper, a more accurate device selection can be provided for industrial design.

Circuit Modeling of the Impact of Heavy Charged Particles on Transient Processes in Bipolar Analog Microcircuits

One of the factors causing the failure of spacecraft integrated circuits is exposure to heavy charged particles. The entry of heavy charged particles into electronic devices leads to the appearance of single event transients (short current pulses), which in analog microcircuits manifest themselves in distortion of the output signal shape, and in digital microcircuits can cause a single event upset. The article discusses a technique for circuit mode-ling of the effect of heavy charged particles on bipolar analog microcircuits, including the developed equivalent electrical circuit of a bipolar transistor for LTSpice and the procedure for modeling transient processes. Despite the simplifications adopted, namely: failure to take into account the dependence of the duration of the rise and fall of the current pulse generated by a charged particle on the parameters of the transistor structure, the assumption that the entire charge is generated in the active base and the space charge regions of the emitter and collector junctions, an equivalent circuit has been developed made it possible to determine that the shape of the collector current pulse for circuit with a common emitter when exposed to a heavy charged particle is determined by the speed of the transistor and its operating mode. Using the developed methodology, the “critical” transistors of the two studied analog microcircuits were determined, and the need to bypass the current-setting resistors with a small capacitor was justified.

Biosensing beyond Debye screening length using epitaxial graphene field-effect transistors on SiC substrate

We demonstrated the antigen detection beyond Debye screening length using antibody-modified epitaxial graphene field-effect transistors (FETs), which have been considered to be impossible because of the Debye screening length. The transfer characteristics of the graphene FETs with a single crystal epitaxial graphene film showed no concentration dependence of buffer solutions. The capacitance measurements in an epitaxial graphene FET also showed no concentration dependence, indicating that the solution-gate capacitance of the epitaxial graphene FET was independent on the Debye screening length. In addition, the minimum capacitance values were also almost independent for the concentration change. Since the Debye screening length depends on the ionic strength of the solution, which is proportional to the buffer solution concentration, the electrical characteristics of solution-gated epitaxial graphene FETs are almost independent on the Debye screening length owing to their small quantum capacitance. The antibody-modified epitaxial graphene FETs indeed detected the antigen, indicating that the epitaxial graphene FETs can detect the target beyond the Debye screening length without any complicated device fabrication processes and other desalted apparatuses.

Startup Analysis and Design of Self-Powered Auxiliary Power Supply in Input-Series System With Small Submodule Capacitance

Startup Analysis and Design of Self-Powered Auxiliary Power Supply in Input-Series System With Small Submodule Capacitance

Active damping control based bus voltage resonance suppression in electrolytic capacitorless PMSM application

Abstract The structure of electrolytic capacitorless in automotive electronic applications has the advantages of lower cost and better reliability. However, motor drive systems using this structure may experience unstable bus voltage. To this end, this paper proposes an active damping control strategy based on virtual impedance. By modelling the electric drive system and conducting stability analysis, the cause of bus voltage resonance due to the use of small capacitors is revealed. Based on the extracted DC bus voltage harmonic signal, additional voltage vectors are added in the d-axis and q-axis voltage vectors, eliminating the impedance mismatch problem in the drive system caused by the reduction of bus capacitance, effectively suppressing the voltage oscillation on the machine side of the drive system. Simulation data shows that under the condition of using small-capacity ceramic capacitors, the method proposed in this paper achieves a harmonic suppression capability similar to that of large-capacity electrolytic capacitors, effectively ensuring the application safety of automotive drivers with electrolytic capacitorless architecture.

Flexible BTO piezoelectric generator fabricated by hydrothermal method with the assistance of lignocellulose and carbon nanomaterials

It is of great significance to develop piezoelectric composites with mechanical flexibility and high electromechanical coupling characteristics for the collection and conversion of mechanical energy. In this work, a barium titanate (BTO) based piezoelectric composite was prepared by hydrothermal synthesis and high-temperature carbonization with the assistance of cellulose nanofibers (CNF), graphene oxide (GO) and carboxylated carbon nanotubes (C-CNT). C-CNT, GO and CNF can provide growth sites for BTO, but compared with C-CNT, CNF and GO have stronger interaction with BTO, which can improve the compatibility between BTO and CNF/polyvinylidene fluoride (PVDF) matrix. The tensile strength of the composite membrane prepared by GO-CNF-BTO treated at 1100 °C can reach 23.36 ± 8.30 MPa. After further hot pressing and polarization treatment, its longitudinal piezoelectric coefficient (d33) reaches 9.8 ± 2.6 pC·N−1. Correspondingly, the open-circuit voltage (VOC) and short-circuit current (ISC) increases to 11.64 V and 824 nA, respectively. In addition, the assembled piezoelectric generator (PEG) can charge for small commercial capacitors, as well as light small bulbs and electronic screens. It also has good piezoelectric output stability and sensing performance, which can effectively convert the mechanical energy from human motion into electrical energy. This work provides a reference for the performance improvement of flexible piezoelectric devices.

A novel capacitive sensor interface based on a simple capacitance-to-phase converter

Abstract A novel room temperature capacitive sensor interface circuit is proposed and successfully tested, which uses a modified All-Pass filter architecture combined with a simple series resonant tank circuit with a moderate Q-factor. It is fashioned from a discrete inductor with small dissipation resonating with a grounded capacitor acting as the sensing element to obtain a resolution of ∆C ~ 2 zF in a capacitance range of 10 – 30 pF. The circuit converts the change in capacitance to the change in the phase of a carrier signal in a frequency range with a central frequency set up by the tank circuit’s resonant frequency and is configured to act as a close approximation of the ideal All-Pass filter. This cancels out the effects of amplitude modulation when the carrier signal is imperfectly tuned to the resonance. The proposed capacitive sensor interface has been specifically developed for use as a front-end constituent in ultra-precision mechanical displacement measurement systems, such as accelerometers, seismometers, gravimeters and gravity gradiometers, where moving plate grounded air gap capacitors are frequently used. Some other applications of the proposed circuit are possible including the measurement of the electric field, where the sensing capacitor depends on the applied electric field, and cost effective capacitive gas sensors. In addition, the circuit can be easily adapted to function with very small capacitance values (1 - 2 pF) as is typical in MEMS-based transducers.

Multilayer ceramic capacitor induced audible noise simulation

Multilayer ceramic capacitors (MLCCs) are one of the most widely used capacitors. Their small size, high capacitance, high reliability and low cost make them ideal for miniaturized electronic devices. However, their piezoelectric effect may cause the deformation of the capacitor associated with the applied voltage. Even worse, the deformation may cause the PCB vibration and potential noise radiation, which can be a problem for devices designed to be quiet, such as cellphones, earbuds, laptops, etc. This paper introduces how MLCCs can cause PCB vibration and noise radiation problems by simulating a single MLCC with piezoelectric effect. And then, a methodology is proposed on how to quantify the MLCC as vibration load source. Moreover, a simplified process is illustrated to simulate the MLCC induced noise radiated from circuit boards. Finally, a couple applications are demonstrated by using the developed process.

Beatless Control Strategy Based on Impedance Reshaping for PMSM Drives With Small DC-Link Capacitors

Beatless Control Strategy Based on Impedance Reshaping for PMSM Drives With Small DC-Link Capacitors

Improved Extended EMF-Based Sensorless Control for IPMSMs With Small DC-Link Capacitor Considering DC-Link Voltage Measurement Error

Improved Extended EMF-Based Sensorless Control for IPMSMs With Small DC-Link Capacitor Considering DC-Link Voltage Measurement Error

Research on high-resolution capacitance detection circuit based on T-type network

Abstract The capacitance detection circuit is a key component of the servo circuit of the quartz flexible accelerometer, which needs to ensure high-precision capacitance detection. The small capacitance change of the quartz flexible accelerometer pendulum will be affected by the noise of each device in the servo loop. To solve this problem, we design a single carrier modulation and demodulation capacitance detection circuit based on a T-type network from the capacitance detection model of a quartz flexible accelerometer. We established a circuit noise model, quantitatively analyzed the noise of the entire capacitance detection circuit from the theoretical level, and obtained the equivalent capacitance noise of the circuit. The rationality and effectiveness of the high-precision capacitance detection circuit are verified by theoretical calculation. We also verify the accuracy of the theoretical calculation through simulation and obtain the signal-to-noise ratio of the circuit. Finally, we prove that the scheme is a high-precision capacitance detection scheme.

Design and analysis of an interleaved step-up DC–DC converter with enhanced characteristics

In this paper, an interleaved DC–DC step-up converter with improved characteristics based on a voltage multiplier rectifier is presented. The proposed converter is presented and analyzed for two different operating duty regions including operating region 1 (0 < D ≤ 0.5), and operating region 2 (0.5 ≤ D < 1). This converter can be used in various applications such as energy storage, electric vehicles, and renewable energy systems. This converter is composed of two stages: an interleaved boost stage and a voltage multiplier rectifier stage, which collectively forms its general structure. The interleaved boost stage is a type of two-phase boost converter that transforms the input DC voltage into a high-frequency AC square waveform. This waveform can be readily filtered using smaller capacitors. The square-shaped voltage waveform from the interleaved boost stage is rectified and converted to a high DC voltage by the Voltage Multiplier Rectifier (VMR) stage. The operating regions, the evaluation of the steady-state condition, the voltage gain of the proposed converter's parasitic and ideal models as well as its losses and efficiency analysis have been evaluated. The proposed converter has an efficiency of 97% at the output power of 150 W. The proposed converter is simulated to convert a voltage of 25–159.5 V and to validate the mathematical relationships and simulation results, a laboratory prototype has been developed. The simulation and experimental results show the precision of the performance of the proposed interleaved boost converter.

Analytical study of Restricted Access Window with short slots for fast and reliable data delivery from energy-harvesting sensors

To address the peculiarities of various Internet of Things applications and improve the performance of Wi-Fi-based sensor stations, a recent Wi-Fi HaLow standard introduces a mechanism called Periodic Restricted Access Window (PRAW). PRAW allows mapping groups of stations to periodic time intervals during which only these stations can transmit while the others cannot. This approach reduces contention and saves energy. However, the standard does not provide any recommendations on how to select the PRAW parameters according to scenario-specific requirements, leaving room for the research. A typical IoT scenario considers low-intensity traffic and requires fast and reliable data delivery from energy-harvesting devices while using the channel efficiently: there shall be still time for transmissions of other stations in the network. This paper develops an analytical model of PRAW that evaluates the probability of delivering data in time from every sensor station that harvests energy, accumulates it in small capacitors, and, thus, may not have enough energy for multiple retries. The model allows selecting such parameters of PRAW that minimize the channel resource consumption of a Wi-Fi HaLow network, provided that the delay and energy requirements are satisfied.

Simulation of 2D ReS2/WSe2 based complementary field-effect transistors towards 1 nm technology node

Advanced Integrated Circuit technology demands high-performance channel materials and innovative device architectures to sustain the scaling of field-effect transistors. In this study, we simulate the electrical performance of rhenium disulfide and tungsten diselenide nanosheet FETs (NSFETs) with gate lengths ranging from 12 nm to 8 nm using Technology Computer-Aided Design method. The simulated high performance including 393 μA/μm on-state current and over 105 on/off ratio can meet the criteria for integrated circuit applications in the 1 nm technology node. Complementary FET (CFET) simulations are conducted through the vertical stacking of ReS2 and WSe2 NSFETs, exhibiting a small parasitic capacitance of 1.0 fF/μm, and notable noise margin (>235 mV) at different process corners. The construction and performance simulation of Static Random-Access Memory (SRAM) is realized through CFET interconnection, involving the calculation of read current and read/write noise margin. This research offers a forward-looking analysis of performance metrics for future 2D materials-based NSFETs, CFETs, and SRAMs.

Research on Fixed-Slope On-Chip Soft-Start Method Applied to Buck DC–DC Converter

A fixed-slope soft-start method applicable to Buck converters for on-chip integration is proposed to address the issue of varying power stresses (device voltage, current stress) during start-up with different output voltages. The main mechanism involves combining feedback coefficient sampling with a fixed-slope reference voltage to achieve a slow rise in the reference voltage by equating the soft-start charging current to a pulse current through the on-chip integration of a small capacitor. This allows for fixed-slope start-ups for different set output voltages. Spike elimination techniques are employed to address charging current spikes caused by pulse periods, enhancing precise control over the soft-start time. By replacing the traditional resistor divider network with a capacitive divider network in the soft-start method, DC power consumption is minimized. Upon completion of the soft start, a smooth transition to a steady-state operation occurs, with the automatic shutdown of the soft-start module reducing static power consumption. A specific circuit design and layout verification based on 0.18 μm high-voltage BCD technology demonstrates that the proposed method maintains a fixed-slope start-up of approximately 5 mV/μs within the chip’s output range of 0.9 V to 4 V, with a slope control accuracy of up to 98%. The soft-start circuit effectively eliminates surge currents generated during start-up under full load conditions of 3 A and no-load conditions of 0 A, reducing the overall surge current by 44% and enabling a stable voltage rise and the smooth transition to a steady-state operation.

Overvoltage Avoidance Control Strategy for Braking Process of Brushless DC Motor Drives with Small DC-Link Capacitance

Single-phase input rectifier brushless DC motor drives with a small film capacitor have many advantages, such as high power density and high reliability. However, when the motor system operates in regenerative braking mode, the dc-link capacitor with reduced capacitance may suffer from overvoltage without adding additional hardware circuits. At the same time, the braking torque control of the motor will be affected by speed variations. In order to ensure smooth and reliable operation of the motor system, an anti-overvoltage braking torque control method is proposed in this article. The relationship among the dc-link capacitance, the dc-link capacitor voltage, and the speed during regenerative braking is analyzed quantitatively, and the speed at which the regenerative braking is switched to the plug braking is obtained, which in turn consumes the capacitor energy to avoid dc-link overvoltage. Additionally, based on the relationship between the controllability of the braking torque and the speed, a reference value of the braking current that matches the speed is designed. The proposed method makes use of the capacitor’s energy storage during regenerative braking. Meanwhile, it mitigates the impact of motor speed on braking torque. Finally, the effectiveness of the proposed method is verified on a motor platform equipped with the dc-link film capacitor.

Conductive MXene/Polymer Composites for Transparent Flexible Supercapacitors.

Transparent flexible energy storage devices are limited by the trade-off among flexibility, transparency, and charge storage capability of their electrode materials. Conductive polymers are intrinsically flexible, but limited by small capacitance. Pseudocapacitive MXene provides high capacitance, yet their opaque and brittle nature hinders their flexibility and transparency. Herein, the development of synergistically interacting conductive polymer Ti3C2Tx MXene/PEDOT:PSS composites is reported for transparent flexible all-solid-state supercapacitors, with an outstanding areal capacitance of 3.1 mFcm-2, a high optical transparency of 61.6%, and excellent flexibility and durability. The high capacitance and high transparency of the devices stem from the uniform and thorough blending of PEDOT:PSS and Ti3C2Tx, which is associated with the formation of O─H…O H-bonds in the composites. The conductive MXene/polymer composite electrodes demonstrate a rational means to achieve high-capacity, transparent and flexible supercapacitors in an easy and scalable manner.