Slow Memory Research Articles

Multichannel adaptive deconvolution based on streaming prediction-error filter

Abstract Deconvolution mainly improves the resolution of seismic data by compressing seismic wavelets, which is of great significance in high-resolution processing of seismic data. Prediction-error filtering/least-square inverse filtering is widely used in seismic deconvolution and usually assumes that seismic data is stationary. Affected by factors such as earth filtering, actual seismic wavelets are time- and space-varying. Adaptive prediction-error filters are designed to effectively characterise the nonstationarity of seismic data by using iterative methods, however, it leads to problems such as slow calculation speed and high memory cost when dealing with large-scale data. We have proposed an adaptive deconvolution method based on a streaming prediction-error filter. Instead of using slow iterations, mathematical underdetermined problems with the new local smoothness constraints are analytically solved to predict time-varying seismic wavelets. To avoid the discontinuity of deconvolution results along the space axis, both time and space constraints are used to implement multichannel adaptive deconvolution. Meanwhile, we define the parameter of the time-varying prediction step that keeps the relative amplitude relationship among different reflections. The new deconvolution improves the resolution along the time direction while reducing the computational costs by a streaming computation, which is suitable for handling nonstationary large-scale data. Synthetic model and field data tests show that the proposed method can effectively improve the resolution of nonstationary seismic data, while maintaining the lateral continuity of seismic events. Furthermore, the relative amplitude relationship of different reflections is reasonably preserved.

Numerical approximations on the transient analysis of bioelectric phenomena at long time scales via the Mittag-Leffler function

• Fractional-order based model for long-tailed transient behavior of biological systems. • Approximations to achieve a “pseudo-steady-state” in non-ideal relaxation processes. • Analysis of rational functions, asymptotically equivalent to Mittag-Leffler pattern for long times. • Application to safe and efficacious protocols of stimulation and electrical characterization. This paper discusses the complexity of distributed relaxation processes in biological systems, particularly with regard to the slowest timescale phenomena that influence the modeling of physiological events. Specifically, our main interest is to determine the optimal excitation time at which the transient response , described in terms of relatively slow decays and memory effects, can be considered negligible. We estimate the time scale required for the Mittag-Leffler function to reach and stay within a range about the final value (dc “pseudo-steady state”). From numerical computations, we consider the problem of approximating holding times with common and rational (Padé-type) asymptotic approximations for comparative purposes. It is important to understand the physiological processes and to explore new mathematical models, based on efficient approximations, in order to design safe, controllable, and effective protocols for the electrical stimulation of excitable cells and the characterization of biological tissues.

Slow oscillation-spindle coupling is negatively associated with emotional memory formation following stress.

Both stress and sleep enhance emotional memory. They also interact, with the largest effect of sleep on emotional memory being seen when stress occurs shortly before or after encoding. Slow wave sleep (SWS) is critical for long-term episodic memory, facilitated by the temporal coupling of slow oscillations and sleep spindles. Prior work in humans has shown these associations for neutral information in non-stressed participants. Whether coupling interacts with stress to facilitate emotional memory formation is unknown. Here, we addressed this question by reanalyzing an existing dataset of 64 individuals. Participants underwent a psychosocial stressor (32) or comparable control (32) prior to the encoding of 150-line drawings of neutral, positive, and negative images. All participants slept overnight with polysomnography, before being given a surprise memory test the following day. In the stress group, time spent in SWS was positively correlated with memory for images of all valences. Results were driven by those who showed a high cortisol response to the stressor, compared to low responders. The amount of slow oscillation-spindle coupling during SWS was negatively associated with neutral and emotional memory in the stress group only. The association with emotional memory was significantly stronger than for neutral memory within the stress group. These results suggest that stress around the time of initial memory formation impacts the relationship between slow wave sleep and memory.

Nanobody-mediated control of gene expression and epigenetic memory

Targeting chromatin regulators to specific genomic locations for gene control is emerging as a powerful method in basic research and synthetic biology. However, many chromatin regulators are large, making them difficult to deliver and combine in mammalian cells. Here, we develop a strategy for gene control using small nanobodies that bind and recruit endogenous chromatin regulators to a gene. We show that an antiGFP nanobody can be used to simultaneously visualize GFP-tagged chromatin regulators and control gene expression, and that nanobodies against HP1 and DNMT1 can silence a reporter gene. Moreover, combining nanobodies together or with other regulators, such as DNMT3A or KRAB, can enhance silencing speed and epigenetic memory. Finally, we use the slow silencing speed and high memory of antiDNMT1 to build a signal duration timer and recorder. These results set the basis for using nanobodies against chromatin regulators for controlling gene expression and epigenetic memory.

Program package MPGOS: Challenges and solutions during the integration of a large number of independent ODE systems using GPUs

Challenges and efficient solution techniques during the integration of a large number of independent ordinary differential equations (ODEs) using the massively parallel architecture of graphics processing units (GPUs) are presented. One of the main difficulties is the minimisation of the memory transactions through the PCI-E bus between the host (CPU) and the device (GPU) required frequently, for instance, during the calculation of the Lyapunov exponent, winding number or maximum response diagram. The second difficulty is the minimisation of the slow global memory transactions and memory usage by exploiting the memory hierarchy of the GPU architecture. Finally, a good GPU solver has to treat the possible asynchronous features of the ODE systems efficiently; for instance, event detection occurring at distinct time instances or handling the orders of magnitude difference in the required number of time steps of the different ODE systems. The program package MPGOS (written in C++ and CUDA C software environments) can address the aforementioned issues easily via the addition of user-defined functions that must be implemented similarly to the right-hand side of the system; via the possibility of the definition of shared parameters common to all instances of the independent ODE systems; via user-programmable parameters to store only the desired properties of the trajectories; and via an easy was to overlap GPU and CPU computations. This paper focuses on the detailed description of the implementation strategies of the program package.

High-Resolution Spectral Sleep Analysis Reveals a Novel Association Between Slow Oscillations and Memory Retention in Elderly Adults.

Objective: In recognition of the mixed associations between traditionally scored slow wave sleep and memory, we sought to explore the relationships between slow wave sleep, electroencephalographic (EEG) power spectra during sleep and overnight verbal memory retention in older adults.Design, Setting, Participants, and Measurements: Participants were 101 adults without dementia (52% female, mean age 70.3 years). Delayed verbal memory was first tested in the evening prior to overnight polysomnography (PSG). The following morning, subjects were asked to recall as many items as possible from the same List (overnight memory retention; OMR). Partial correlation analyses examined the associations of delayed verbal memory and OMR with slow wave sleep (SWS) and two physiologic EEG slow wave activity (SWA) power spectral bands (0.5–1 Hz slow oscillations vs. 1–4 Hz delta activity).Results: In subjects displaying SWS, SWS was associated with enhanced delayed verbal memory, but not with OMR. Interestingly, among participants that did not show SWS, OMR was significantly associated with a higher slow oscillation relative power, during NREM sleep in the first ultradian cycle, with medium effect size.Conclusions: These findings suggest a complex relationship between SWS and memory and illustrate that even in the absence of scorable SWS, older adults demonstrate substantial slow wave activity. Further, these slow oscillations (0.5–1 Hz), in the first ultradian cycle, are positively associated with OMR, but only in those without SWS. Our findings raise the possibility that precise features of slow wave activity play key roles in maintaining memory function in healthy aging. Further, our results underscore that conventional methods of sleep evaluation may not be sufficiently sensitive to detect associations between SWA and memory in older adults.

Optimization of workpiece detection model based on channel pruning and fixed-point quantization

Abstract As the development of deep learning, the accuracy and speed of object detection tasks are constantly improved, and more and more neural network models meet the needs of object detection. Many network models provide a new possibility for workpiece detection in factory workshops. However, the existing object detection model has the problems of large parameters, slow running speed and high memory consumption, which makes it difficult to be applied to the actual workshop production scene. In order to solve the above problems, based on the research of network model compression and acceleration algorithm, this paper optimizes the classical mobile Mobilenet-yolov3 network by quantification and pruning, and makes experimental analysis and comparison with existing result. The experimental results show that using the same workpiece data set, the new model can get the same effect in F1 score and accuracy rate as the original model, and also slightly improve the recall rate. Compared with the original model, the computational complexity and model size and the Flops (forward inference speed) are greatly reduced.

August

August Ryler Dustin (bio) The season wears a windless dirt road shoulder, a crop of lilies, fields as burnished brown as beach glass, bright beyond the stony odor of sidewalks wet from sprinklers. August: now and always never, deeper, best believerin the lastingness of bees, and boyhood, rust-colored crickets, wet retrievers, teachers working in their rented rooms of plywood. A warbler croons. All afternoon, my dreams keep shimmering with heat from vanished days, slow memories attached to faded scenes— the wavy haze of dust a truck has made before a church's old, unchanged marquee, a bench, a broken van, a dogwood tree. [End Page 96] Ryler Dustin ryler dustin is the author of Heavy Lead Birdsong. His poems appear in outlets like Verse Daily, Colorado Review, Gulf Coast, and the Best of Iron Horse Literary Review. Raised in the Pacific Northwest, he has represented Seattle on the final stage of the Individual World Poetry Slam.* Copyright © 2021 University of North Carolina Wilmington

Reinforcement regulates timing variability in thalamus

Learning reduces variability but variability can facilitate learning. This paradoxical relationship has made it challenging to tease apart sources of variability that degrade performance from those that improve it. We tackled this question in a context-dependent timing task requiring humans and monkeys to flexibly produce different time intervals with different effectors. We identified two opposing factors contributing to timing variability: slow memory fluctuation that degrades performance and reward-dependent exploratory behavior that improves performance. Signatures of these opposing factors were evident across populations of neurons in the dorsomedial frontal cortex (DMFC), DMFC-projecting neurons in the ventrolateral thalamus, and putative target of DMFC in the caudate. However, only in the thalamus were the performance-optimizing regulation of variability aligned to the slow performance-degrading memory fluctuations. These findings reveal how variability caused by exploratory behavior might help to mitigate other undesirable sources of variability and highlight a potential role for thalamocortical projections in this process.

Coordination of hippocampal theta and gamma oscillations relative to spatial active avoidance reflects cognitive outcome after febrile status epilepticus.

Cognitive deficits may arise from a variety of genetic alterations and neurological insults that impair neural coding mechanisms and the routing of neural information underpinning learning and memory. Slow and medium gamma oscillations underpin memory recall and sensorimotor processing and represent dynamic inputs at CA1 synapses. Febrile status epilepticus (FSE) can lead to increased risk for temporal lobe epilepsy and enduring cognitive impairments. In a rodent model, we assessed how FSE alters hippocampal CA1 signals relative to spatial task performance and serve as a readout of synaptic input efficacy. The power of theta (5-12 Hz), slow gamma (30-50 Hz), and medium gamma (70-90 Hz) differentially interact with respect to cognitive demands during active avoidance behavior on a rotating arena. Successful avoidance was characterized by slow gamma that was largest several seconds before or after peak acceleration. Peak acceleration coincides with peak theta oscillations, followed within approximately 1 s by peak medium gamma. FSE animals showing impairment in the task maintained the profiles of theta and medium gamma associated with increased sensorimotor processing following peak acceleration but did not exhibit the same slow gamma profile associated with epochs of memory retrieval. While CA1 synapses from entorhinal cortex were functionally unaffected by FSE, communication via synapses from CA3 may have been impaired, leading to both temporal discoordination and poor memory retrieval. These findings demonstrate theta/gamma profiles can serve as both physiological biomarkers for memory retrieval or encoding deficits and synapse level treatment targets that could attenuate cognitive comorbidities associated with early life seizures. (PsycInfo Database Record (c) 2021 APA, all rights reserved).

Adaptive Page Migration Policy With Huge Pages in Tiered Memory Systems

To accommodate the growing demand for memory capacity in a cost-effective way, multiple types of memory are incorporated in a single system. In such tiered memory systems consisting of small fast and large slow memory components, accurately identifying the performance importance of pages is critical to properly migrate hot pages to fast memory. Meanwhile, growing address translation cost due to the increasing memory footprints, helped adopting huge pages in common systems. Although such page hotness identification problems have existed for a long time, this article revisits the problem in the new context of tiered memory systems and huge pages. This article first investigates the memory locality behaviors of applications with three potential migration polices, least-recently-used (LRU), least-frequently-used (LFU), and random with huge pages. The evaluation shows that none of the three migration policies excel the others, as the effectiveness of each policy depends on application behaviors. In addition, the results show huge pages can be effective even with page migration, if a proper migration policy is used. Based on the observation, this paper proposes a novel dynamic policy selection mechanism, which identifies the best migration policy for a given workload. It allows multiple concurrently running workloads to adopt different policies. To find the optimal one for each workload, this study first identifies key features that must be inferred from limited approximate memory access information collected using accessed bits in page tables. In addition, it proposes a parallel emulation of alternative policies to assess the benefit of possible alternatives. The proposed dynamic policy selection can achieve 23.8percent performance improvement compared to a prior approximate mechanism based on LRU lists in Linux systems.

Ferroelectric memory: state-of-the-art manufacturing and research

Semiconductor industry calls for emerging memory, demonstrating high speed (like SRAM or DRAM), nonvolatility (like Flash NAND), high endurance and density, good scalability, reduced energy consumption and reasonable cost. Ferroelectric memory FRAM has been considered as one of the emerging memory technologies for over 20 years. FRAM uses polarization switching that provides low power consumption, nonvolatility, high speed and endurance, robust data retention, and resistance to data corruption via electric, magnetic fields and radiation. Despite the advantages, market share held by FRAM manufacturers is insignificant due to scaling challenges. State-of-the-art FRAM manufacturing is studied in this paper. Ferroelectric capacitors and memory cells made by main commercial FRAM manufactures (Texas Instruments, Cypress Semiconductor, Fujitsu и Lapis Semiconductor) are explored. All memory cells are based on the lead zirconate titanate PZT capacitor with the thickness of about 70 nm and IrOx/Ir or Pt electrodes. The leading FRAM technology remains the 130 nm node CMOS process developed at Texas Instruments fabs. New approaches to further scaling and new devices based on ferroelectrics are reviewed, including binary ferroelectrics deposited by ALD techniques, piezoelectronic transistors, ferroelectric/2D-semiconductor transistor structures, and others. Whether FRAM technology will be able to resolve one of the main contradictions between a high-speed processor and a relatively slow nonvolatile memory depends on the success of the new technologies integration.

Neural correlates of error detection during complex response selection: Introduction of a novel eight-alternative response task

Error processing in complex decision tasks should be more difficult compared to a simple and commonly used two-choice task. We developed an eight-alternative response task (8ART), which allowed us to investigate different aspects of error detection. We analysed event-related potentials (ERP; N = 30). Interestingly, the response time moderated several findings. For example, only for fast responses, we observed the well-known effect of larger error negativity (Ne) in signalled and non-signalled errors compared to correct responses, but not for slow responses. We identified at least two different error sources due to post-experimental reports and certainty ratings: impulsive (fast) errors and (slow) memory errors. Interestingly, the participants were able to perform the task and to identify both, impulsive and memory errors successfully. Preliminary evidence indicated that early (Ne-related) error processing was not sensitive to memory errors but to impulsive errors, whereas the error positivity seemed to be sensitive to both error types.

Optimal Data Placement for Heterogeneous Cache, Memory, and Storage Systems

New memory technologies are blurring the previously distinctive performance characteristics of adjacent layers in the memory hierarchy. No longer are such layers orders of magnitude different in request latency or capacity. Beyond the traditional single-layer view of caching, we now must re-cast the problem as a data placement challenge: which data should be cached in faster memory if it could instead be served directly from slower memory? We present Chopt, an offline algorithm for data placement across multiple tiers of memory with asymmetric read and write costs. We show that Chopt is optimal and can therefore serve as the upper bound of performance gain for any data placement algorithm. We also demonstrate an approximation of Chopt which makes its execution time for long traces practical using spatial sampling of requests incurring a small 0.2% average error on representative workloads at a sampling ratio of 1%. Our evaluation of Chopt on more than 30 production traces and benchmarks shows that optimal data placement decisions could improve average request latency by 8.2%-44.8% when compared with the long-established gold standard: Belady and Mattson's offline, evict-farthest-in-the-future optimal algorithms. Our results identify substantial improvement opportunities for future online memory management research.

A Study of Memory Placement on Hardware-Assisted Tiered Memory Systems

Recent advances in memory technology, memory hierarchy is becoming diverse with performance-differentiated memory such as high bandwidth memory (HBM) and non-volatile memory (NVM) in modern computer systems. However, the current memory placement has been designed with the assumption that all the memory has the same capabilities based on DRAM. In this letter, we analyze memory placement schemes in state-of-the-art Linux systems to the hardware-assisted tiered memory system. Our analysis is conducted on the real system equipped with Intel's Optane Persistent Memory, enabling tiered memory with DRAM (fast) and Optane (slow) memory. We observe that tiered memory augmented on traditional NUMA form do not exhibit that accessing the local memory provides better performance than that of the remote memory because local Optane memory is slower than remote DRAM. Due to this distinct characteristic, there are several inefficiencies in the commodity operating systems. To make use of tiered memory systems efficiently, this paper explores the design space of practical software solutions, which can be currently applicable in the Linux system.

Addressing variability in reuse prediction for last-level caches

Last-Level Cache (LLC) represents the bulk of a modern CPU processor's transistor budget and is essential for application performance as LLC enables fast access to data in contrast to much slower main memory. However, applications with large working set size often exhibit streaming and/or thrashing access patterns at LLC. As a result, a large fraction of the LLC capacity is occupied by dead blocks that will not be referenced again, leading to inefficient utilization of the LLC capacity. To improve cache efficiency, the state-of-the-art cache management techniques employ prediction mechanisms that learn from the past access patterns with an aim to accurately identify as many dead blocks as possible. Once identified, dead blocks are evicted from LLC to make space for potentially high reuse cache blocks. In this thesis, we identify variability in the reuse behavior of cache blocks as the key limiting factor in maximizing cache efficiency for state-of-the-art predictive techniques. Variability in reuse prediction is inevitable due to numerous factors that are outside the control of LLC. The sources of variability include control-flow variation, speculative execution and contention from cores sharing the cache, among others. Variability in reuse prediction challenges existing techniques in reliably identifying the end of a block's useful lifetime, thus causing lower prediction accuracy, coverage, or both. To address this challenge, this thesis aims to design robust cache management mechanisms and policies for LLC in the face of variability in reuse prediction to minimize cache misses, while keeping the cost and complexity of the hardware implementation low. To that end, we propose two cache management techniques, one domain-agnostic and one domain-specialized, to improve cache efficiency by addressing variability in reuse prediction.

Optimal Data Placement for Heterogeneous Cache, Memory, and Storage Systems

New memory technologies are blurring the previously distinctive performance characteristics of adjacent layers in the memory hierarchy. No longer are such layers orders of magnitude different in request latency or capacity. Beyond the traditional single-layer view of caching, we now must re-cast the problem as a data placement challenge: which data should be cached in faster memory if it could instead be served directly from slower memory? We present CHOPT, an offline algorithm for data placement across multiple tiers of memory with asymmetric read and write costs. We show that CHOPT is optimal and can therefore serve as the upper bound of performance gain for any data placement algorithm. We also demonstrate an approximation of CHOPT which makes its execution time for long traces practical using spatial sampling of requests incurring a small 0.2% average error on representative workloads at a sampling ratio of 1%. Our evaluation of CHOPT on more than 30 production traces and benchmarks shows that optimal data placement decisions could improve average request latency by 8.2%-44.8% when compared with the long-established gold standard: Belady and Mattson's offline, evict-farthest-in-the-future optimal algorithms. Our results identify substantial improvement opportunities for future online memory management research.

Joint Management of CPU and NVDIMM for Breaking Down the Great Memory Wall

To provide larger memory space with lower costs, NVDIMM is a production-ready device. However, directly placing NVDIMM as the main memory would seriously degrade the system performance because of the “great memory wall” caused by the fact that in NVDIMM, the slow memory (e.g., flash memory) is several orders of magnitude slower than the fast memory (e.g., DRAM). In this article, we present a joint management framework of host/CPU and NVDIMM to break down the great memory wall by bridging the process information gap between host/CPU and NVDIMM. In this framework, a page semantic-aware strategy is proposed to precisely predict, mark, and relocate data or memory pages to the fast memory in advance by exploiting the process access patterns, so that the frequency of the slow memory accesses can be further reduced. The proposed framework with the proposed strategy was evaluated with several well-known benchmarks and the results are encouraging.

ABOUT OPTIMAL MANAGEMENT OF WORK-STEALING DEQUES IN TWO-LEVEL MEMORY

In the parallel work-stealing load balancers, each core owns a personal buffer of tasks called deque. One end of the deque is used by its owner to add and retrieve tasks, while the second end is used by other cores to steal tasks. Our experience in software implementations has shown that it is important to optimize work with cache memory in parallel work-stealing load balancers. For example, by modifying deques so that they can hold task objects instead of pointers, we managed to increase the performance more than 2.5 times on the CPU-bound applications and decrease last-level cache misses up to 30 % compared to Intel TBB (Threading Building Blocks) and Intel / MIT (Massachusetts Institute of Technology) Cilk work-stealing schedulers. Therefore, it is important to investigate special methods of working with deques in two-level memory, and not just try to optimize the use of universal cache implementations. The paper analyzes the problem of optimal control of a work-stealing deque in two-level memory (for example, registers – random access memory), where probabilities of parallel operations with the deque are known. The classic sequential cyclic method for representing a deque in memory is considered. If a deque overflows or empty, we transfer elements from its middle part from the fast memory to the slow memory, since data from the end parts of the deque may be needed earlier. The problem is to find the optimal number of elements from both sides of the deque to leave in the fast memory if the deque is full or empty. The average time to get into the states when it is necessary to reallocate the memory is maximized.The simulation model and the mathematical model in the form of an absorbing Markov chain were constructed. The results of numerical experiments are presented.

Does Acoustic Stimulation During Sleep Boost Slow Wave Sleep and Memory Performance?

Does Acoustic Stimulation During Sleep Boost Slow Wave Sleep and Memory Performance?