Slope Compensation Research Articles

Research on Shape Signal Smoothing Processing of Cold Rolling Strip

In the process of measuring the shape of the cold rolling strip, by combining proportion compensation with slope compensation, the signal error of edge shape should be compensated reasonably. In addition, corresponding solutions are proposed to solve the channel signal loss or the discontinuous transverse shape value which takes place occasionally in the shape measuring roller. These solutions could improve the stability of shape measuring signal, avoid serious accidents of controlling mill caused by abnormal shape signals and achieve reliable shape control without worries

An Adaptive Slope Compensation Circuit and its Application

An Adaptive Slope Compensation Circuit and its Application

A wide load range, multi-mode synchronous buck DC—DC converter with a dynamic mode controller and adaptive slope compensation

A synchronous buck DC—DC converter with an adaptive multi-mode controller is proposed. In order to achieve high efficiency over its entire load range, pulse-width modulation (PWM), pulse-skip modulation (PSM) and pulse-frequency modulation (PFM) modes were integrated in the proposed DC—DC converter. With a highly accurate current sensor and a dynamic mode controller on chip, the converter can dynamically change among PWM, PSM and PFM control according to the load requirements. In addition, to avoid power device damage caused by inrush current at the start up state, a soft-start circuit is presented to suppress the inrush current. Furthermore, an adaptive slope compensation (SC) technique is proposed to stabilize the current programmed PWM controller for duty cycle passes over 50%, and improve the degraded load capability due to traditional slope compensation. The buck converter chip was simulated and manufactured under a 0.35 μm standard CMOS process. Experimental results show that the chip can achieve 79% to 91% efficiency over the load range of 0.1 to 1000 mA

Register Control of Roll-to-Roll Printing System Based on Statistical Approach

One of the most important requirements when using roll-to-roll printing equipment for multilayer printing is register control. Because multilayer printing requires a printing accuracy of several microns to several tens of microns, depending on the devices and their sizes, precise register control is required. In general, the register errors vary with time, even for one revolution of the plate cylinder. Therefore, more information about the register errors in one revolution of the plate cylinder is required for more precise register control, which is achieved by using multiple register marks in a single revolution of the plate cylinder. By using a larger number of register marks, we can define the value of the register error as a statistical value rather than a single one. The register errors measured from an actual roll-to-roll printing system consist of a linearly varying term, a static offset term, and small fluctuations. The register errors resulting from the linearly varying term and the offset term are compensated for by the velocity and phase control of the plate cylinders, based on the calculated slope and offset of the register errors, which are obtained by the curve-fitting of the data set of register errors. We show that even with the slope and offset compensation of the register errors, a register control performance of within 20 µm can be achieved.

160 Gbit/s-300 km single-channel transmission in the 11 μm band with a precise GVD and slope compensation

We report a 160 Gbit/s single-channel OTDM transmission in the 1.1 μm band using a high-Δ single-mode step-index fiber (SIF) and ytterbium-doped fiber amplifiers (YDFAs). The 160 Gbit/s OTDM signal was generated from a 10 GHz mode-locked Yb fiber laser. The dispersion and dispersion slope of the SIF were precisely compensated with a chirped fiber Bragg grating (FBG) and a pre-chirping technique, respectively. A nonlinear optical loop mirror (NOLM) was employed to demultiplex the 160 Gbit/s OTDM signal to 10 Gbit/s. As a result, we achieved a 100 km transmission with a BER of < 10⁻⁹ and a 300 km transmission with a BER of < 10⁻³, which is below the standard FEC limit at a net bit rate of 149.5 Gbit/s taking the 7% FEC overhead into account.

Broadband dispersion compensation of conventional single mode fibers using microstructure optical fibers

This paper presents a microstructure optical fiber for dispersion compensation in a wide range of wavelengths. The finite-element method with perfectly matched absorbing layers boundary condition is used to investigate the guiding properties. The designed novel dispersion compensating fiber shows that it is possible to obtain a larger negative dispersion coefficient of about −130 to −360ps/(nmkm), better dispersion slope compensation, better compensation ratio, and lower confinement losses less than 10−2dB/km in the entire telecommunication (1400–1600nm) band by using a modest number of design parameters and very simple cladding design.

Design of a Step-down DC-DC Converter ASIC Applied to Portable Electronic Products

Using CSMC 0.5μm process model, a Step-Down DC-DC converter ASIC applied to portable electronic products was designed. The peak current-mode control PWM with slope compensation was adopted in the power management chip to improve the dynamic response speed of the system; the error amplifier and PWM comparator was redesigned to improve the response speed and stability of the chip; the over-current protection function was included in the peak current sampling circuit; in addition, the circuit with the pulse-skipping mode reduce the battery energy loss. Capable of delivering 600mA Output Current over a wide input voltage range from 3.1 to 5.5V, the ASIC, that has a fixed operation frequency of 800kHz and 95% conversion efficiency, is ideally suited for portable electronic products. No external Schottky diode is required in practical application.

S+C+L波段色散斜率补偿光子准晶体光纤

针对光纤通信中的色散补偿,尤其是密集波分复用系统的多信道同时补偿的需求,提出了一种用于宽带色散斜率补偿的光子准晶体光纤.该光纤结构包层空气孔为准晶体排列,并且在纤芯引入了中心缺陷.通过对光纤特性的数值分析表明,在1 460-1 625 nm的光通信波段,该结构光纤的相对色散斜率为0.004 4-0.002 9 nm^-1,相对色散斜率与标准单模光纤近似相等,且负色散值达-2 476 ps·nm^-1·km^-1.对标准单模光纤进行色散补偿后,在S＋C＋L波段色散值为（-0.5-0）ps·nm^-1·km^-1.该光纤可用于对当前光纤通信系统进行宽带色散补偿,实现多信道同时补偿,简化结构,并降低补偿成本.

Design of a switching frequency adaptive slope compensation circuit for frequency synchronous DC–DC converters

The inductor value of the frequency synchronous DC–DC converter is related to the operating switching frequency. In order to optimize the performance of stability, transient response and load capability, this paper presents a switching frequency adaptive slope compensation circuit. The circuit adjusts the slope compensation by automatic operation according to the synchronized switching frequency to avoid excessive compensation. The proposed circuit has been implemented in a high voltage buck DC–DC converter with 0.6μm CDMOS process. The test results indicate that fast transient response and load capability are realized and the stability is achieved without sub-harmonic oscillation in the whole synchronous frequency range. Graphical abstract [Display omitted] Highlights► A frequency adaptive slope compensation circuit is proposed. ► The slope compensation adjusts with the synchronized switching frequency. ► Avoids excessive compensation and sub-harmonic oscillation. ► The circuit is implemented and verified in a frequency synchronous DC–DC converter.► Transient response and load capability have well performance in the frequency range.

Design of Broadband Dispersion Compensating Photonic Crystal Fiber

This paper presents a triangular-lattice photonic crystal fiber for broadband dispersion compensation. The finite element method with perfectly matched absorbing layers boundary condition is used to investigate the guiding properties. The designed dispersion compensating fiber shows that it is possible to obtain a larger negative dispersion coefficient of ?360 ps/(nm.km) at 1.55 ?m, better dispersion slope compensation, better compensation ratio in the entire telecommunication (1460-1640 nm) band by using a modest number of design parameters and very simple cladding design.

Microcontroller-Based Peak Current Mode Control Using Digital Slope Compensation

Microcontroller-based peak current mode control of a buck converter is investigated. The new solution uses a discrete time controller with digital slope compensation. This is implemented using only a single-chip microcontroller to achieve desirable cycle-by-cycle peak current limiting. The digital controller is implemented as a two-pole, two-zero linear difference equation designed using a continuous time model of the buck converter and a discrete time transform. Subharmonic oscillations are removed with digital slope compensation using a discrete staircase ramp. A 16 W hardware implementation directly compares analog and digital control. Frequency response measurements are taken and it is shown that the crossover frequency and expected phase margin of the digital control system match that of its analog counterpart.

Sampled-Data Analysis of the Dual-Interleaved Boost Converter With Interphase Transformer

By exploiting the half-cycle symmetry in the waveforms of the dual-interleaved boost converter, a small-signal, sampled-data model is developed, which includes the differential inductance of the interphase transformer and a peak current-mode controller. The model is validated by Saber simulation and experimental results from a 10-kW prototype. Significant differences are seen in the dynamic characteristics between the two operating modes: duty ratio D ≤ 0.5 or D >; 0.5. For D ≤ 0.5, slope compensation is needed to prevent subharmonic instability over an increasing range of D when the inductance ratio of interphase transformer and input inductor increases beyond 4.0. Furthermore, with D ≤ 0.5 the control-to-output transfer function becomes sensitive to the inductance ratio, whereas it is not when D >; 0.5. Also for D >; 0.5, the range of duty ratio over which slope compensation is needed reduces as the inductance ratio is increased.

Control of fast-scale bifurcation in single-phase SPWM inverter and its stability analysis

H bridge inverter is a basic nonlinear topology in power electronic circuits. However it is prone to the generation of fast-scale instability phenomenon due to the variation of some parameters in the operation process, which can be eliminated with the slope compensation simply and effectively. Experience plays the leading role and common engineering design is lacking in necessary design criteria. Accrording to the bifurcation control theory of nonlinear system, in this paper we analyze the implementation of slope compensation on H bridge inverter under peak current mode control in detail, thereby obtaining the accurate amplitude requirements of the compensated slope signal and realize the optimization. The results of the analysis are consistent with those of simulation experiment, and the inverter circuit under appropriate slope compensation can operate in stable regime especially with the performances being enhanced remarkably. The research method is also applicable for the stability analysis of other power electronic circuits.

Practical application of valley current mode control in a flyback converter with a large duty cycle

This study proposes the application of valley current mode (VCM) control in a flyback dc–dc converter with a large duty cycle. The use of VCM control eliminates the need of slope compensation in operation under a duty cycle greater than 50%. For operation with duty cycle near the boundary value (50%), a relatively small compensation ramp is required comparing with that of the conventional peak current mode (PCM) control. Moreover, the noise sensitivity issue of PCM control is also addressed by the change of the current sensing position in VCM and hence the immunity against the current spike. The VCM-controlled flyback converter achieves consistent steady-state and transient-response performances as its PCM-controlled counterpart. Stability analyses of inner current loop and overall closed-loop system are presented. Experiments are also conducted to evaluate the effectiveness of VCM control in controlling the flyback dc–dc converter.

斜坡补偿电路在峰值电流控制模式中的应用

斜坡补偿电路在峰值电流控制模式中的应用

Control of chaos in positive output Luo converter using slope compensation method

This paper illustrates the control of chaotic behaviour in positive output Luo converter by slope compensation method. Bifurcation analysis is carried out in the discrete domain for a current controlled Luo converter operating in the continuous conduction mode. As the reference current is varied, periodic 1 orbit undergoes a flip bifurcation, periodic doubling and finally enters into chaotic regime. Variable ramp compensation technique is proposed to dynamically adjust the slope of the inductor current such that the upper bound of Iref is increased thereby widening the operating range. An iterative function that describes the dynamics of the inductor current with and without variable ramp compensation and the equivalent criteria for bifurcation-free operation is derived. A computer simulation using MATLAB/Simulink confirms the predicted bifurcations. The simulated results are validated through hardware implementation.

A Current-Mode Buck DC-DC Converter with Frequency Characteristics Independent of Input and Output Voltages Using a Quadratic Compensation Slope

By using a quadratic compensation slope, a CMOS current-mode buck DC-DC converter with constant frequency characteristics over wide input and output voltage ranges has been developed. The use of a quadratic slope instead of a conventional linear slope makes both the damping factor in the transfer function and the frequency bandwidth of the current feedback loop independent of the converter's output voltage settings. When the coefficient of the quadratic slope is chosen to be dependent on the input voltage settings, the damping factor in the transfer function and the frequency bandwidth of the current feedback loop both become independent of the input voltage settings. Thus, both the input and output voltage dependences in the current feedback loop are eliminated, the frequency characteristics become constant, and the frequency bandwidth is maximized. To verify the effectiveness of a quadratic compensation slope with a coefficient that is dependent on the input voltage in a buck DC-DC converter, we fabricated a test chip using a 0.18µm high-voltage CMOS process. The evaluation results show that the frequency characteristics of both the total feedback loop and the current feedback loop are constant even when the input and output voltages are changed from 2.5V to 7V and from 0.5V to 5.6V, respectively, using a 3MHz clock.

Analysis of the Stability of Current Mode PWM DC/DC Converter

To address the poor Stability of current mode PWM DC / DC converter when duty cycle [5] is greater than 50%, by analyzing the converter, the design.of appropriate slope compensation circuit is given. And by Comparing the experimental waveform through simulation, it can effectively solve the converter poor stability and interference.of noise, if the slope compensation is appropriate.

A new fast‐response buck converter using accelerated pulse‐width‐modulation techniques

SUMMARYA new fast‐response buck converter using accelerated pulse‐width‐modulation techniques is proposed in this article. The benefits of the accelerated pulse‐width‐modulation technique is fast‐transient response, simple‐compensation design, and no requirement for slope compensation; furthermore, some power management problems are minimized, such as EMI (Electro Magnetic Interference), size, design complexity, and cost. The traditional voltage‐mode speed is slower with the transient response, so an accelerated pulse‐width‐modulation technique is used to solve the problem of slowed transient response in this article. The proposed buck converter has excellent conversion efficiency with a wide load conditions. The proposed buck converter has been fabricated with TSMC 0.35 µm CMOS 2P4M processes, and the total chip area is 1.32 × 1.22 mm2. Maximum output current is 300 mA when the output voltage equals 1.8 V. When the supply voltage is 3.6 V, the output voltage can be 1–2.6 V. Maximum transient response is less than 5 µs. The simulation and experimental results are presented in this article. Copyright © 2011 John Wiley &amp; Sons, Ltd.

An Adaptive Slope Compensation for the Single-Stage Inverter With Peak Current-Mode Control

This letter develops a mathematical model of the slope compensation for a single-stage inverter with peak current-mode control. The model proves that the single-stage inverter with peak current-mode control will be unconditionally stable only if a slope compensation equal or greater than half the slope rate of the inductor current downslope is applied. Thus, the slope compensation requirements for a conventional dc-dc converter and a single-stage inverter with peak current-mode control are the same. A simulation model has been developed to prove this mathematical model is valid. A frequency-domain analysis of the single-stage inverter shows that the unified slope compensation will degrade the loop gain at lower input voltages. An adaptive slope compensation is proposed to keep the loop gain of the single-stage inverter nearly constant at all the duty cycles. A practical design is also proposed.