Slew Rate Control Research Articles

A Cost-Efficient Active Gate Driver for Seamless Slew Rate Control of SiC MOSFETs

A Cost-Efficient Active Gate Driver for Seamless Slew Rate Control of SiC MOSFETs

A 12V-to-1V Outphase-Interleaved SC Hybrid Converter With Enhanced Inductor De-Energizing Slew Rate and Adaptive Deadtime Control

A 12V-to-1V Outphase-Interleaved SC Hybrid Converter With Enhanced Inductor De-Energizing Slew Rate and Adaptive Deadtime Control

Slew rate control of switching transient for SiC MOSFET in boost converter using digital active gate driver

This paper experimentally validates a fully digitalized active gate driver for suppressing the switching surge voltage of SiC MOSFETs in a boost converter. High-voltage power conversion systems are expected to adopt SiC unipolar power devices utilizing their high-speed switching capability. The high-speed switching operation causes the switching surge voltage in its switching transient. Active gate driving is a key technology for suppressing it. A fully digitalized active gate driver is particularly focused upon, which freely shaped the output gate-source voltage waveform by a multi-bit gate control signal. This driver achieves the dynamical control of the voltage/current behaviours of MOSFET in the switching transient by taking the Miller effect into account. It contributes to suppressing the switching surge voltage. This paper applies this digital active gate driver to a high voltage power conversion circuit. The switching surge voltage is experimentally suppressed by slew rate control with the digital active gate driver for various operating conditions. The results clarify the control strategy of the digital active gate driver for SiC MOSFET in a power conversion circuit.

Leader‐following consensus control of second‐order nonlinear multi‐agent systems with applications to slew rate control

AbstractThis paper addresses the distributed leader‐following consensus control of second‐order strict‐feedback nonlinear multi‐agent systems. By employing mean value theorem, variable separation technique, and backstepping methodology, a fully distributed adaptive control law is designed using only local relative state information. The proposed control law solves the leader‐following consensus problem for any directed communication graph that contains a spanning tree with the root node being the leader agent. The application to hovercraft slew rate control system is given to verify the effectiveness of the theoretical results.

Inverse Optimal Control of a Class of Nonlinear Multi-Agent Systems With Applications to Ship Slew Rate Control

Abstract This paper deals with the inverse optimal leader-following consensus problem of a class of high-order nonlinear multi-agent systems in strict-feedback form under directed communication topology. By employing the backstepping methodology and introducing an integral type Lyapunov function, a nonlinear distributed control law is constructed using the relative information between neighboring agents. The proposed control law solves the inverse optimal leader-following consensus problem under directed communication graph that contains a spanning tree with the root node being the leader agent. A practical example of ship slew rate control system is given to verify the effectiveness of the theoretical results.

Lossless Snubber for GaN-Based Flyback Converter With Common Mode Noise Consideration

The previous lossless snubber for flyback converters, although with a small number of components, simple control and high power conversion efficiency, has no consideration for electromagnetic interference (EMI). This paper proposes a lossless snubber converter with a novel drain voltage rising slew rate control for the main switch of the flyback converter. Compared to traditional topologies, the proposed snubber topology has two advantages: first, only an additional inductor is used. Second, the proposed method can reduce EMI emissions significantly. Finally, a prototype of the proposed snubber is built and verified with two existing similar snubbers.

High-speed Clock and Data Recovery System with Segmented Slew-rate Control Circuit for High-linearity in 65 nm CMOS Process

High-speed Clock and Data Recovery System with Segmented Slew-rate Control Circuit for High-linearity in 65 nm CMOS Process

A 1-A 6-MHz Digitally Assisted Buck–Boost Converter With Seamless Mode Transitions and Fast Dynamic Performance for Mobile Devices

A 1-A 6-MHz buck-boost converter with seamless mode transitions and fast dynamic operation is proposed for extending the useable voltage range of Li-ion batteries in mobile devices, and thereby their battery life. The proposed converter employs a proportional-integral peak-current-mode pulsewidth modulation controller with a digital adaptive slew-rate control scheme that minimizes output undershoots, overshoots, and settling time during mode transitions and dynamic events, such as load and output voltage steps. Additionally, hysteretic mode detection is proposed to prevent falsely triggering the converter to transition between the various operation modes (i.e., buck, boost, and buck-boost) and negatively impacting the performance of the circuit loads. The converter is fabricated in 0.13-μm CMOS technology, and supports 2.3-5 V input and 1.5-3.6 V output. The converter achieves 91.7% peak efficiency and over 80% efficiency at 1-mA load across all conditions. The output voltage ripple is less than 10 mV with a 220-nH inductor and a 10-μF output capacitor.

A Review of Switching Slew Rate Control for Silicon Carbide Devices Using Active Gate Drivers

Driving solutions for power semiconductor devices are experiencing new challenges since the emerging wide bandgap power devices, such as silicon carbide (SiC), with superior performance become commercially available. Generally, high switching speed is desired due to the lower switching loss, yet high dv/dt and di/dt can result in elevated electromagnetic interference (EMI) emission, false-triggering, and other detrimental effects during switching transients. Active gate drivers (AGDs) have been proposed to balance the switching losses and the switching speed of each switching transient. The review of the in-existence AGD methodologies for SiC devices has not been reported yet. This review starts with the essence of the slew rate control and its significance. Then, a comprehensive review categorizing the state-of-the-art AGD methodologies is presented. It is followed by a summary of the AGDs control and timing strategies. In this work, using AGD to reduce the EMI noise of a 10-kV SiC MOSFET system is reported. This work also highlights other capabilities of AGDs, including reliability enhancement of power devices and rebalancing the mismatched electrical parameters of parallel- and series-connected devices. These application scenarios of AGDs are validated via simulation and experimental results.

A BMC Analog and Digital PHY for USB Type-C Power Delivery

A Type-C biphase mark code (BMC) transceiver in 0.14- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology is presented. The analog PHY in combination with digital PHY supports BMC data for USB power delivery (PD) negotiations through a Type-C cable. It compensates for signal-level loss and duty cycle distortion due to ground shifting at both ends of a Type-C cable. Analog receiver includes a BMC squelch detector decision-making comparators and a duty cycle correction circuit. Analog transmitter includes a slew rate control circuit, level shifter, and linear line driver. Digital PHY makes more corrections on duty cycle in the receiver side, recovers bits and symbols from the asynchronous serial data, and sends BMC coded data to the transmitter. The connector-facing high-voltage pins to which an analog transceiver is connected are protected against the high-voltage surge. Analog receiver consumes 0.2-mA current under 3-V supply and analog transmitter consumes 1.7-mA current to drive a 1-nF and serial 50- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> loads. The total area of receiver and transmitter with all supporting circuits and high-voltage switches is 0.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The implemented transceiver is compliant with USB PD and Type-C standards with respect to all required parameters.

Optimal Current Slew Rate Control for a Three-Phase MOSFET Inverter Driving a PMSM

The active control of the current slew rate of hard switched voltage source inverters is a common method to reduce the electromagnetic emissions, overshoot and ringing. In a previous work, the authors derived a model-based optimal slew rate control strategy which combines iterative learning control (ILC) with an adaptive feedforward control for a single half-bridge inverter. This control strategy minimizes the switching losses while the current slew rate stays within desired limits. This paper presents the required extensions of the current slew rate control strategy for a three-phase voltage source inverter driving a permanent magnet synchronous machine (PMSM). The extended control strategy is implemented on a rapid prototype test bench to verify the performance by a number of measurement results. The results show that the current slew rate of each phase is controlled separately within the defined limits while the switching losses are minimized, independent of the load current, the supply voltage and the temperature.

Convex Constrained Iterative Learning Control Using Projection: Application to a Smart Power Switch

This brief presents the application of convex constrained iterative learning control (ILC) using projection to the systematic slew rate control of smart power switches. Criteria for the monotonic and global convergence of the input and output iteration are presented for general first-order ILC laws with projection. Convergence of the ILC-based slew rate control for a smart power switch is analyzed and experimental results are shown.

The application of low-noise DC-DC power source in fiber-optic gyroscope system

In high-precision fiber-optic gyroscope (FOG) system, the spike noise of DC-DC power source can lead to a considerable disturbance to the signal processing circuit of FOG, which results in a sampling error. In this work, the cause of spike noise and the influence mechanism were clarified. The slew rate control technology was researched and proved to be an effective solution to prevent spike noise of FOG power source. Using slew rate control technology, a kind of low-noise power module has been developed and applied successfully in the FOG system. This power module consists of DC-DC circuit and LDO circuit, and slew rate control circuit was used in the DC-DC circuit to realize low-noise performance. The peak-to-peak noise value of the developed power module was tested to be about 1 mV in a bandwidth of 200 MHz. Two typical FOG systems were tested with the use of this low-noise power source, and their output noise improvement were 3.1% and 4.4%.

A configurable 2‐Gbps LVDS transceiver in 150‐nm CMOS with pre‐emphasis, equalization, and slew rate control

SummaryA configurable full‐duplex low‐voltage differential signaling transceiver is presented, which can be configured to operate either for smaller differential channels (a few inches of striplines) or for longer channels (10 m of twisted pair cables). The configurability is embedded in the form of functionalities like pre‐emphasis, equalization, and slew rate control within the transceiver. The transmitter employs a hybrid voltage–current‐mode driver, which due to replica action, achieves a high‐impedance current‐mode signal dispatch and at the same time provides a matched impedance at the near end for improved intersymbol interference. The transmitter achieves slew rate control through a band‐limited pre‐driver, while the pre‐emphasis is achieved through a capacitive feed‐forward. The receiver employs a large‐input common‐mode first stage enclosed in a common‐mode control loop that enables its first stage to also act like a domain shifter (VDDIO‐to‐VDDCORE) reducing the overall power consumption. The equalization in the receiver is implemented by using carefully sized active inductive loads inside the receiver. The transceiver is designed and fabricated in 150‐nm complementary metal–oxide–semiconductor, sharing the space with a larger die, occupying an area of 400 × 400μm. The measurement results demonstrate that the transceiver is operating at 2 Gbps both for a 4‐in microstrip and a 10‐m twisted pair CAT6 cable with 30 and 180 ps of total jitter, respectively. The built‐in impedance calibrator minimizes the spread in the on‐die termination at the near end provided by the transmitter‐minimizing bit error rate across process, voltage, and temperature corners. The transmitter consumes a total power of 17 mW operating at 2 Gbps, that is, 8.5 pJ/bit of energy consumption; the receiver consumes a total power of 3.5 mW while driving a load of 5 pF at 2 Gbps. Copyright © 2016 John Wiley &amp; Sons, Ltd.

Design and Performance of Power Supplies for Superconductor Insertion Devices at TLS 1.5-GeV Ring

A sophisticated power supply system was developed, installed, and successfully put into operation for the superconducting insertion devices at the 1.5-GeV Taiwan Light Source. These magnets include a superconducting wavelength shifter, a superconducting multipole wiggler, and three in-achromate superconducting wigglers. The power supply, with ±350-A/±15-V output power, is a four-quadrant bipolar switching step-down converter. The power supply, employing multiple regulation loops, slew rate control, and ultra high precision current transducer for feedback loop, is capable of delivering highly stable and reliable current to the superconducting loads. The topology, control scheme, and its performance are described in this paper. The power supply system's performance and reliability will be further improved and adopted to power low-temperature superconducting devices at the National Synchrotron Radiation Research Center in the future.

A ZVS Bidirectional Three-Level DC–DC Converter With Direct Current Slew Rate Control of Leakage Inductance Current

A high-frequency isolated bidirectional three-level dc–dc converter is proposed for high voltage applications. Direct current slew rate (DCSR) control of leakage inductance is proposed to minimize conduction loss and current stress in facing the load variation, the mismatch of turns ratio and circuit parasitic parameters. The mode analysis and the disadvantages of conventional PWM plus phase-shift (PPS) control are addressed while these disadvantages can be dealt with by the proposed control. Comprehensive comparison between conventional PPS control and the proposed DCSR control are made within the designed low voltage side (LVS) voltage range. Besides, the implementation of the proposed DCSR control is also given. With the proposed DCSR control, lower conduction loss, lower peak current, lower voltage spike over switches can be obtained in spite of the turns-ratio mismatch, load variation, and system parasitic parameters. Zero voltage switching (ZVS) can be achieved for all power switches in spite of the power flow direction. The effectiveness of the proposed DCSR control on the proposed topology is verified by simulation and experimental results.

Digital Slew Rate and S-Shape Control for Smart Power Switches to Reduce EMI Generation

Smart power switches are power switches with integrated control and protection functions for the switching of middle- and high-current loads. In particular in automotive applications, smart power switches have to be operated without additional stabilization networks, EMI filters, and heat sinks to keep the weight, required space and costs of the circuit boards as low as possible. Therefore, the generated electromagnetic emissions must be reduced by another measure without significantly increasing the switching losses. This can be achieved by the active control of the first and/or second derivative of the output voltage. This paper presents a digital slew rate control and its extension to an S-shape control strategy, which in addition to the slew rate, also controls the second derivative of the output voltage. Both strategies are based on feedforward gate current profiles, which are iteratively adapted by an iterative learning control strategy to compensate for load variations and temperature dependences. A rapid prototyping test bench is presented, and the performance and robustness of the control strategies are demonstrated by a series of measurement results. An EMC compliance test according to the CSIPR 25 standard shows that the generation of conducted electromagnetic emissions can be reduced in a power efficient way by the proposed approach.

Dynamic Slew-Rate Control for High Uniformity and Low Power in LCD Driver ICs

A slew-rate control method of LCD driver ICs is introduced to increase uniformity between adjacent driver ICs and reduce power consumption. The slew rate of every voltage follower is calibrated by a feedback algorithm during the non-displaying period. Under normal operation mode, the slew rate is dynamically controlled for improving power efficiency. Experimental results show that the power consumption is reduced by 16% with a white pattern and by 10% with a black pattern, and display defects are successfully eliminated.

Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current

Analysis of an open-loop time amplifier shows good agreement between measurements and calculations on the time gain, distortion of time gain, and rms noise and offset of output time difference. The time amplifier is based on the slew rate control method. It achieves a large time gain up to 120 and a wide range of input time difference up to 2 ns. The circuit consists of two precharged capacitors and current sources, where one capacitor is discharged at a fast slew rate during the time interval of the input time difference and then both capacitors are discharged at the same slow slew rate. The time gain is simply determined by the ratio of two bias current values. The proposed time amplifier is followed by an 8-bit TDC to obtain the digital output code. The time gain distortion caused by channel length modulation is less than 1.6% for the input time difference larger than 100 ps. The time offset and the rms noise of output time difference are inversely proportional to the smaller bias current. The rms noise is dominated by the noise of the comparator reference voltage. The time amplifier and TDC consume 0.36 mW and 1 mW, respectively, at 1.2 V supply in a 0.13 μm CMOS process.

Power optimal gate current profiles for the slew rate control of Smart Power ICs

Smart Power ICs are Power Switches with integrated control and protection functions. In order to meet the electromagnetic compatibility requirements, the output terminal slew rate has to be limited during the switching operation. In this context, special feedforward gate current profiles are widely used to control the switching slew rate. These profiles are typically determined on the basis of a linearized mathematical model of the Smart Power IC. However, due to the nonlinear characteristics of the IC, these profiles may lead to a reduced switching speed and thus to higher switching losses. In this work, an optimal control problem is considered which systematically accounts for the nonlinearities of the Power Switch, the switching losses and the limitation of the slew rate. In particular, a tailored mathematical model of the Smart Power IC is developed and parametrized. Based on this, the optimal control problem is formulated, numerically solved and the results are presented.