Slack Time Research Articles

Design of Power and Area Efficient Carry Skip Adder and FIR filter Implementation

Adders are used in processing units such as Arithmetic and Logic Units (ALUs) as an essential building block, and in many blocks of microprocessor chips critical path, adders occupy an important place. Hence reducing power, area and increasing the speed of adders are significantly important. This paper proposes a modified structure of Carry Skip Adder (CSKA) with a reduction in consumption of power and area without affecting the speed when compared with the conventional adder structures. In order to get better effectiveness of the modified CSKA by including concatenation, incrementation schemes, and variable latency for the proposed hybrid structure, which reduces the power utilized without affecting the operating speed of the adder. The modified structure in CSKA helps in improving the slack time, which further reduces the voltage with the parallel structure. Experimental results show that the 32-bit implementation of the proposed adder has a significant power reduction of 42% and 38.3%, area reduction of 27%, and 18.3% with respect to Conventional CSKA and CI CSKA adder with a little over ahead in delay. The proposed adder is used to implement a 5-tap FIR filter which shows a significant reduction in power consumption and area.

Methodology of Generating Timing-Slack-Based Cell-Aware Tests

In order to reduce defect parts per million, cell-aware (CA) methodology was proposed to cover various types of intracell defects. In this article, we present a novel methodology for generating 2-time-frame (2tf) CA tests based on timing slack analysis. The proposed 2tf CA fault model, aware of timing slack and named TS, defines a fault: 1) on a cell instance basis and 2) based on per-instance timing criticality (according to timing slack). By comparing the derived extra delay against the timing slack of the cell instance, a delay fault can be defined, and according to its severity, the fault can be further classified into small-delay fault or gross-delay fault. In contrast to prior 2tf CA methodology that is on a cell (rather than cell instance) basis and unaware of timing criticality/slack, our methodology can identify “more realistic” faults which really need to be considered, and potentially the cost/effort for testing those 2tf CA faults can be reduced. We also propose a test quality metric, timing slack defect coverage (TSDC), to measure the effectiveness of automatic test pattern generation (ATPG) tests in terms of the ability to detect small-delay TS defects along long paths. Experimental results on a set of 22-nm industrial designs demonstrate that, due to more realistic fault identification, the number of identified small-delay faults can be reduced by 56.8%. With the slack-based ATPG for testing small-delay faults along long paths, TS can reduce the number of test patterns by 33.1% while achieving 0.49% higher TSDC, compared with the results of prior 2tf CA methodology.

A security-aware hardware scheduler for modern multi-core systems with hard real-time constraints

In this paper, we propose an online security-aware hardware scheduler, the so-called Secure And Fast hardware Scheduler (SAFAS), for real-time task scheduling in multi-core systems in the presence of schedule-based side-channel attacks. To avoid such attacks and ensure that all tasks meet their deadlines, SAFAS schedules critical tasks and their replicas using a hardware-based strict Least Slack Time first (LST) algorithm independently while it independently schedules the non-critical tasks using a hardware-based EDF algorithm. SAFAS enhances the system performance and reduces the chance of side-channel attacks due to the different processing cores allocated to each task in each scheduling interval. The hardware scheduler operates independently and in parallel with the multi-core system and hides the scheduling characteristics from adversaries. The software-based Earliest Deadline First (EDF) algorithm is also used for schedulability tests and feasibility analysis of hard real-time periodic tasks to maximize the number of tasks scheduled successfully in the multi-core system. SAFAS has been synthesized and simulated on a Xilinx Vivado 2018.2 and implemented on a Spartan-7 FPGA chip. Our experimental results indicate that SAFAS increases the performance of the system by 4.8 times as compared to previous state-of-the-art hardware schedulers while guaranteeing that all critical tasks and their replicas meet their deadlines.

How to Choose and Implement Slack Time Models

How to Choose and Implement Slack Time Models

Resilience-Based Surrogate Robustness Measure and Optimization Method for Robust Job-Shop Scheduling

This paper addresses the robust job-shop scheduling problems (RJSSP) with stochastic deteriorating processing times by considering the resilience of the production schedule. To deal with the disturbances caused by the processing time variations, the expected deviation between the realized makespan and the initial makespan is adopted to measure the robustness of a schedule. A surrogate model for robust scheduling is proposed, which can optimize both the schedule performance and robustness of RJSSP. Specifically, the computational burden of simulation is considered a deficiency for robustness evaluation under the disturbance of stochastic processing times. Therefore, a resilience-based surrogate robustness measure (SRM-R) is provided for the robustness estimation in the surrogate model. The proposed SRM-R considers the production resilience and can utilize the available information on stochastic deteriorating processing times and slack times in the schedule structure by analyzing the disturbance propagation of the correlated operations in the schedule. Finally, a multi-objective hybrid estimation of distribution algorithm is employed to obtain the Pareto optimal solutions of RJSSP. The simulation experiment results show that the presented SRM-R is effective and can provide the Pareto solutions with a lower computational burden. Furthermore, an RJSSP case derived from the manufacturing environment demonstrates that the proposed approach can generate satisfactory robust solutions with significantly improved computational efficiency.

A Multiobjective Optimization Model for Flexroute Transit Service Design

Flexroute transit (also referred to as route-deviation) is an innovative public transportation approach in which service is provided at fixed stops on a predetermined schedule, while also providing “on-demand” service to customers between the fixed stops. A significant challenge to the implementation of flexroute transit has been the complexity inherent in the design process. This research explored two of the key design parameters available to a transit planner: service zone size (the area between fixed stops where deviations are permitted), and slack time distribution (the method used to distribute among zones the total “slack” time built into the schedule to allow for deviations). It was found that the objectives of maximizing feasible deviations and minimizing unused slack time are conflicting and highly sensitive to the design parameters. To assist in the design process, the article formulates a multiobjective binary optimization model that can be used to develop an efficient frontier—guiding transit planners as they seek to explore design trade-offs.

Intelligent energy-efficient scheduling with ant colony techniques for heterogeneous edge computing

Energy efficiency is a significant issue in heterogeneous edge computing systems for a large number of latency-sensitive applications. This article presents an efficient technique to minimize energy overhead of time-constrained applications modeled by DAGs in heterogeneous edge computing. The technique is divided into three stages. First, we design a new method to compute task priority and propose the ant-colony based energy-aware scheduling algorithm to get a preliminary scheduling result. Second, taking the slack time between tasks and their deadlines into consideration, we propose the downward proportionally reclaiming slack algorithm to further cut down energy overhead by the DVFS technique. Third, taking the slack time between tasks into consideration, we propose the upward and downward proportionally reclaiming slack algorithm to cut down energy overhead by the DVFS technique again. Simulated results indicate that the presented technique is highly efficient in reducing energy overhead compared with state-of-the-art techniques using benchmarks of distinct characteristics.

Design of Serial Multiplier Circuit Based on a Variable Length Conditional Binary Counter for Improved Critical Path Delay and Slack Time

Design of Serial Multiplier Circuit Based on a Variable Length Conditional Binary Counter for Improved Critical Path Delay and Slack Time

EnHAT — Synergy of a tree-based Ensemble with Hoeffding Adaptive Tree for dynamic data streams mining

The goal of this paper is to improve the predictive accuracy of data streaming algorithms without increasing the processing time of the incoming data. We propose the EnHAT (Ensemble Combined with Hoeffding Adaptive Tree) algorithm, which combines the state-of-the-art Hoeffding Adaptive Tree (HAT) algorithm with an ensemble of J48 decision trees induced from sequential chunks of the data stream. The slack time of HAT adaptation to a new window of incoming records is utilized in parallel for building a decision-tree ensemble. In our experiments on 4 benchmark streaming datasets and 4 synthetic datasets with different types of concept drift, EnHAT has reached the highest predictive accuracy in 23 out of 26 cases compared to an ensemble of J48 trees, HAT, and a single J48 model induced from the last sliding window. Thus, we can conclude that the ensemble/HAT synergy yields better prediction results than each one of the two approaches on its own. The higher accuracy does not come at the expense of any additional computational effort beyond the model induction times of the combined algorithms.

Energy aware fixed priority scheduling in mixed-criticality systems

Most of studies about energy management for MC systems are based on dynamic priority scheme. The disadvantages of dynamic priority scheme are high system overhead and poor predictability. Unlike previous studies, we focus on the problem of scheduling mixed-criticality (MC) periodic tasks with minimizing energy consumption in MC systems based on fixed priority scheme. Firstly, we explain a criticality rate monotonic scheduling (CRMS) and propose the sufficient schedulability condition of CRMS. Secondly, we compute the energy minimization uniform scaled speed and present an optimal static solution algorithm based on CRMS. The extra workload of the high criticality level (HI) task executes with the maximum processor speed in the high criticality mode (HI-mode). But this algorithm does not exploit the slack time generated from the HI task in the low criticality mode (LO-mode). For energy efficiency, we propose a dynamic fixed priority energy minimization algorithm which exploits the slack time generated from the HI task in LO-mode to save energy. In addition, it combines a dynamic voltage and frequency scaling technique and a dynamic power management technique to reduce energy consumption. Finally, the experiments are applied to evaluate the performance of the proposed algorithm and the experimental results show that the proposed algorithm can save up 23.89% energy compared with other existing algorithms.

Formulation and Optimization of Gastro retentive Glimepiride Floating Matrix Tablets

The main objective of this research investigational studies is to formulate floating matrix tablets of glimipride by applying simplex centroid design for optimization technique and by direct compression method. The simplex Centroid configuration was drilled as an enhancement strategy by adjusting the amount of three components all the while and holding back their total concentration constant. Ingredients HPMC K15m, Kappa-carrageenan and sodium bicarbonate as X1,X2,X3 independent Variables while response variables Y1 floating lag time Y1, Percentage drug released after 1 hour Y2% and t90 time required for 90% were considered as response variable factors for formulation and optimization of total 14 formulations simplex centroid design was applied. The measures of HPMC K15M (X1), kappa-Carrageenan (X2) and sodium bicarbonate (X3) were utilized as the autonomous factors while coasting slack time (Y1), Percentage drug discharged after 1 hour(Y2) and time required for 90% (t90) were taken as the reaction factors. According to the simplex centroid configuration complete 14 formulations were formulated. Matrices were evaluated for physical parameters, in-vitro buoyancy, swelling ability and adhesion retention period. It was inferred that the blend of kappa carrageenan and HPMC K 15 M builds the adaptability in the release pattern of the drug. This examination sets up the utilization of simplex centroid structure in the advancement of coasting network tablets with least experimentation.

Design of VLSI Based Power-Saving Streetlight System and Automatic Traffic Controller with Automatic Transfer Switch

The number of road accidents is increasing due to the power outage of the traffic light system and the streetlight system's maintenance fees was too high. Therefore, a proposed solution that includes automatic traffic light controller, energy-saving streetlight controller and automatic energy transfer switch had been designed to overcome these issues. The proposed traffic light is on a four-way junction which has one sensor for each direction. This traffic light controller has 3 different conditions which will act differently when all directions had detected vehicle, or when vehicle is not detected, or when vehicle is detected in some directions. Apart from this, a streetlight controller is also designed to minimize the power usage and the streetlight will only turn on when vehicle is detected. The proposed solution was designed in Quartus 18 via Verilog Hardware Description Language (HDL) and functional simulation is used to verify the proposed circuit is functioning correctly The Verilog HDL files were input to the Synopsys Design Compiler for logical synthesis and IC Compiler for physical synthesis. After both logical and physical synthesis, the design was then analysed in terms of speed, area, and power consumption through the generate report commands. Besides, the proposed energy-saving streetlight was programmed into Field Programmable Gate Array (FPGA) and connected with AC Dimmer Module and LED bulb to measure the power consumption and the reduction of power consumption of the LED bulb. As for the result, the designed chip had a total area of 392.002199 μm^2, positive critical timing slack of 0.1 ns and power consumption of 0.1196 mW. The streetlight was able to achieve a reduction in power consumption by 77.87%.

Learning-Oriented QoS- and Drop-Aware Task Scheduling for Mixed-Criticality Systems

In Mixed-Criticality (MC) systems, multiple functions with different levels of criticality are integrated into a common platform in order to meet the intended space, cost, and timing requirements in all criticality levels. To guarantee the correct, and on-time execution of higher criticality tasks in emergency modes, various design-time scheduling policies have been recently presented. These techniques are mostly pessimistic, as the occurrence of worst-case scenario at run-time is a rare event. Nevertheless, they lead to an under-utilized system due to frequent drops of Low-Criticality (LC) tasks, and creation of unused slack times due to the quick execution of high-criticality tasks. Accordingly, this paper proposes a novel optimistic scheme, that introduces a learning-based drop-aware task scheduling mechanism, which carefully monitors the alterations in the behaviour of the MC system at run-time, to exploit the generated dynamic slacks for reducing the LC tasks penalty and preventing frequent drops of LC tasks in the future. Based on an extensive set of experiments, our observations have shown that the proposed approach exploits accumulated dynamic slack generated at run-time, by 9.84% more on average compared to existing works, and is able to reduce the deadline miss rate by up to 51.78%, and 33.27% on average, compared to state-of-the-art works.

Hardware Patching Methodology for Neutralizing Timing Hardware Trojans Using Vulnerability Analysis and Time Borrowing Scheme

Outsourcing of the design and IC fabrication to the untrusted entities increases the risk of hardware Trojan insertion in different stages of IC’s life cycle. In this brief, we propose a pre-silicon modification scheme, aiming at detecting and compensating the adverse effect of timing hardware Trojans (THT) using a time borrowing approach. The key idea is that a circuit path under tamper in which the setup time is violated can borrow some time from the following stage if it has enough positive timing slack to donate. Accordingly, we modify the original circuit by employing the Dynamic flip-flop Conversion (DFFC) structures to convert the suspected flip-flops into a single transparent latch. A new timing vulnerability analysis including the path-delay and structural analysis along with the proposed test pattern generation scheme is also developed to exploit the vulnerable paths suitable for DFFC insertion. The experimental results show that the insertion of DFFC structures can effectively predict timing errors higher than 1.4% of the critical path-delay while it can fully restore the Trojan-infected paths back to its normal state by compensating 100% of the injected delays ranging from 39% to 81% of the critical path.

State-Dependent Parameter Tuning of the Apparent Tardiness Cost Dispatching Rule Using Deep Reinforcement Learning

The apparent tardiness cost (ATC) is a dispatching rule that demonstrates excellent performance in minimizing the total weighted tardiness (TWT) in single-machine scheduling. The ATC rule’s performance is dependent on the lookahead parameter of an equation that calculates the job priority index. Existing studies recommend a fixed value or a value derived through a handcrafted function as an estimate of the lookahead parameter. However, such parameter estimation inevitably entails information loss from using summarized job data and generates an inferior schedule. This study proposes a reinforcement learning-based ATC dispatching rule that estimates the lookahead parameter directly from raw job data (processing time, weight, and slack time). The scheduling agent learns the relationship between raw job data and the continuous lookahead parameter while interacting with the scheduling environment using a deep deterministic policy gradient (DDPG) algorithm. We trained the DDPG model to minimize the TWT through a simulation in a single-machine scheduling problem with unequal job arrival times. Based on a preliminary experiment, we verified that the proposed dispatching rule, ATC-DDPG, successfully performed intelligent state-dependent parameter tuning. ATC-DDPG also displayed the best performance in the main experiment, which compared the performance with five existing dispatching rules.

Power-Aware Checkpointing for Multicore Embedded Systems

Increasing the number of cores integrated on a single chip offers a great potential for the implementation of fault-tolerant techniques to achieve high reliability in real-time embedded systems. Checkpointing with rollback-recovery is a well-established technique to tolerate transient faults in multicore platforms. To consider the worst-case fault occurrence scenario, checkpointing technique requires to re-execute some parts of the tasks, and that might lead to simultaneous execution of task parts with high power consumptions, which eventually might result in a peak power increase beyond the thermal design power (TDP). Exceeding TDP can elevate on-chip temperatures beyond safe limits, and thereby triggering countermeasures that throttle down the voltage and frequency levels or power gate the cores. Such countermeasures might lead to violating task deadlines and degrading the system&#x0027;s reliability. To avoid such severe scenarios, it is inevitable to consider the impact of applying fault-tolerant techniques on the power consumption and prevent violating the power constraint of the chip, i.e., TDP. This paper presents for the first time, a peak-power-aware checkpointing (PPAC) technique that tolerates a given number of faults, <i>k</i>, while at the same time meets the power constraint in hard real-time embedded systems. To do this, our proposed technique (PPAC) adjusts the timing of the checkpoints, which have lower power consumption than the tasks to the execution time points that have power spikes beyond TDP. Moreover, PPAC exploits the available slack times on the cores to delay the execution of some tasks to avoid the remaining power spikes beyond TDP, which could not be mitigated by solely adjusting checkpoints. To evaluate our technique, we extend the state-of-the-art system-level simulator, gem5, with the state-of-the-art checkpointing module in Linux. Our experimental results show that our proposed technique is able to tolerate a given number of faults without exceeding the timing and power constraints in hard real-time embedded systems. The resulting peak power reduction achieved by our technique compared to state-of-the-art techniques is an average of 23&#x0025;. Moreover, our technique employs the Dynamic Power Management (DPM) during the slack times resulting at runtime in the case of fault-free scenarios, which provides energy savings with an average of 17.28&#x0025; and up to 61.1&#x0025;.

Developing Guidelines for Implementing Transit Signal Priority and Freight Signal Priority Using Simulation Modeling and a Decision Tree Algorithm

Transit signal priority (TSP) and freight signal priority (FSP) allow transportation agencies to prioritize signal service allocations considering the priority of vehicles and, potentially, decrease the impact signal control has on them. However, there have been no studies to develop guidelines for implementing signal control considering both TSP and FSP. This paper reports on a study conducted to provide such guidelines that employed a literature review, a simulation study, and a decision tree algorithm based on the simulation results. The guideline developed provides recommendations in accordance with the signal timing slack time, the proportion of major to minor street hourly volume, hourly truck volume per lane for the major street, hourly truck volume per lane for the minor street, the proportion of major to minor street hourly truck volume, the proportion of major to minor street hourly bus volume, the volume-to-capacity ratio for the major street, and the volume-to-capacity ratio for the minor street. The guideline developed was validated by implementing it for a case study facility. The validation result showed that the guideline works correctly for both high and low traffic demand.

Integration of Mixed-Integer Nonlinear Program and Project Management Tool to Support Sustainable Cost-Optimal Construction Scheduling

This paper presents the integration of mixed-integer nonlinear program (MINLP) and project management tool (PMT) to support sustainable cost-optimal construction scheduling. An integrated structure of a high-level system for exact optimization and PMT was created. To ensure data compatibility between the optimization system and PMT and to automate the process of obtaining a cost-optimal schedule, a data transformation tool (DTT) was developed within a spreadsheet application. The suggested system can determine: (i) an optimal project schedule with associated network diagram and Gantt chart in continuous or discrete time units; (ii) optimal critical and non-critical activities, including their early start, late start, early finish, late finish along with total and free slack times; and (iii) minimum total project cost along with the allocation of direct and indirect costs. The system provides functionalities such as: (i) MINLP can be updated, and schedules can be re-optimized; (ii) the optimal schedule can be saved as a baseline to track changes; (iii) different optimization algorithms can be engaged whereby switching between them does not require model changes; (iv) PMT can be used to track task completion in the optimized schedule; (v) calendar settings can be changed; and (vi) visual reports can be generated to support efficient project management. Results of cost-optimal project scheduling are given in a conventional PMT environment, which raises the possibility that the proposed system will be more widely used in practice. Integration of MINLP and PMT allows each software to be used for what it was initially designed. Their combination leads to additional information and features of optimized construction schedules that would be significantly more difficult to achieve if used separately. Application examples are given in the paper to show the advantages of the proposed approach.

Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error Control

Approximate Computing has emerged as an alternative way to further reduce the power consumption of integrated circuits (ICs) by trading off errors at the output with simpler, more efficient logic. So far the main approaches in approximate computing have been to simplify the hardware circuit by pruning the circuit until the maximum error threshold is met. One of the critical issues, though, is the training data used to prune the circuit. The output error can significantly exceed the maximum error if the final workload does not match the training data. Thus, most previous work typically assumes that training data matches with the workload data distribution. In this work, we present a method that dynamically overscales the supply voltage based on different workload distribution at runtime. This allows to adaptively select the supply voltage that leads to the largest power savings while ensuring that the error will never exceed the maximum error threshold. This approach also allows restoring of the original error-free circuit if no matching workload distribution is found. The proposed method also leverages the ability of High-Level Synthesis (HLS) to automatically generate circuits with different properties by setting different synthesis constraints to maximize the available timing slack and, hence, maximize the power savings. Experimental results show that our proposed method works very well, saving on average 47.08% of power as compared to the exact output circuit and 20.25% more than a traditional approximation method.

Energy-aware fixed priority scheduling with shared resources in standby-sparing systems

The problem of joint energy and reliability management for fixed priority periodic real-time tasks set with shared resources on a standby-sparing system is studied in this paper. A novel algorithm called FPMPSA is proposed. It considers frequency transition and processor state transition overheads imposed by dynamic voltage frequency scaling (DVFS) and dynamic power management (DPM). In addition, it applies the rate monotonic with dual priority scheduling policy (RM/DPP) to ensure that shared resources can be accessed in a mutual exclusive manner. Moreover, the mixed mapping method is applied to map the main task and backup task. Furthermore, the energy efficient speed of the main task SM is determined and the backup task executes with the maximum processor speed. For energy efficiency, the algorithm called DFPMPSA which is an extension of FPMPSA is proposed. It can use the dynamic slack time to reduce energy consumption. The experimental results show that DFPMPSA algorithm consumes average 8.15% less energy than that of FPMPSA.