Switch Size Research Articles

Design Considerations for Power-Efficient Fully Integrated 3:1 Switched Capacitor DC-DC Converter for PV Modules

This article presents a power-efficient DC-DC converter based on a switched-capacitor (SC) cell in power management systems supplied for fully integrated photovoltaic (PV) modules. These modules shall provide high-performance point-of-load voltage regulation. The primary objective of this study is to better utilize capacitance and switches by selecting a proper SC topology in order to improve the power efficiency of SC converters. A general steady-state performance model is investigated to optimize and compare a variety of SC DC-DC topologies. The investigation method relies on a charge-multiplier approach and considers the impact of area constraint on capacitors. To identify the most suitable topology for a given conversion ratio, the performance-limit metrics of SC converters are calculated. The analysis provides framework to determine optimum switch size and switching frequency for a two-phase 3:1 series–parallel converter for a target load current of 10 mA implemented on a 22 nm process technology. The results shows that a minimum of 250 MHz switching frequency is desirable for achieving a target efficiency greater than 85% while maintaining the minimum output voltage of 0.34 V. The analysis results are verified through MATLAB and PSpice-based simulations.

The size coding of responses: The size of switches and the force feedback.

We aimed to understand which factors have a functional role in the size coding of responses, either the size of the switches or the force required to trigger each switch. This question is of relevance because it allows a better understanding of processes underlying action coding. In each trial, participants saw a small or large object. Depending on its colour, the participants had to press one of two switches. In the "size" condition, the response device consisted of two switches of different visual size, but both required the same amount of force. In the "force-feedback" condition, the response device consisted in two switches of identical visual size, but one switch required more force than the other. We found a compatibility effect in the "size," not in the "force-feedback" condition, supporting that the size-coding of responses would be due to the size of the switches.

What Drives Task Performance in Animal Fluency in Individuals Without Dementia? The SMART-MR Study.

In this study, we aim to understand whether and how performance in animal fluency (i.e., total correct word count) relates to linguistic levels and/or executive functions by looking at sequence information and item-level metrics (i.e., clusters, switches, and word properties). Seven hundred thirty-one Dutch-speaking individuals without dementia from the Second Manifestations of ARTerial disease-Magnetic Resonance study responded to an animal fluency task (120 s). We obtained cluster size and number of switches for the task, and eight different word properties for each correct word produced. We detected variables that determine total word count with random forests, and used conditional inference trees to assess points along the scales of such variables, at which total word count changes significantly. Number of switches, average cluster size, lexical decision response times, word frequency, and concreteness determined total correct word count in animal fluency. People who produced more correct words produced more switches and bigger clusters. People who produced fewer words produced fewer switches and more frequent words. Concurrent with existing literature, individuals without dementia rely on language and executive functioning to produce words in animal fluency. The novelty of our work is that such results were shown based on a data-driven approach using sequence information and item-level metrics. https://doi.org/10.23641/asha.23713269.

Phonological and semantic verbal fluency test: Scoring criteria and normative data for clustering and switching strategies for Colombian children and adolescents.

Verbal fluency tests (VFT) are highly sensitive to cognitive deficits. Usually, the score on VFT is based on the number of correct words produced, yet it alone gives little information regarding underlying test performance. The implementation of different strategies (cluster and switching) to perform efficiently during the tasks provide more valuable information. However, normative data for clustering and switching strategies are scarce. Moreover, scoring criteria adapted to Colombian Spanish are missing. (1) To describe the Colombian adaptation of the scoring system guidelines for clustering and switching strategies in VFT; (2) to determine its reliability; and (3) to provide normative data for Colombian children and adolescents aged 6-17 years. A total of 691 children and adolescents from Colombia completed phonological (/f/, /a/, /s/, /m/, /r/ and /p/) and semantic (animals and fruits) VFT, and five scores were calculated: total score (TS), number of clusters (NC), cluster size (CS), mean cluster size (MCS) and number of switches (NS). The intraclass correlation coefficient was used for interrater reliability. Hierarchical multiple regressions were conducted to investigate which strategies were associated with VFT TS. Multiple regressions were conducted for each strategy, including as predictors age, age2 , sex, mean parents' education (MPE), MPE2 and type of school, to generate normative data. Reliability indexes were excellent. Age was associated with VFT TS, but weakly compared with strategies. For both VFT TS, NS was the strongest variable, followed by CS and NC. Regarding norms, age was the strongest predictor for all measures, while age2 was relevant for NC (/f/ phoneme) and NS (/m/ phoneme). Participants with higher MPE obtained more NC, and NS, and larger CS in several phonemes and categories. Children and adolescents from private school generated more NC, NS and larger CS in /s/ phoneme. This study provides new scoring guidelines and normative data for clustering and switching strategies for Colombian children and adolescents between 6 and 17 years old. Clinical neuropsychologists should include these measures as part of their everyday practice. What is already known on the subject VFT are widely used within the paediatric population due to its sensitivity to brain injury. Its score is based on the number of correct words produced; however, TS alone gives little information regarding underlying test performance. Several normative data for VFT TS in the paediatric population exist, but normative data for clustering and switching strategies are scarce. What this paper adds to existing knowledge The present study is the first to describe the Colombian adaptation of the scoring guidelines for clustering and switching strategies, and provided normative data for these strategies for children and adolescents between 6 and 17 years old. What are the potential or actual clinical implications of this work? Knowing VFT's performance, including strategy development and use in healthy children and adolescents, may be useful for clinical settings. We encourage clinicians to include not only TS, but also a careful analysis of strategies that may be more informative of the underlying cognitive processes failure than TS.

A high‐efficiency power management unit with wide dynamic range for RF energy harvesting system

AbstractA high‐efficiency power management unit (PMU) with wide dynamic range for radio frequency (RF) energy harvesting system is proposed in this paper. A digital zero current switching (ZCS) and a digital maximum power point tracking (MPPT) circuits are adopted. A sub‐threshold current reference circuit and a subthreshold voltage detection circuit are proposed to reduce the power consumption of always‐on control circuits and improve the conversion efficiency at low input power. A dual‐oscillator is designed to extend the frequency range and widen the input power range with optimized power consumption under low‐end band and high‐end band, respectively. Switch size and on‐time are adjusted according to the input power, which optimizes the conversion efficiency in a wide power range. Proposed PMU is implemented in a standard 180 nm CMOS process. The post‐layout simulation results show that proposed PMU can achieve cold‐start at the input voltage of 280 mV, the power consumption to maintain the PMU is only 9.6 nW. The input power range of the PMU is 11 nW–677 μW. When the input power is 50 nW, a power conversion efficiency (PCE) of 65% is achieved, and the peak PCE can reach 93% at 23.5 μW.

Optical waveguide switch based on a negative-index metamaterial load.

An optical switch concept is presented which involves moving a negative-index metamaterial (NIM) load, possibly with loss, close to one waveguide in a two-waveguide directional coupler. The NIM load limits the number of optical modes in the switch, creating a system where the single waveguide mode propagation constant is far from other mode propagation constants. The wide spacing in propagation constants, not possible with positive-index media (PIM) loads, permits a small switch size. Three-dimensional (3D) finite-difference time-domain (FDTD) simulations confirm results from a simple one-dimensional (1D) model. Importantly, realistic NIM losses do not impede switch operation.

A 6.78-MHz Digital Rectifier-Based Single-Stage Wireless Charger Using Digital-Controlled CC–CV Technique for Implantable Biomedical Devices

This letter presents a digital rectifier-based single-stage wireless charger. The proposed charger regulates charging current by adjusting the size of the power switch digitally, and the power loss of the switch can be reduced adaptively according to the charging condition. The power conversion efficiency is consequently improved significantly. Furthermore, high charging resolution and low output voltage ripple have been achieved by introducing a successive approximation method. Compared with the conventional analog-controlled charging technique, the proposed digital control can shorten the mode transition time, and thus avoid potential battery overcharging. In addition, a high-speed current sensor operating at 6.78 MHz is proposed to guarantee the sensing accuracy. The proposed single-stage wireless charger is fabricated in a 0.18-µm bipolar CMOS DMOS process with a die area of 0.56 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^{2}$</tex-math></inline-formula> . The measured peak receiver efficiency of the proposed charger is 92.8%.

Beta-Quasi-Z-Source (β-qZS) DC–DC Converter Without Duty Cycle Constraint for Wide Input Voltage Applications

A novel beta-quasi-Z-source (β-qZS) converter is proposed for an isolated dc–dc converter with the buck (step-down) and boost (step-up) functions. The β-qZS isolated dc–dc converter addresses the common challenges such as components stresses, reliability, suppression of switch voltage overshoot, size, and power derating in the existing impedance source-based isolated dc–dc converter applications. In addition, the proposed topology dealt with operating duty cycle constraint and loss of duty cycle phenomenon in the Z/qZS galvanically isolated dc–dc converters. This article describes the configuration and provides the principle of operation for the proposed β-qZS converter topology. A laboratory prototype is developed, and the experimental results satisfy the theoretical analysis.

A 13.56 MHz Wireless Power Transfer System With Fully Integrated PLL-Based Frequency-Regulated Reconfigurable Duty Control for Implantable Medical Devices.

In this paper, a 13.56 MHz wireless power transfer system with transmitter (TX) and receiver (RX) chips is presented. Both TX and RX chips were designed with fully integrated reconfigurable single power stage to realize adaptive power delivery and output voltage regulation. The reconfigurable operation of TX and RX is synchronized and the reconfiguration frequency which could vary with coupling or loading condition is locked by the proposed phase-locked-loop-based on-time duty controller to mitigate the electromagnetic interference. In addition, calibrations for circuit delay and power switch size were implemented in the RX chip to enhance system efficiency further. The system complexity is reduced considerably by removing the successive power stages and off-chip controllers used in previous studies. The TX and RX chips were fabricated in TSMC 0.18 μm CMOS process. The measurement results demonstrated seamless output voltage regulation under an output power range from 4.2 mW to 162 mW and a peak end-to-end efficiency of 70.1%.

A Fully Integrated Switched Capacitor Power Converter With Minimum Driving Loss Point Tracking Technique

A fully integrated switched capacitor power converter (SCPC) with minimum driving loss point tracking (MDLPT) technique is proposed in this brief. The driving voltage, switching frequency and power switch size are all taken into consideration, and are dynamically adjusted to the optimal value. As the result, the driving loss of SCPC is optimized in real time. Digital LDO is used to detect driving loss in the proposed technique, thereby avoiding complicated search algorithms or sampling circuits. The proposed SCPC is manufactured in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18\mathbf {\mathrm {\mu }}\text{m}$ </tex-math></inline-formula> CMOS process. The input voltage is 1.8V and the output voltage is 0.5V to 1.5V, the maximum load current is 15mA. Experimental results show that the efficiency of the proposed SCPC can reach 81.9%. The proposed method can reduce the driving loss by up to 27% at typical load point, resulting in a 7.8% increase in efficiency.

A Reconfigurable DC-DC Converter for Maximum Thermoelectric Energy Harvesting in a Battery-Powered Duty-Cycling Wireless Sensor Node

This paper presents a reconfigurable dc–dc converter for maximum thermoelectric generator (TEG) energy harvesting in a battery-powered duty-cycling wireless sensor node. The proposed dc–dc converter adopts discontinuous energy harvesting, which operates in single-input dual-output (SIDO) boost, battery-TEG pile-up buck (BTPB), dual-phase buck–boost (DPBB), and battery supplied buck modes with a single shared inductor. Fabricated in a 65-nm CMOS process, the converter adopts an adaptive dead-time controller for zero-voltage switching (ZVS) and an adaptive switch size (ASS) with maximum power point tracking (MPPT) to maximize efficiency in a wide TEG voltage range. The SIDO boost mode achieves 88.5% and 81.1% peak end-to-end efficiency with maximum and no-load conditions (only charging the battery), respectively. The combination of BTPB and DPBB modes to maximize the TEG power extraction during the battery-powered operation results in up to 44% saving in battery power. The battery-supplied buck mode achieves 93.3% peak efficiency.

Performance Modelling and Design Techniques for Efficiency Improvement in On-chip Switched-Capacitor DC-DC Converter

Fundamental charge vector method analysis is a single parameter optimization technique limited to conduction loss assuming all frequency-dependent switching (parasitic) loss negligible. This paper investigates a generalized structure to design DC-DC SC converters based on conduction and switching loss. A new technique is proposed to find the optimum value of switching frequency and switch size to calculate target load current and output voltage that maximize the efficiency. The analysis is done to identify switching frequency and switch size for two-phase 2:1 series–parallel SC converter for a target load current of 2.67 mA implemented on a 22 nm technology node. Results show that a minimum of 250 MHz switching frequency is required for target efficiency more than 90% and the output voltage greater than 0.85 V where the switch size of a unit cell corresponds to 10Ω on-resistance. MATLAB and PSpice simulation tools are used for results and validation.

T- and Cascaded Pi-Shaped 1H T/R Switches with Realistic Trace Width for 7 Tesla MRI

In this work, two designs of Transmit/Receive (T/R) switches are introduced for 7-Tesla magnetic resonance imaging. The T-shaped and the two cascaded Pi-shaped microstripline-based T/R switches for 1H MRI are designed with the minimum trace width constraint that handles the required power and assures a compact size of the switch. When the peak power of the Radio Frequency (RF) amplifier signal is 1 kW with 10% duty cycle, the average current that will pass through 50 Ω input impedance circuit is 2 A. Based on IPC 2221 standard for PCB traces, the minimum trace width that handles such a current is of 0.513 mm. The ADS software is used in designing the T as well as two sections pi-shaped switches. All the proposed 7-Tesla 1H MRI switches have revealed good matching (&lt;-20 dB), low insertion loss (&lt;0.34 dB), and high isolation (&gt;60 dB) during transmit and receive. The designed switches are compact in size by around 40% reduction in dimensions compared to a conventional switch size (100 mm × 100 mm) without folding.

A compact dual‐functional component for spatial diversity and multiplexing applications

This paper presents a new compact four-port component with dual-functional dual-mode characteristics for spatial diversity and multiplexing applications. The component can achieve the 3-dB hybrid coupler mode at the lower frequency and the transmission line mode at the higher frequency, corresponding to spatial diversity and multiplexing applications, respectively. The proposed component is designed based on a three-section crossover and analyzed based on the Even-odd model analysis. It features good S-parameter characteristics, compact size, and none of the RF switches. A component working at 4.5-/5.4-GHz has been fabricated and measured to prove its design theory. To practice, the proposed component is applied to a 1 × 2 wideband Yagi antenna array. The measured results show diversity beams and multiplexing beams at two operating bands respectively, suitable for complex wireless communication systems.

Voltage- and Redox State-Triggered Oxygen Adatom Conductance Switch

Switches are omnipresent in all electronic devices. Miniaturization reduced the size of switches down to atomic dimensions. While on-surface tip-tuned molecular switches have recently been widely s...

Euler–Lagrange passivity-based controller for the three-level Ćuk PFC converter for electric vehicle battery charging application

This paper intends a Euler-Lagrange passivity-based controller (EL-PBC) for the three-level (TL) Ćuk PFC converter for EVs battery charging application. The TL Ćuk converter has features of reduced filter size and voltage stress of switches. First, the Euler-Lagrange formulation is used to develop the mathematical modelling. Then, the EL-PBC methodology is implemented by injecting a virtual resistor in series with the input inductor. Further, the stability analysis is also carried out. To improve the performances against input perturbations and reduce the steady state error, a PI controller is integrated with the aforesaid controller and its performances are investigated. Furthermore, the power quality of the charger is assessed and it satisfies IEC 61000-3-2 Class C standard. This controller is also compared with the benchmark PI controller. A prototype model of same specifications is tested in hardware in loop. Computer simulations and test results are presented to validate the theoretical aspects.

A Packaged THz Shunt RF MEMS Switch With Low Insertion Loss

This paper demonstrates a packaged THz shunt capacitor micro-electromechanical systems (MEMS) switch with low insertion loss. In-line shunt switch is used to achieve a low loss in THz band, which is realized by reducing the equivalent parallel inductance of switch. The equivalent circuit of the switch is analyzed systematically, the equivalent resistance is obtained based on the skin effect of high frequency current on the conductor and the current density distribution characteristics of the conductor cross-section. The equivalent capacitance is obtained by using &#x201C;double microstrip&#x201D; characteristic impedance calculation method, and the correction factor (<inline-formula> <tex-math notation="LaTeX">$\Delta$ </tex-math></inline-formula>) is introduced to calculate the equivalent inductance accurately. By optimizing equivalent circuit parameters and switch sizes, the structure of MEMS switch with low loss and high isolation characteristics are achieved. The switch is packaged by rectangular waveguide and achieved a low insertion loss. The comparison between the switch simulation results and the equivalent circuit simulation results verify that the parameter extraction method and circuit analysis are correct. The packaged MEMS switch is measured, and the results are in an acceptable agreement with simulation, the switch is actuated under voltage of &#x007E;30V. The measured result has achieved a low insertion loss with less than &#x003C; 2dB from 220 to 280GHz, and isolation with &#x007E;16 dB from 240GHz to 320GHz in the &#x201C;down&#x201D; state.

Architecture design and performance analysis of a novel memory system for high-bandwidth onboard switching fabric

The development of the space–air–ground integration has put higher demands on satellite network. It needs to support high-bandwidth, large-capacity and various quality of service guarantees. However, the satellite onboard switching is facing the problem of resource constraints and special requirements of hardware complexity and scheduling efficiency. For this, this paper proposes a novel memory architecture for high-bandwidth onboard switching fabric. To reduce hardware complexity, multiplexer is used in the input side to merge k input ports into one internal bus, while the output demultiplexer splits an internal bus into k output links. Shared memory architecture is adopted in the input module to improve the memory efficiency, and a buffered crossbar is used to interconnect the input modules to the output modules. A discrete-time queuing model is formulated, and an iterative approach is used to quantitatively analyze the performance of the proposed architecture. The throughput and delay are calculated under different switch size, input load, and buffer capacity. The numerical results can serve as a guidance on deciding the required buffer size and appropriate speedup ratio. This work is validated by both simulations and FPGA implementations. Synthesize result show that using the state-of-the-art Xilinx VU13P FPGA, a switching fabric with 48 ports can be implemented and the peak throughput of the proposed architecture can reach 480 Gbps. Compared with existing combined input-crosspoint queuing, the proposed architecture can significantly reduce the packet delay and the memory resource cost.

A 6.78 MHz, 95.0% Peak Efficiency Monolithic Two-Dimensional Calibrated Active Rectifier for Wirelessly Powered Implantable Biomedical Devices.

In this paper, a fully integrated active rectifier with triple feedback loops is proposed to enhance power conversion efficiency (PCE) over a wide loading range by calibrating both the gate transition timing and power switch size. The on- and off-transitions of the power switches are calibrated using a hybrid delay-based gate control circuit (HDGCC) with hybrid feedback loops. Conventional active rectifiers that only focused on calibrating the gate transition timing of a NMOS power switch with a fixed power switch size exhibit a low PCE when the loading condition deviates from the predetermined range. Thus, an automatic size selector based on a third feedback loop is proposed, which changes the power switch size based on the loading condition and ensures a stable operation of the hybrid loops by maintaining the voltage drop across the NMOS switches. An active rectifier was fabricated using the standard 0.18 μm CMOS process. The effectiveness and robustness of the two-dimensional calibration were verified through measurements under an AC input voltage ranging from 2.5 to 5.0 V and an output power ranging from 1.25 to 125 mW. The peak voltage conversion ratio and peak PCE were 97.6% and 95.0%, respectively, at RL = 500 Ω.

Design and implementation of fast and hardware‐efficient parallel processing elements to set full and partial permutations in Beneš networks

A new design for parallel and distributed processing elements (PEs) is proposed to configure Beneš networks based on a novel parallel algorithm that can realise full and partial permutations in a unified manner with very little overhead time and extra hardware. The proposed design reduces the hardware complexity of PEs from O ( N 2 ) to O ( N ( lo g 2 N ) 2 ) due to a distributed architecture. In the proposed design, asynchronous operation was introduced in parts to reduce the time complexity per PE stage down to O(1) within a certain N, while it takes O ( lo g 2 N ) time per PE stage in conventional algorithms. A prototype parallel was constructed and PEs were distributed in a field programmable gate array to investigate performance for the switch size of N = 4 to 32. The experimental results demonstrate that the proposed design outperforms a recent method by at least several times in terms of hardware and processing time complexities.