Si-SiO2 Interface Research Articles

Silicon p-i-n Mesa-Photodiode Technology

The paper proposes the technology of silicon p-i-n mesa-photodiodes, which allows to exclude one high-temperature operation from the technological route. Reducing the number of thermal operations reduces the degree of degradation of the electro-physical characteristics of silicon during heat treatment, which also contributes to reducing the density of surface states at the SiSiO2 interface. It is proposed to etch the mesa-profile by the method of chemical-dynamic polishing using a gold masking coating. The obtained photodiodes are cheaper than serial samples made by diffusion-planar technology and have higher sensitivity.

Design and 3D Electrical Simulations for a Controllable Equal-Gap Large-Area Silicon Drift Detector.

In this study, a controllable equal-gap large-area silicon drift detector (L-SDD) is designed. The surface leakage current is reduced by reducing the SiO2-Si interface through the new controllable equal-gap design. The design of the equal gap also solves the problem whereby the gap widens due to the larger detector size in the previous SDD design, which leads to a large invalid area of the detector. In this paper, a spiral hexagonal equal-gap L-SDD of 1 cm radius is selected for design calculation, and we implement 3D modeling and simulation of the device. The simulation results show that the internal potential gradient distribution of the L-SDD is uniform and forms a drift electric field, with the direction of electron drift pointing towards the collecting anode. The L-SDD has an excellent electron drift channel inside, and this article also analyzes the electrical performance of the drift channel to verify the correctness of the design method of the L-SDD.

Effect of Proton Irradiation on Complementary Metal Oxide Semiconductor (CMOS) Single-Photon Avalanche Diodes

The effects of proton irradiation on CMOS Single-Photon Avalanche Diodes (SPADs) are investigated in this article. The I–V characteristics, dark count rate (DCR), and photon detection probability (PDP) of the CMOS SPADs were measured under 30 MeV and 52 MeV proton irradiations. Two types of SPAD, with and without shallow trench isolation (STI), were designed. According to the experimental results, the leakage current, breakdown voltage, and PDP did not change after irradiation at a DDD of 2.82 × 108 MeV/g, but the DCR increased significantly at five different higher voltages. The DCR increased by 506 cps at an excess voltage of 2 V and 10,846 cps at 10 V after 30 MeV proton irradiation. A γ irradiation was conducted with a TID of 10 krad (Si). The DCR after the γ irradiation increased from 256 cps to 336 cps at an excess voltage of 10 V. The comparison of the DCR after proton and γ-ray irradiation with two structures of SPAD indicates that the major increase in the DCR was due to the depletion region defects caused by proton displacement damage rather than the Si-SiO2 interface trap generated by ionization.

Design study and spectroscopic performance of SOI pixel detector with a pinned depleted diode structure for X-ray astronomy

We have been developing silicon-on-insulator (SOI) pixel detectors with a pinned depleted diode (PDD) structure, named “XRPIX”, for X-ray astronomy. The PDD structure is formed in a thick p-type substrate, to which high negative voltage is applied to make it fully depleted. A pinned p-well is introduced at the backside of the insulator layer to reduce a dark current generation at the Si-SiO2 interface and to fix the back-gate voltage of the SOI transistors. An n-well is further introduced between the p-well and the substrate to make a potential barrier between them and suppress a leakage current. An optimization study on the n-well dopant concentration is necessary because a higher dopant concentration could result in a higher potential barrier but also in a larger sense-node capacitance leading to a lower spectroscopic performance, and vice versa. Based on a device simulation, we fabricated five candidate chips having different n-well dopant concentrations. We successfully found out the best n-well design, which suppressed a large leakage current and showed satisfactory X-ray spectroscopic performance. Too low and too high n-well dopant concentration chips showed a large leakage current and degraded X-ray spectroscopic performance, respectively. We also found that the dependency of X-ray spectroscopic performance on the n-well dopant concentration can be largely explained by the difference in sense-node capacitance.

Surface Passivation by Quantum Exclusion: On the Quantum Efficiency and Stability of Delta-Doped CCDs and CMOS Image Sensors in Space.

Radiation-induced damage and instabilities in back-illuminated silicon detectors have proved to be challenging in multiple NASA and commercial applications. In this paper, we develop a model of detector quantum efficiency (QE) as a function of Si-SiO2 interface and oxide trap densities to analyze the performance of silicon detectors and explore the requirements for stable, radiation-hardened surface passivation. By analyzing QE data acquired before, during, and after, exposure to damaging UV radiation, we explore the physical and chemical mechanisms underlying UV-induced surface damage, variable surface charge, QE, and stability in ion-implanted and delta-doped detectors. Delta-doped CCD and CMOS image sensors are shown to be uniquely hardened against surface damage caused by ionizing radiation, enabling the stability and photometric accuracy required by NASA for exoplanet science and time domain astronomy.

Low-temperature deuterium annealing for improved electrical characteristics of SONOS

Deuterium annealing is a promising process technology for CMOS fabrication. Deuterium annealing effectively passivates interface traps at the Si-SiO2 interface, allowing for improvements in the electrical characteristics and reliability of CMOS. However, conventional deuterium annealing is typically performed at high temperatures above 400 °C, which can lead to unwanted dopant deactivation, random dopant fluctuation (RDF), and thermal-induced stress in the backend-of-the-line (BEOL). In this study, we demonstrate the use of deuterium annealing at low temperatures, resulting in improvements in SONOS devices. Device characterizations based on subthreshold swing (SS), on-state current (ION), off-state current (IOFF), and gate leakage current (IG), as well as time-of-flight secondary ion mass spectrometry (ToF-SIMS) are included to clarify the effects of annealing.

Isolation of Responsive Elements of Planar Multi-Element Photodiodes

In the mass production of multi-element silicon p-i-n photodiodes, the problem of systematic rejection of products due to a decrease in the insulation resistance between the active elements of photodetectors has been revealed. The purpose of this work is to study the causes of insulation resistance degradation and to establish optimal methods for avoiding this phenomenon. A comparative analysis of three insulation methods was carried out: classical insulation by the surface of a non-conductive substrate and a dielectric layer; insulation by means of mesaprofile grooves with a dielectric film; insulation by means of areas of limitation of surface leakage channels isotypic with the substrate material (in this case, p+-type) formed in the gaps between active elements. The study found that the reason for the deterioration of the insulation resistance between the active elements of photodiodes is the presence of conductive inversion channels at the Si-SiO2 interface due to the use of silicon with high resistivity. One mechanism for the formation of inversion channels is the redistribution of impurities in the masking oxide (in particular, phosphorus) and their diffusion to the interface during thermal operations. Another mechanism for the formation of inversion layers is the diffusion of boron from silicon into SiO2 during heat treatment due to the fact that the boron segregation coefficient is less than one. In the manufacture of samples with insulation using non-conductive areas of the substrate, a decrease in insulation resistance was observed as the technological route was performed (after each subsequent operation, the resistance degraded). The degree of degradation can be reduced by reducing the duration of thermal operations. It has been shown that reducing the thickness of the masking oxide causes a decrease in insulation resistance. When using mesa-technology, it is possible to increase the insulation resistance by eliminating the high-temperature oxidation operation and, in fact, due to the absence of a masking coating during phosphorus deposition. Insulation by means of p+-type areas in the gaps between the active elements allows to obtain the highest insulation resistance values. The formation of these regions with a width of 100 μm in the gaps with a width of 200 μm allowed us to obtain an insulation resistance of 25-30 MΩ. To ensure the insulation of the active elements of photodiodes by this method, two thermal operations are added to the technological route. The number of thermal operations can be reduced by doping the entire silicon surface with a low boron concentration before forming a masking coating.

The cell-centered Finite-Volume self-consistent approach for heterostructures: 1D electron gas at the Si–SiO2 interface

Achieving self-consistent convergence with the conventional effective-mass approach at ultra-low temperatures (below 4.2 K) is a challenging task, which mostly lies in the discontinuities in material properties (e.g. effective-mass, electron affinity, dielectric constant). In this article, we develop a novel self-consistent approach based on cell-centered finite-volume discretization of the Sturm–Liouville form of the effective-mass Schrödinger equation and generalized Poisson’s equation (FV-SP). We apply this approach to simulate the one-dimensional electron gas formed at the Si–SiO2 interface via a top gate. We find excellent self-consistent convergence from high to extremely low (as low as 50 mK) temperatures. We further examine the solidity of FV-SP method by changing external variables such as the electrochemical potential and the accumulative top gate voltage. Our approach allows for counting electron–electron interactions. Our results demonstrate that FV-SP approach is a powerful tool to solve effective-mass Hamiltonians.

In Ukrainian

Investigating the formation of inversion layers (IL) at the Si-SiO2 interface in the manufacturing technology of silicon photodetectors, some dynamics of dislocations after isothermal annealing were revealed, which were absent in samples without inversion. After selective etching of samples with inversion layers, localization of dislocations on the periphery of responsive elements (RE) with accumulation of guard rings (GR) or other elements of n+-type topology outside the RE was observed. This testified to the movement of dislocations on the surface of the Si-SiO2 structures with IL in the direction of the periphery of the crystal during isothermal annealing, which contributed to a significant decrease in the density of structural defects in RE. The described phenomenon can be used to obtain highly doped defect-free silicon structures. Since the presence of dislocations or other violations of the crystal lattice negatively affect the parameters of the products. In the case of using the described phenomenon as a technological method of “cleaning” the surface of silicon structures, there is a need for controlled formation of IL. One of the methods of forming inversion layers can be thermal oxidation in hydrochloric acid vapors according to the principle of dry-wet-dry oxidation (for p-type silicon). Another method that does not require additional materials is the annealing of Si-SiO2 structures at a temperature of 900–950 Celsium degrees in a nitrogen atmosphere for ≥ 240 minutes. Inversion channels, in this case, will be formed due to the redistribution and diffusion of metal impurities in the oxide (which were introduced during previous thermal operations) to the Si-SiO2 interface. In the described case, these structural defects after annealing were localized in the GR, which is also an active element of the phododiodes, as it limits the dark current of the RE, accordingly, the dark current of the GR should also be low. To be able to implement this method, it is necessary to create passive n+-regions on the periphery of the crystals, limited by oxide, which will be the locations of defects after annealing. It can be both separate areas of arbitrary shape and a concentric ring outside the GR. Elements that will be the locations of defects on the periphery can be cut off at the stage of separating the substrates into crystals. After annealing, it is necessary to remove the IL and form an anti-reflective coating by any known method, since the presence of inversion channels contributes to the growth of dark currents. When examining the morphology of defect localization areas after annealing under high-magnification microscopes and with the help of an atomic force microscope, the formation of hexagonal and round defects, which are partial marginal Frank dislocation loops, was observed. The mechanism of dislocation movement described in this article has not been thoroughly studied by us and requires additional research, but it may be related to Cottrell atmospheres and their interaction with IL

Problems of Masking and Anti-Reflective SiO2 in Silicon Technology

The article examines the problems of thermal oxidation of silicon. Oxidation plays an important role in planar technology, which in turn is the basis of the technology of silicon integrated circuits, photodetectors and other solid-state electronics. During our production of silicon p-i-n photodiodes, a number of systematic types of defects and deterioration of product parameters caused by the degradation of masking or anti-reflective coatings during the manufacturing process were observed. A decrease in the insulation resistance of responsive elements in multi-element photodiodes was observed, which contributed to the increase of dark currents. A decrease in the responsivity of the products due to the degradation of the thickness or structure of the anti-reflective coating during technological operations, etc., was also revealed. It was established that the reason for the decrease in insulation resistance is the formation of inversion layers at the Si-SiO2 interface, the presence of which can be detected when measuring CV-characteristics. It was also established that chemical treatment of substrates with SiO2 in boiling acid solutions helps to reduce the thickness of the oxide. To avoid deviation of the thickness of the film from the condition of minimum reflection, it is necessary to grow a thicker layer of anti-reflective coating. It is noted that when etching the oxide during photolithography or when removing the PSG/BSG in hydrofluoric acid, it is not permissible to remove the cassette with plates from the solution for a long time, as this leads to uneven etching of the film due to the flow of the herb on the surface of the substrate. The causes of defect formation in Si and SiO2 during oxidation are given. Thus, with improper mechanical and chemical processing of the plates, cristobalite inclusions may form in the film during oxidation. Cristobalite has a higher density than quartz glass, and the boundaries between amorphous regions and denser crystalline regions represent voids, which can be filled both by impurities from the surface and by the diffusant in the diffusion process. Also, during oxidation in silicon, packing defects are often formed. Centers of defect genesis can be mechanical damage to the plate surface or growth defects.

Theoretical Investigation of Dual-Material Stacked Gate Oxide-Source Dielectric Pocket TFET Based on Interface Trap Charges and Temperature Variations

In this paper, the performance of dual-material stacked gate oxide-source dielectric pocket-tunnel field-effect transistor (DMSGO-SDP-TFET) has been investigated by considering fixed interface trap charges (ITCs) at the Si–SiO2 interface. During the analysis, both types of trap charges, positive (donor) and negative (acceptor), have been considered to investigate their effect on the DC, analog/ radio frequency, linearity and harmonic distortion performance parameters in terms of the carrier concentration, electric field, band-to-band tunneling rate, transfer characteristics, transconductance ([Formula: see text]), unity gain frequency ([Formula: see text]), gain–bandwidth product, device efficiency ([Formula: see text]/[Formula: see text]), transconductance frequency product, transit time ([Formula: see text]), second- and third-order transconductance and voltage intercept points ([Formula: see text], [Formula: see text], VIP2 and VIP3), third-order Input Intercept Point and Intermodulation Distortion (IIP3, IMD3), second-, third-order and total harmonic distortions (HD2, HD3 and THD), respectively. Further, the impact of temperature variations from [Formula: see text][Formula: see text]K to [Formula: see text][Formula: see text]K in the presence of ITCs is investigated and the results are compared with conventional DMSGO-TFET. In terms of percentage variation, DMSGO-SDP-TFET depicts lower variation than conventional DMSGO-TFET, indicating that the proposed device is more immune to trap charges and can be used for energy-efficient, high-frequency and linearity applications at elevated temperatures.

Silicon four element p-i-n photodiode with improved characteristics

This article presents the results of the development of silicon coordinate p-i-n photodiodes (PD) with improved parameters. The technological possibilities of reducing the gaps between the responsive areas of multi-element PDs were studied. PDs with reduced gaps were modeled, samples were made according to the models, the parameters of the obtained PDs and the influence of various technological factors on their values were investigated. During research, it was established that the factor that limits the possibility of reducing the gaps is the insulation resistance between the responsive elements. The decrease in the insulation resistance between the PD elements was a consequence of the formation of inversion leakage channels at the Si-SiO2 interface, which is characteristic of high-resistance p-type silicon, the conductivity of which increased with a decrease in the width of the gaps. To increase the resistance of the gaps between the platforms and reduce the influence of inversion layers, it was decided to form regions of the restriction of the leakage channels between the REs – highly doped regions isotypic with the substrate material (p+-type). They will prevent the movement of current carriers that are generated in the inversion layers on the surface of the substrate. Four-element p-i-n photodiodes with 31 μm gaps between the sites were made. The proposed PD is not significantly inferior in parameters to analogues, but it is the sample with the smallest gaps between RE among photodiodes of the same type and size in the world market. The improvement of the insulation resistance between the REs made it possible to reduce the level of dark current of the PD by twice compared to serial products, with a slight decrease in responsivity due to the introduction of additional thermal operations into the technological route. In particular, the dark current density of the RE of experimental PDs was 40-80 nA/cm2, compared to 80-250 nA/cm2 for commercial samples. Impulse current monochromatic sensitivity at a wavelength of 1064 nm for experimental samples was 0.41-0.44 A/W, and for commercial ones - 0.45-0.48 A/W.

The Influence of Deep-Level Defects With Various Depths in SiO2 on Ionizing Damage

In this article, we analyzed the interaction mechanism between ionization and displacement defects in SiO2 using experimental and simulation techniques. In the experiment, the gate-controlled lateral p-n-p transistors (GLPNPs) were pretreated by He ions irradiation with different energies, which can create additional oxygen vacancy defects (Vo) at various depth ranges in SiO2. The pretreated GLPNPs were irradiated with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula> -rays to analyze their response to ionization damage. It can be found that the introduction of additional deep Vo in SiO2 weakens the ionization damage of GLPNPs, and this weakening effect is heavily related to the depth of additional deep Vo. In addition, the TCAD simulation tool was used to investigate the mechanism by which the ionization damage is weakened with additional deep Vo depth. The simulation results show that as the additional deep Vo defect approaches the SiO2–Si interface, the additional deep Vo defect enhances the capture of the holes (or release of electrons), resulting in a decrease in hydrogenated Vo ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {Vo}\mathbf {H}_{\mathbf {2}}^{\mathbf {+}}$ </tex-math></inline-formula> ) concentration, which affects the release of protons and ultimately reduces <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N_{\mathrm {it}}$ </tex-math></inline-formula> . Based on the above mechanism, it would be helpful to accurately evaluate the electrical characteristics degradation of bipolar transistors in complex space environments.

Study of the internal quantum efficiency of FBK sensors with optimized entrance windows

Single-photon detection of X-rays in the energy range of 250 eV to 1 keV is difficult for hybrid detectors because of the low quantum efficiency and low signal-to-noise ratio. The low quantum efficiency is caused by the absorption of soft X-rays in the entrance window of the silicon sensors. The entrance window consists of an insensitive layer on the surface and a highly doped layer, which is typically from a few hundred nanometers to a couple of micrometers thick and is comparable to the absorption depth of soft X-ray photons (e.g. the attenuation length of 250 eV X-ray photons is ∼100 nm in silicon). The low signal-to-noise ratio is mainly caused by the small signal amplitude (e.g. ca. 70 electrons for 250 eV X-ray photons in silicon) with respect to the electronic noise. To improve the quantum efficiency, the entrance window must be optimized by minimizing the absorption of soft X-rays in the insensitive layer, and reducing charge recombination at the Si-SiO2 interface and in the highly doped region. Low gain avalanche diodes (LGADs) with a multiplication factor between 5 and 10 increase the signal amplitude and therefore improve the signal-to-noise ratio for soft X-rays, enabling single-photon detection down to 250 eV. Combining LGAD technology with an optimized entrance window technology can thus allow hybrid detectors to become a useful tool also for soft X-ray detection. In this work we present the optimization of the entrance window by studying the internal quantum efficiency of eight different process technology variations. The sensors are characterized using light emitting diodes with a wavelength of 405 nm. At this wavelength, the light has an absorption depth of 125 nm, equivalent to that of 276 eV X-rays. The best variation achieves an internal quantum efficiency of 0.992 for 405 nm UV light. Based on this study, further optimization of the quantum efficiency for soft X-rays detection is planned.

Understanding silicon monoxide gas evolution from mixed silicon and silica powders.

Silicon on silica materials are ubiquitous in 21st century technology. From nanoparticles to integrated circuits, these systems are integral for modern semiconductor fabrication. While the Si-SiO2 interface is often (incorrectly) presumed to be stable, the direct reduction of silica by silicon is possible at high temperatures, resulting in the evolution of silicon monoxide (SiO) gas. Under appropriate conditions, this somewhat unexpected reaction can complicate solid state nanomaterial syntheses by etching away the desired products. This report describes an investigation into the SiO evolution reaction by interrogation of powdered Si-SiO2 mixtures before and after thermal treatment. The impacts of processing temperature, time, and sample composition are examined and discussed. Of particular importance, this investigation reveals the underappreciated role of silica crystallinity (cristobalite) in this solid-state reaction under comparatively low temperature conditions (ca. 1200 °C). With an improved understanding of SiO evolution, we hope to inspire new creative pathways for Si-SiO2 interface manipulation.

First characterization results of ARCADIA FD-MAPS after X-ray irradiation

The ARCADIA collaboration is developing fully-depleted (FD) Monolithic Active Pixel Sensors (MAPS) in a 110 nm CMOS process in collaboration with LFoundry. The sensor design incorporates an n+ collection node within a n-type epi-layer on top of a high-resistivity n-type substrate and p+ backside. Thus, the pn-junction sits on the backside and through an applied backside bias, the full substrate gets depleted. The targeted applications of this technology range from future high energy physics experiments to space applications, and medical and industrial scanners. Together, these applications set the minimum requirements on the detector: data collection at hit rates of (10–100) MHz/cm2, full signal processing within (1–10) μs, maximum power consumption (5–20) mW/cm2 and radiation tolerances of up to 3.4 Mrad or 6.2 × 1012 1 MeV neutron equivalent fluence. In order to proof the performance of the technology, a demonstrator chip of 512 × 512 pixels with 25 μm pitch was designed and fabricated in a first engineering run in 2021, together with additional test structures of pixel and strip arrays with different pitches and sensor geometries. The production run has produced functional passive and active pixel matrices. Earlier studies have shown that positive oxide charges and traps at the Si-SiO2 interface, introduced by ionising radiation, affect the depletion region around the collection electrode, increasing the pixel capacitance. By varying the gap size between collection node and pwells, the geometry can be optimised to keep the capacitance low also after irradiation. To study the performance after irradiation, of the optimised diode designs, the passive pixel matrices were irradiated with doses up to 10 Mrad (SiO2) using a X-ray tube with a Tungsten anode. The measurements are complemented by TCAD simulations. The maximum capacitance increase after irradiation was found to reach 6 and 12 fF/pixel for pixel pitches of 25 and 50 μm, respectively. The relative capacitance increase after irradiation has hereby been found to reach up to 250% after a dose of 10 Mrad.

Влияние ловушек на накопление подвижного заряда в МОП-структурах при термополевых обработках

A quantitative model describing the influence of traps on the parameters of mobile charge migration in the gate dielectric of MOS structures is presented. The dependences of the effective diffusion coefficients and activation energy on trap accumulation, ion-trapping binding energy, impurity concentrations, and thermal field treatment temperatures are calculated. An increase in trap concentration was found to hamper mobile charge accumulation in the vicinity of the Si-SiO2 interface. The presented model can be used to explain the scattering of experimental data on sodium ion diffusion in silicon dioxide.

LOCALIZATION OF NITROGEN ATOMS IN Si–SiO2 STRUCTURES

Studies have been carried out by time-of-flight mass spectroscopy of secondary ions of subcutaneous silicon&#x0D; oxides, nitridation by ion implantation (II) or nitrided by high-temperature annealing in an atmosphere of N2. Nitrogen&#x0D; AI was produced with an energy of 40 keV, implantation doses of 2,5×1014 and 1×1015 cm-2. High-temperature&#x0D; annealing was carried out at a temperature of 1200 C for 2 hours or at 1100 C for 30 minutes. It is established&#x0D; that at the Si–SiO2 interface, after nitriding by II or high-temperature annealing, a maximum with a high concentration&#x0D; of nitrogen atoms is observed. It is shown that after conducting nitrogen AI with a dose of 2,5 ×1014 cm-2&#x0D; through a protective SiO2 with a thickness of 23 nm and RTA at 1000 C for 15 seconds, the main maximum&#x0D; of nitrogen distribution (1×1019 cm-3) is observed at the Si–SiO2 interface, which indicates the presence of a saturation&#x0D; concentration of the Si–SiO2 interface.&#x0D; &#x0D; A charge-based one-dimensional Fermi model is proposed to describe the accelerated diffusion of nitrogen&#x0D; atoms. The main mechanism is the diffusion of interstitial atoms, which can occur with the preliminary displacement&#x0D; of nodal nitrogen atoms by their own embedding atoms. It is shown that nitrogen atoms can act as annihilation&#x0D; centers of point defects in the silicon crystal lattice.

Optimal Design of Multiple Floating Rings for 3D Large-Area Trench Electrode Silicon Detector.

The 3D electrode silicon detector eliminates the limit of chip thickness, so it can reduce the electrode spacing (small area) and effectively improve the radiation hardness. In order to expand the application range of the 3D electrode detector, we first propose a 3D large-area silicon detector with a large sensitive volume, and realize multiple floating rings on the upper and lower surfaces of the detector. Due to the influence of different charge states and energy levels in the Si-SiO2 interface system, the top and bottom of the 3D P+ electrode are more prone to avalanche breakdown in the 3D large-area detector before the detector is completely depleted or the carrier saturation drift velocity is reached. Moreover, the electric field distribution becomes very uneven under the influence of the oxide charge, resulting in non-equilibrium carriers that cannot drift in the optimal path parallel to the detector surface. In this paper, the effect of floating rings on the performance of a 3D large-area silicon detector is studied by TCAD simulation. It can increase avalanche breakdown voltage by 14 times in a non-irradiated environment, and can work safely in a moderate irradiated environment. The charge collection efficiency can be effectively improved by optimizing the drift path.

Analysis and optimal design of surface radiation hard p+n Si pixel detector: impact on signal collection using TCAD simulation

Surface radiation hard p+n Si pixel detectors are required for the science experiment at a synchrotron, and the major challenge is to improve the charge collection efficiency in the high-voltage X-ray-irradiated Si pixel detectors. Several experiments have been performed at DESY, Hamburg, Germany, within the AGIPD consortium on the test structures to extract the microscopic parameters of the X-ray-induced surface radiation damage in the detectors. The results on the microscopic parameters are fed into Cogenda Visual TCAD commercial simulation program to compare the experimental results and simulation data. A very good agreement has been recorded between the results and simulation data. In this paper, several surface radiation hard p+n Si pixel design options have been explored using a microscopic model for the improvement in the high-voltage stability of the detector and high-charge collection efficiency. A new intra-guard ring is incorporated in the design of the two adjacent p+ pixels equipped with symmetric in and outward metal overhang extensions. The proposed surface radiation hard optimal design can enhance the electric field in the gutter region of the n-Si-bulk, a region which can have a very low electric field, which is just below the Si-SiO2 interface of the detectors, and this is the major concern for the charge loss in the X-ray-irradiated detectors. The results are discussed in detail using electric field distribution in the different designs of the pixel detectors for the different X-ray doses, and an optimized p+n Si pixel detector design with an intra-guard ring structure is proposed for the experiment.