Sinusoidal Clock Research Articles

2-Phase Adiabatic Logic for Low-Energy and CPA-Resistant Implantable Medical Devices

Designing a low-energy and secure lightweight cryptographic coprocessor is the primary design constraint for modern wireless Implantable Medical Devices (IMDs). The lightweight cryptographic ciphers are the preferred cryptographic solution for low-energy encryption. This article proposes 2-SPGAL, the 2-phase sinusoidal clocking implementation of Symmetric Pass Gate Adiabatic Logic (SPGAL) for IMDs. The proposed 2-SPGAL is energy-efficient and secure against the Correlation Power Analysis (CPA) attack. The proposed 2-SPGAL was evaluated with the integration of synchronous resonant Power Clock Generators (PCGs): (i) 2N2P-PCG, and (ii) 2N-PCG. The case study implementation of one round of PRESENT-80 encryption using 2-SPGAL, with 2N2P-PCG integrated into the design, shows an average of 47.50% of energy saving compared to its CMOS counterpart, over the frequency range of 50 kHz to 250 kHz. The same 2-SPGAL based case study, with 2N-PCG integrated into the design, shows 51.18% of an average energy saving compared to its CMOS counterpart, over 50 kHz to 250 kHz. Further, the 2-SPGAL based PRESENT-80 one round shows an average energy saving of 16.62% and 28.90% respectively for 2N2P-PCG and 2N-PCG integrated into the design compared to existing 2-phase adiabatic logic called 2-EE-SPFAL. We also subjected PRESENT-80 design of 2-SPGAL and CMOS against CPA attack. The 2-SPGAL, with 2N2P-PCG and 2N-PCG, integrated into one round of PRESENT-80 design protects the encryption key. However, the encryption key was successfully revealed in one round of PRESENT-80 design using CMOS logic. Therefore, the proposed 2-SPGAL logic can be useful to design energy-efficient and CPA resilient Implantable Medical Devices (IMDs).

Low Power Adiabetic Logic System for Biomedical Applications

There have been significant advances in sensors and device structures in the medical industry, particularly in implanted medical devices. Increasingly complex electronic circuitry may now be implanted in the human body thanks to compact, high-energy batteries and hermetic packaging. These gadgets must adhere to strict power consumption guidelines due to the battery recharging schedule. Designing energy-efficient circuits and systems becomes increasingly important as a result of this fact. Adiabatic circuits provide a hopeful alternative for traditional circuitry in case of low energy design. Because of power-clock phases synchronization complexity, designing and functionally verifying presenting 4-phase adiabatic circuitry takes longer. Accordingly, multiple clock generators are used typically and can reveal enhanced consumption of energy in the network of clock distribution. Furthermore, they are not suitable for designing in high-speed because of their clock skew management and high complexity issues. In this paper, TMEL (True multi-phase energy recovering logic), the first energyrecovering/adiabatic logic family is presented for biomedical applications, which functions using the scheme multiple-phase sinusoidal clocking. Moreover, a system of SCAL, a source-coupled variation with TMEL having enhanced energy efficiency and supply voltage scalability, is introduced. A novel true multi-phase Approach and Source-coupled adiabatic logic for energy effective communication system is proposed. The adiabatic logic is employed for both write and read side operation. The CMOS inverter is integrated with TMEL cascades, which in turn reduces leakage loss. In SCAL, the optimal performance at any operating circumstance is attained byan adjustable current source in each gate. SCAL, and TMEL, are capable of outperforming existing adiabatic logic families concerning operating speed and energy efficiency. The performance analysis was carried and simulated through 45 nm CMOS inverter in terms of leakage power, delay, and power consumption. In particular, for the clock rates that range from 10 MHz to 200 MHz, the proposed SCAL was more energy-efficient and less dissipative on comparing their pipelined or purely combinational CMOS counterparts. In biomedical equipment, the system may be included into the low-power design since it is energy efficient and very robust. Improvements in VLSI technology, such as increased dynamic range, low-voltage EEPROMs (electrically eraseable programmable ROMs), and specific sensor techniques, are also expected to contribute to advancements in implanted medical devices in the near future.

Minimum shift keying based protection mode capable wavelength division multiplexed passive optical network optical overlay system

We explored the functioning of an optical overlay of multicast and unicast data streams on a survival wavelength division multiplexed passive optical network using intensity and minimum shift keying modulation for both single and multiuser. In optical line terminal, using a sinusoidal clock, optical subcarriers are generated not only to carry the multicast and unicast data streams simultaneously but also in case of fiber failure, protection mode is enabled to carry the data streams smoothly. Here, 10 Gbps downstream multicast in normal mode and unicast signals both in normal and protection mode are transmitted error-free through 30 km dispersion shifted fiber. In both the cases 10 Gbps upstream signal is modulated and sent back to the optical line terminal. For single user nearly similar power penalty is witnessed for downstream unicast as well as re-modulated upstream data in both the conditions and also when multicast data is disabled. The power penalties between single and multiuser for both the modes are found to be approximately 0.06, 0.42 and 0.7 dB for unicast MSK, multicast and upstream respectively.

Wavelength division multiplexed passive optical network-based optical overlay of two multicast/one unicast data using intensity modulation/minimum shift keying

We simulated and investigated the performance of optical overlay of two multicast and a unicast data on a wavelength division multiplexed passive optical network using intensity and minimum shift keying modulation. In an optical line terminal (OLT), three optical subcarriers are generated from a single sinusoidal clock to carry two independent 10-Gbps multicast data and one 10-Gbps unicast data through dispersion-shifted fiber. At the same time, another 10-Gbps data are remodulated and transmitted back to the OLT. Error-free transmission is achieved and almost the same power penalty is observed for the downstream unicast as well as the remodulated upstream data irrespective of whether either one or both of the multicast data are enabled or disabled.

Low power combinational and sequential logic circuits using clocked differential cascode adiabatic logic (CDCAL)

This paper presents the Clocked Differential Cascode Adiabatic Logic (CDCAL), the quasi-adiabatic dynamic logic that can operate efficiently at GHz-class frequencies. It is operated by two phase sinusoidal power clock signal for the adiabatic pipeline. The proposed logic uses clocked control transistor in addition to the less complex differential cascode logic structure to achieve low power and high speed operation. To show the feasibility of implementation of both combinational and sequential logic circuits using the proposed logic, the CLA adder and counter have been selected. To evaluate the energy efficiency of the proposed logic, an 8-bit pipelined carry look-ahead (CLA) adder is designed using CCDAL and it is also compared against the other high speed two phase counterpart available in the literature and conventional static CMOS. The simulation results show that the CCDAL logic can operate efficiently at high frequencies compared to other two phase adiabatic logic circuits. All the circuits have been designed using UMC 90nm technology library and the simulations are carried out using industry standard Cadence® Virtuoso tool.

Low-Power Resonant Clocking Using Soft Error Robust Energy Recovery Flip-Flops

An energy recovery or resonant clocking scheme is very attractive for saving the clock power in nanoscale ASICs and systems-on-chips, which have increased functionality and die sizes. The technology scaling followed Moore’s law, that lowers node capacitance and supply voltage, making nanoscale integrated circuits more vulnerable to radiation-induced single event upsets (SEUs) or soft errors. In this work, we propose soft-error robust flip-flops (FFs) capable of working with a sinusoidal resonant clock to save the overall chip power. The proposed conditional-pass Quatro (CPQ) FF and true single phase clock energy recovery (TSPCER) FF are based on a unique soft error robust latch, which we refer to as a Quatro latch. The proposed C2-DICE FF is based on a dual interlocked cell (DICE) latch. In addition to the storage cell, each FF consists of a unique input-stage and a two-transistor, two-input output buffer. In each FF with a sinusoidal clock, the transfer unit passes the data to the Quatro and DICE latches. The latches store the data values at two storage nodes and two redundant nodes, the latter enabling recovery from a particle-induced transient with or without multiple-node charge sharing. Post-layout simulations in 65nm CMOS technology show that the FF exhibits as much as 82% lower power-delay product compared to recently reported soft error robust FFs. We implemented 1024 proposed FFs distributed in an H-tree clock network driven by a resonant clock-generator that generates a 1–5 GHz sinusoidal clock signal. The simulation results show a power reduction of 93% on the clock tree and total power saving of up to 74% as compared to the same implementation using the conventional square-wave clocking scheme and FFs.

Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL)

This paper presents the quasi-adiabatic logic for low power powered by two phase sinusoidal clock signal. The proposed logic called two phase adiabatic dynamic logic (2PADL) realizes the advantages of energy efficiency through the use of gate overdrive and reduced switching power. It has a single rail output and the proposed logic does not require the complementary input signals for any of its variables. The 2PADL logic is operated by two complementary clock signals acting as power supply. The validation of the proposed logic is carried out through practical circuits such as (i) sequential circuits using energy recovery technique suitable for memory circuits, (ii) an adiabatic carry look ahead adder (CLA) designed using 2PADL to study the speed performance and to prove its energy efficiency across a range of frequencies and (iii) a multiplier circuit using 2PADL compared against CMOS counterpart. The CLA adder is also implemented using the other static adiabatic logics, namely, quasi static energy recovery logic (QSERL), clocked CMOS adiabatic logic (CCAL) and conventional static CMOS logic to compare against 2PADL and validate its power advantages. The performance of the CCAL logic is tested for higher frequencies by implementing the widely presented CLA circuit. The result proves that the design is energy efficient and operates up to the frequency of 600 MHz. The simulation was carried out using industry standard Cadence® Virtuoso tool using 180[Formula: see text]nm technology library files.

Multicast-enabled survivable architecture for wavelength-division-multiplexed passive optical networks

We propose and experimentally demonstrate a multicast-enabled survivable architecture for wavelength-division-multiplexed passive optical networks. By manipulating the sinusoidal control clock and the wavelength of the light source for each downstream wavelength channel at the optical line terminal, different optical subcarriers are generated to provide subscribers with not only multicast data transmission but also survivability against fiber failure in either distribution or feeder fibers. The simultaneous transmissions of 10-Gb/s unicast data and 10-Gb/s multicast data under normal working mode, as well as the 10-Gb/s transmissions for unicast data under protection mode, are experimentally demonstrated.

Design and Analysis of 32-Bit CLA Using Energy Efficient Adiabatic Logic for Ultra-Low-Power Application

This paper shows that a conventional semi-custom design-flow based on a energy efficient adiabatic logic (EEAL) cell library allows any VLSI designer to design and verify complex adiabatic arithmetic units in a simple way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom EEAL-based 32-bit carry-lookahead adder (CLA) has been designed in a TSMC 90-nm CMOS process technology and verified by CADENCE Design suite. Differential cascode voltage swing (DCVS) logic has been used to implement the newly proposed EEAL and it uses only a sinusoidal clock supply to ensure correct operation. Post-layout simulations show that semi-custom adiabatic arithmetic units can save significant amount of energy, as compared to the previously reported single clocked adiabatic logic and logically equivalent static CMOS implementation. Extensive CADENCE simulations have been done for the verification of the functionality of the proposed logic structure.

Generation of a frequency sextupled optical millimeter wave with a suppressed central carrier using one single-electrode modulator

We have theoretically and experimentally investigated the generation of optical millimeter wave (mm-wave) generation based on a quadrupling and sextupling technique using one single-electrode intensity modulator (IM) with a simultaneously suppressed optical central carrier. By adjusting the bias voltage and utilizing proper peak-to-peak voltage of the RF signal drive on the IM, undesired sidebands can be suppressed. Based on this rule, an experiment was performed to generate 48 and 72-GHz optical mm-waves using a sinusoidal clock source running at only 12GHz.

SINUSOIDAL CLOCKED SENSE-AMPLIFIER-BASED ENERGY RECOVERY FLIP-FLOPS

Energy recovery clocking is an ultimate solution to the ultra low power sequential digital circuit design. In this paper, we present a new slave latch for a sense-amplifier based flip-flop (SAFF). Energy recovery sinusoidal clock is applied to the low power SAFF. Extensive simulation based comparisons among reported and proposed SAFF are carried-out at 90 nm CMOS technology node. The proposed flip-flop operating with energy recovery single phase sinusoidal clock shows better performance. The proposed flip-flop also reduces the leakage current and glitch.

Simultaneous switching noise reduction by resonant clock distribution networks

Resonant clock distribution networks are known as low-power alternatives for conventional power-hungry buffer-driven clock networks. In this paper, we investigate the simultaneous switching noise (SSN) in a resonant clock network compared to that in conventional clocking. Analytical and simulation results show that employing the clock generated by a resonant clock network reduces the SSN voltage on power supply rails. The main drawback of using a sinusoidal clock is that the short-circuit power increases in the clocked devices. This problem is also investigated and discussed analytically.

Optical Overlay of Multicast Stream on a Survivable WDM Passive Optical Network

We propose a novel scheme to perform an optical multicast overlay on a survivable wavelength division multiplexed passive optical network. By flexibly controlling a sinusoidal clock signal and an optical switch at the optical line terminal, optical sub-carriers, which enable not only protection for distribution and feeder fibers, but also multicast data delivery, are generated. 10-Gb/s transmissions under both normal working and protection modes are experimentally demonstrated.

Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks

In this paper we introduce a new flip-flop for use in a low- swing LC resonant clocking scheme. The proposed low-swing differential conditional capturing flip-flop (LS-DCCFF) operates with a low-swing sinusoidal clock through the utilization of reduced swing inverters at the clock port. The functionality of the proposed flip-flop was verified at extreme corners through simulations with parasitics extracted from layout. The LS-DCCFF enables 6.5% reduction in power compared to the full- swing flip-flop with 19% area overhead. In addition, a frequency dependent delay associated with driving pulsed flip-flops with a low-swing sinusoidal clock has been characterized. The LS-DCCFF has 870 ps longer data to output delay as compared to the full-swing flip-flop at the same setup time for a 100 MHz sinusoidal clock. The functionality of the proposed flip-flop was tested and verified by using the LS-DCCFF in a dual-mode multiply and accumulate (MAC) unit fabricated in TSMC 90-nm CMOS technology. Low-swing resonant clocking achieved around 5.8% reduction in total power with 5.7% area overhead for the MAC.

1.1 TMACS/mW Fine-Grained Stochastic Resonant Charge-Recycling Array Processor

We present a resonant adiabatic mixed-signal 128 × 256 array processor that achieves the energy efficiency of 1.1 TMACS (1012 multiply accumulates per second) per mW of power operating from a 1.6 V DC supply. The 1.9 μm × 9 μm 3T NMOS unit cell with a single-wire pitch multiplexed bit/compute line provides charge-conserving 1b-1b multiplication and single-node charge-domain analog accumulation. A stochastic data modulation scheme minimizes on-chip capacitance variability maintaining sinusoidal clock oscillations near resonance.

A phase stable short pulse generator using a DPMZM and phase modulators for application in 160 GBaud DQPSK systems

A method of 40GHz phase stable short pulses generation is experimentally demonstrated. It is based on a dual parallel Mach–Zehnder modulator (DPMZM) driven by only one electrical sinusoidal clock and two cascaded phase modulators. The generated pulses are characterized with full-width-at-half-maximum pulse width of 1.9ps, extinction ratio of 27dB, timing jitter of 36fs and signal to noise ratio over 30dB. The high quality and phase stability of the pulses are further experimentally verified in a 4×40 GBaud differential quadrature phase shift keying (DQPSK) optical-time-division-multiplexing (OTDM) system.

A novel WDM passive optical network architecture supporting two independent multicast data streams

We propose a novel scheme to perform optical multicast overlay of two independent multicast data streams on a wavelength-division-multiplexed (WDM) passive optical network. By controlling a sinusoidal clock signal and shifting the wavelength at the optical line terminal (OLT), the delivery of the two multicast data, being carried by the generated optical tones, can be independently and flexibly controlled. Simultaneous transmission of 10-Gb/s unicast downstream and upstream data as well as two independent 10-Gb/s multicast data was successfully demonstrated.

Sinusoidal Clock Sampling for Multigigahertz ADCs

Current multigigahertz ADC performance is limited by the sampling clock timing jitter. This paper describes the effects of clock transition time on the spurious-free dynamic range (SFDR) of a CMOS T/H circuit. A signal-dependent nonlinearity model is first introduced that provides insight on the effect of finite clock transition time, and presents the use of sinusoidal signal as the sampling clock to improve SFDR. Whereas a square-wave clock exhibits a shorter transition time but more jitter susceptibility, sinusoidal clocking provides a longer transition time but a lower jitter spectrum. To verify this concept, an 8 GS/s, 4b flash ADC with a sinusoidal clock is designed and experimentally measured, achieving a figure-of-merit of 0.86 pJ/conv-step based upon effective resolution bandwidth (ERBW), and 0.2 pJ/conv-step based upon sampling rate.

Optical Overlay of Two Independent Multicast Streams on a WDM Passive Optical Network

We propose a novel scheme to perform optical multicast overlay of two independent multicast data streams on a wavelength-division-multiplexed passive optical network. By controlling a sinusoidal clock signal and an optical switch at the optical line terminal, the delivery of the two multicast data, being carried by the generated optical tones, can be independently and flexibly controlled. Simultaneous transmissions of 10-Gb/s unicast downstream and upstream data as well as two independent 10-Gb/s multicast data are successfully demonstrated.

Skew compensation in energy recovery clock distribution networks

In this study a new approach for skew compensation in energy recovery clock distribution networks is introduced by manipulating the operating speed of the flip-flops. The STMicroelectronics 90 nm technology allows the use of devices with different threshold voltages, namely: high threshold voltage (HVT), standard threshold voltage (SVT) and low threshold voltage (LVT). Three types of flip-flops of equal input load: fast , standard and slow are used. Timing parameters of the flip-flops are adjusted by manipulating the switching threshold of the clock port of the flip-flops. A fast/slow flip-flop has a shorter/longer T DQ delay, compared with a standard flip-flop for the same setup time (T DCLK ). Distributing flip-flops according to their delay requirements would reduce the effect of the clock's skew on the outputs of sequentially adjacent flip-flops. Owing to the slow rise time of the sinusoidal clock signal used in energy recovery clock distribution networks compared to the conventional square-wave clock, the skew that can be compensated for in energy recovery clock distribution networks using this approach would be much higher than in square-wave clock distribution networks. This approach increases the skew bounds required by algorithms to balance the skew in the clock tree leading to reduced design complexity. Theoretical analysis and simulation results using STMicroelectronics 90 nm technology at a clock frequency of 500 MHz show that this approach is feasible and effective where a skew of up to 6.2% 1of the clock period can be compensated for in the example used. In addition, constructing clock trees using the skew slack provided in the proposed technique in a new modified differed merge embedding (DME) algorithm on five benchmarks have shown that the proposed technique enables an average reduction of 11.5% in total wire length and 53.2% reduction in the number of wire elongations. Balancing the skew in the clock tree using buffers was not considered here since inserting a buffer in the clock's path eliminates the energy recovery property. As an example of illustrating the proposed methodology, the authors have used the Elmore delay model with a selected energy recovery flip-flop to verify the practicality of the proposed scheme. Better results can be obtained by using different flip-flops. The method can generally be applied to energy recovery or square-wave clocking if different flip-flops of various speeds are used.