Single Wafer Research Articles

Prediction Model of Material Removal for Polishing Single Crystal Silicon by Cluster Magnetorheological Finishing with Dynamic Magnetic Fields Based on BP Neural Network

Magnetorheological Finishing (MRF) is a new optical surface processing method, which has the advantages that good polishing effect, no subsurface damage, and suitable for complex surface processing. However, the interaction mechanism between the MRF pad and the workpiece is very complicated, so that the existing MRF material removal theoretical model is not accurate enough to establish the relationship between polishing parameters and material removal. In order to improve the processing efficiency and explore the material removal mechanism, a cluster magnetorheological finishing (CMRF) with dynamic magnetic fields method was proposed. Studying CMRF with dynamic magnetic fields material removal model is helpful to explain the removal mechanism more deeply, and improve the processing efficiency. In this study, the CMRF method was used to conduct a multi-factor orthogonal test on 2-inch single crystal silicon wafers. Based on the empirical Preston equation, the relationship between the machining gap and the polishing pressure was explained. Orthogonal experiments were done for a series of speeds, and obtaining the order of the influence of various factors on the average surface roughness <i>Ra</i> of the workpiece was: workpiece rotation speed > polishing disk speed > magnetic poles rotation speed > oscillating speed; the material removal rate (<i>MRR</i>) was: polishing disk speed > workpiece rotation speed > magnetic poles rotation speed > oscillating speed. Then combining with the orthogonal experimental data, and taking the surface roughness <i>Ra</i> and <i>MRR</i> as evaluation criteria, using Adam (Adaptive momentum) optimization algorithm to build a prediction model of <i>Ra</i> and <i>MRR</i> for polishing single crystal silicon by CMRF with dynamic magnetic fields based on BP neural network. For the prediction result, <i>Ra</i> of the maximum error was 7.05%, the minimum was 0.31%; <i>MRR</i> of the maximum error was 10.22%, the minimum was 1.32%. Therefore, the feasibility of this model for predicting the results of CMRF was verified, and it laid a good foundation for the development of CMRF technology and its industrial application.

Effective-medium-cladded dielectric waveguides for terahertz waves.

Terahertz integrated platforms with high efficiency are crucial in a broad range of applications including terahertz communications, radar, imaging and sensing. One key enabling technology is wideband interconnection. This work proposes substrate-less all-dielectric waveguides defined by an effective medium with a subwavelength hole array. These self-supporting structures are built solely into a single silicon wafer to minimize significant absorption in metals and dielectrics at terahertz frequencies. In a stark contrast to photonic crystal waveguides, the guiding mechanism is not based on a photonic bandgap but total internal reflections The waveguides are discussed in the context of terahertz communications that imposes stringent demands on performance. Experimental results show that the realized waveguides can cover the entire 260-400 GHz with single dominant modes in both orthogonal polarizations and an average measured attenuation around 0.05 dB/cm. Limited by the measurement setup, the maximum error-free data rate up to 30 Gbit/s is experimentally achieved at 335 GHz on a 3-cm waveguide. We further demonstrate the transmission of uncompressed 4K-resolution video across this waveguide. This waveguide platform promises integration of diverse active and passive components. Thus, we can foresee it as a potential candidate for the future terahertz integrated circuits, in analogy to photonic integrated circuits at optical frequencies. The proposed concept can potentially benefit integrated optics at large.

Integrated Photonic Platform for Rare-Earth Ions in Thin Film Lithium Niobate.

Rare-earth ion ensembles doped in single crystals are a promising materials system with widespread applications in optical signal processing, lasing, and quantum information processing. Incorporating rare-earth ions into integrated photonic devices could enable compact lasers and modulators, as well as on-chip optical quantum memories for classical and quantum optical applications. To this end, a thin film single crystalline wafer structure that is compatible with planar fabrication of integrated photonic devices would be highly desirable. However, incorporating rare-earth ions into a thin film form-factor while preserving their optical properties has proven challenging. We demonstrate an integrated photonic platform for rare-earth ions doped in a single crystalline thin film lithium niobate on insulator. The thin film is composed of lithium niobate doped with Tm3+. The ions in the thin film exhibit optical lifetimes identical to those measured in bulk crystals. We show narrow spectral holes in a thin film waveguide that require up to 2 orders of magnitude lower power to generate than previously reported bulk waveguides. Our results pave the way for scalable on-chip lasers, optical signal processing devices, and integrated optical quantum memories.

Evaluation of the Topographical Surface Changes of Silicon Wafers after Annealing and Plasma Cleaning

The morphological stability of silicon single crystal wafers was investigated, after performing cleaning surface treatments based on moderate temperature annealing and plasma sputtering. The wafer surfaces were measured by Tapping mode atomic force microscopy in air, before and after the different treatments. The 3D images were segmented by watershed algorithm identifying the local peaks, and the stereometric parameters were extracted thereof. The analysis of variance allowed to better assess the statistically significant differences. All the resulting quantities were critically discussed. It appeared that the different cleaning treatments affected differently the surface morphology changes occurring between pristine and treated surfaces, making them distinguishable in these terms. The presented combination of measurement technique and analyzing protocol potentially allows one to assess the structural differences of the surfaces of interest, when assumptions are made about the physical origin of the emerging topographical features. In the present case, if no etching is assumed, it appears that all cleaning protocols actually worsen the surface quality. The effect of these morphological differences on the functional properties of the surface should be ascertained independently.

Transmitting volume Bragg grating with longitudinal moiré apodization

The apodized transmitting volume Bragg grating (TVBG) with the amplitude of the refractive index modulation (RIM) dropped to zero at both the surfaces is discussed. The proposed method for apodization is based on the recording of two identical uniform TVBGs with slightly different directions of their Bragg wave vectors in a single wafer. As a result, slow sinusoidal moire modulation occurs in the direction perpendicular to the averaged direction of the two wave vectors of Bragg modulation. The cutting of a specimen at the planes of the two closest zeros of the moire envelope produces the apodized TVBG. The longitudinal sinusoidal semi-period profile of RIM requires its specific maximum value to achieve 100% diffraction efficiency at the exact Bragg condition. Such an apodized TVBG demonstrates a significant suppression of the sidelobes in the diffraction efficiency depending on the angular or the wavelength detuning, in comparison to the diffraction operation of a uniform TVBG.

Rotational plating process design with computational fluid analysis

During the semiconductor manufacturing process and equipment development, we designed a face-up type electro-plating process and equipment including technologies of single wafer processing, wafer handling, and cyclic fluid delivery. In this study, with the help of computational fluid dynamics, we presented the flow effect on the wafer from the viewpoint of the coating uniformity. Process and hardware parameters, such as the electrode rotating speed, the gap between the electrode and the wafer, and the electrode shape were considered. The electrode height of 10 mm exhibited the best results, and this may be caused by the shoulder gap location to the outlet duct. A rotating speed of 5 rpm was shown to produce better results than those at other speeds. The butterfly wing and the meshed disk electrode showed a similar tendency in terms of the rotating speed and the gap. However, the butterfly-wing-type might show less uniform results than those of the meshed disk due to its original non-uniformity in the circumferential direction in case of lower rotating speed.

Novel fabrication for vertically stacked inverted triangular and diamond-shaped silicon nanowires on (1 0 0) single crystal silicon wafer

The vertical integration of multiple silicon nanowires (multi-SiNWs) has an outstanding ability to enhance drive current, sensitivity and noise immunity by maximizing nanowire density. However, the crystal plane of the SiNW prepared by the present technology for the vertical stacked integration is indeterminate and has plasma damage. In this paper, a novel fabrication method for vertically stacked SiNWs with inverted triangular and diamond-shaped cross-sections on (1 0 0) single crystal silicon wafer is developed and presented, using conventional micromachining processes. The fabrication is based on the crystal plane distribution and anisotropic etching characteristics of (1 0 0) single crystal silicon. An iteration process of self-aligned dry etching and wet etching is first designed to form vertically stacked triangular and diamond-shaped silicon columns. After thermal oxidation thinning and removal of the oxide layer, the vertically stacked triangular and diamond-shaped SiNWs without plasma damage are obtained in the double silicon columns. The vertically integrated approach not only precisely controls the position and shape of the SiNWs but also determines the crystal plane and orientation of the SiNWs. In addition, the triangular and diamond-shaped SiNWs have a larger surface-to-volume ratio than circular and rectangular-shaped SiNWs with the same cross-sectional area and the same length. Therefore, this method can provide a novel, controllable, and economical way to vertically stack more SiNWs with larger surface-to-volume ratio into one chip for high-performance device applications.

Preparation and characterization of AlN seeds for homogeneous growth

Large size AlN bulk crystal has been grown on SiC heterogeneous seed by physical vapor transport (PVT). The properties of AlN wafer were characterized by high resolution X-ray diffraction (HRXRD), Raman spectroscopy, etched method and atomic force microscope (AFM). Growth mechanism of AlN crystal grown on heterogeneous SiC seeds was proposed. Crystallization quality of AlN samples were improved with the growth process, which is associated with the growth mechanism. AlN single wafer has excellent crystallization quality, which is indicated by HRXRD showing the (0002), ( ) XRD FWHM of 76.3, 52.5 arcsec, respectively. The surface of the AlN wafer is measured by AFM with a roughness of 0.15 nm, which is a promising seed for AlN homogeneous growth.

Characteristics and Processing of Hydrogen-Treated Copper Powders for EB-PBF Additive Manufacturing

The fabrication of high purity copper using additive manufacturing has proven difficult because of oxidation of the powder feedstock. Here, we present work on the hydrogen heat treatment of copper powders for electron beam powder bed fusion (EB-PBF), in order to enable the fabrication of high purity copper components for applications such as accelerator components and vacuum electronic devices. Copper powder with varying initial oxygen contents were hydrogen heat-treated and characterized for their chemistry, morphology, and microstructure. Higher initial oxygen content powders were found to not only reduce surface oxides, but also reduce oxides along the grain boundaries and form trapped H2O vapor inside the particles. The trapped H2O vapor was verified by thermogravimetric analysis (TGA) and residual gas analysis (RGA) while melting. The mechanism of the H2O vapor escaping the particles was determined by in-situ SEM heated stage experiments, where the particles were observed to crack along the grain boundaries. To determine the effect of the EB-PBF processing on the H2O vapor, the thermal simulation and the validation of single melt track width wafers were conducted along with melting single layer discs for chemistry analysis. A high speed video of the EB-PBF melting was performed in order to determine the effect of the trapped H2O vapor on the melt pool. Finally, solid samples were fabricated from hydrogen-treated copper powder, where the final oxygen content measured ~50 wt. ppm, with a minimal residue hydrogen content, indicating the complete removal of trapped H2O vapor from the solid parts.

Shedding X-ray Light on the Interfacial Electrochemistry of Silicon Anodes for Li-Ion Batteries.

Electrochemical alloying reactions of group IV elements, such as Si, Ge, or Sn, with lithium provide a promising route to next-generation anode materials for lithium-ion batteries (LIBs) due to their high volumetric and gravimetric capacities. However, commercialization of these anodes is still sparse owing to quick capacity fading and limited Coulombic efficiency, which arise from large volume expansion leading to particle cracking and subsequent electrochemical inactivity. As a result, the solid electrolyte interphase (SEI), originating in the decomposition of the electrolyte upon battery operation outside the electrolyte's thermodynamic stability window, grows uncontrollably. While a large number of mitigation strategies have been developed, an improved nanometer level fundamental understanding of the (de)lithiation process and SEI formation, growth, and evolution is necessary to overcome these challenges. Toward this end, many experimental and theoretical approaches have been utilized but still provide an incomplete picture. This is due to the difficulty of investigating buried interfaces and interphases of lithiation products and thin SEI layers (nanometer-scale) in situ and with the desired nanometer accuracy. In this Account, we illustrate the utilization of in situ X-ray reflectivity (XRR) to provide nanometer-scale insights on the SEI nucleation, growth, and evolution, and well as the (de)lithiation process of Si electrodes. XRR is a nondestructive and surface- and interface-sensitive technique that allows for in situ investigations during battery operation under realistic electrochemical conditions. Insight into the system is provided via the surface-normal density profile, which is interpreted in terms of thickness, density, and roughness of individual surface layers, allowing monitoring of the interfacial morphology and chemistry evolution, through which the SEI growth and Si (de)lithiation process can be resolved. We utilized a model battery anode consisting of a native oxide terminated single crystalline Si wafer in half cell configuration with standard electrolyte in a specifically designed in situ XRR electrochemical cell. We have resolved the nucleation and formation process of the inner inorganic SEI and have observed two well-defined inorganic SEI layers on Si anodes: a bottom-SEI layer (adjacent to the electrode) formed via the lithiation of the native oxide and a top-SEI layer mainly consisting of the electrolyte decomposition product, LiF. This SEI layer grows during lithiation and contracts during delithiation. Further, our results show that the lithiation of crystalline Si (c-Si) is a layer-by-layer, reaction-limited, two-phase process with a well-defined phase boundary between LixSi lithiation product and c-Si; in contrast, the delithiation of LixSi and the lithiation of amorphous Si (a-Si) are reaction-limited, single-phase processes. Moreover, we resolved the influences of current density and the Si crystallographic orientation of the reaction interface on the (de)lithiation process. The implications of our findings are discussed with regard to battery performance.

VQS (Vapor-Quasiliquid-Solid, Vapor-Quasisolid-Solid) Mechanism for Realizing Narrow Distributions of Chirality and Diameters of Single-Walled Carbon Nanotubes (SWCNTs).

Diameter-selective and chiral-selective single-walled carbon nanotubes (SWCNTs), all on a single wafer, have vast technological promise. An investigation has been carried out to study the role of the physicochemical state of the nanoparticle surface, and of the growth parameters and growth mechanism, on the relatively-low-temperature control of SWCNT diameter and chirality. For this, amorphicity, porosity, coarsening, high energy states, etc. resulting from controlled surface disturbance, disorder and/or restructuring of nanoparticle have been considered. Possible relationship between growth rate, chiral angle, diameter, and monodispersity of SWCNTs has been explored. The influence of the nanoparticle's peripheral hill on the diameter selectivity has been examined. Surface segregation and formation of shell have been described. The impact of charge redistribution, creation of contour of charges, and dipole moment in shell in creating chiral-selective SWCNTs has been discussed. The diffusion of the carbon species through the nanopores of the shell via Knudsen dynamics has been elucidated. The role of growth parameters in the growth process has been studied. The fundamental understanding of chiral selectivity and diameter selectivity of SWCNTs has been tried. Possible strategies for realizing narrow diameter and chirality distributions have been presented. The optimized chemical state of nanoparticle surface and the degree of ease and spontaneity, with which SWCNTs are grown on this surface, have been found to govern the chiral-selectivity, diameter-selectivity and high growth rates of SWCNTs. Good agreements of the calculated results with available experiments attest to the validity of the present study.

Effect of Substrate Temperature on the Physical Properties of ZnхSn1 – хSe Films for Thin-Film Solar Cells

At the present time, 92% of the PV market is made using single crystal or polycrystalline wafer silicon. However, producing power with these cells remains expensive compared to conventional power generation. Thin film solar cells have been developed to reduce production costs, especially those based on cadmium telluride (CdTe) and copper indium gallium diselenide (CIGS). Despite a number of successes in the development of thin film solar cells, some problems associated with the toxicity of cadmium and with the high cost of indium and gallium remain, which has prompted researchers to search for alternative materials for solar cells. Novel low cost and high efficiency zinc tin selenide (ZnxSn1 – xSe) thin film solar cells are without these drawbacks. However, there is no information in the literature about this new material. The samples of ZnxSn1 – xSe films were fabricated using the chemical molecular beam deposition (CMBD) method at atmospheric pressure in hydrogen flow. ZnSe and SnSe powders with 99.999% purity were used as precursors. The temperature of precursors varied in the range of 850–950°C. Films were deposited at substrate temperature of 500–600°C. Borosilicate glass was used as a substrate. The results showed that the composition of the samples changed toward ZnSe with the temperature of the substrate. The grain size of the samples increased from 2–5 μm to 15–17 μm at substrate temperatures of 500 and 550°C, respectively. At a substrate temperature of 600°C, the grain size decreased to 3–5 μm, which is possibly due to an increase in the ZnSe content. The X-ray diffraction pattern has shown that the samples have ZnSe, SnSe, Se, and Sn phases.

Kinetic Effect of Additives in High Temperature Phosphoric Acid on the Etching of Si3N4/SiO2

For the integration of 3D NAND, which has multiple Si3N4 and SiO­­2 pair-layer stack structure, highly selective etching of Si3N4 to SiO­­2 is required without decrease in the etching rate of Si3N4. While phosphoric acid is widely used as an etchant of Si3N4 in actual processes [1], chemical additives are added to the phosphoric acid as accelerators or inhibitors to control the kinetics of the reaction. In general, etching of Si3N4 is done at around 160 °C, but in the meantime, the process temperature may increase with the introduction of single wafer tool. In this study, we investigated the effects of various additives in H3PO4 on the Si3N4 etch rate and Si3N4/SiO2 etch selectivity at a higher temperature. LPCVD Si3N4 and SiO2 blanker wafers were etched in H3PO4 with the addition of various etching accelerators and inhibitors such as HF, NH4F, Si(OH)4, Si(OC2H5)4, and H2SiF6 at a temperature range from 160 to 200 °C. The thickness of the wafer before and after etching was measured by ellipsometry to measure etching rates of the films. When experiments were carried out with additives containing F, the etching rates of Si3N4 and SiO2 were increased by more than 30%. On the other hand, the Si3N4 and SiO2 etching rates decreased with the addition of the Si-based additives, but the decrease was remarkable in SiO2. In addition, the Arrhenius plots of Si3N4 and SiO2 were plotted to obtain activation energies of the reactions. As shown in Fig. 1(a), the F-containing additives act as catalyst in the Si3N4 etching reaction, reducing activation energy than the conventional phosphoric acid process (54 kJ/mol·K). On the other hand, Si-based additive show no significant change in the activation energy for the etching of Si3N4 (Fig. 1(b)). This is because addition of Si-based material to H3PO4 does not change reaction pathway, but suppresses the rates of etching reaction by Le-Chateliers principle [2]. On the other hand, SiO2 shows slightly different etching tendency. As shown in Fig. 2(a), the activation energy of the SiO2 etching reaction decreased with the addition of F-containing additives than that of phosphoric acid process (81 kJ/mol·K). However, Si-containing additives increased activation energy as inactivating agents. In addition, fluorosilicic acid (H2SiF6) was selected as an additive because it was expected that it reacts with water in aqueous solution to produce hydrates of Si and HF, giving effects of both F-containing and Si-containing additives. It was observed that the etching rate of Si3N4 was increased, but the etching rate of SiO2 was decreased (Data not shown here). In addition, the activation energy of the etching of Si3N4 was lower than that of phosphoric acid. On the other hand, the activation energy of the SiO2 etching increased. Therefore, it is suggested that the Si-inactivating effect is greater than the catalytic etching effect of fluorine. Based on the current study, it is concluded that a higher etch selectivity with an increased Si3N4 etch rate is achievable with the addition of proper additives by controlling the activation energy.

The Adhesion and Removal Mechanism of Ceria Particles for STI Post-CMP Cleaning Process

Chemical mechanical planarization (CMP) is an essential step to remove overburden oxide surface and form STI (Shallow Trench Isolation) structures during the semiconductor manufacturing. This is usually carried out with ceria slurry due to high selectivity between oxide and nitride surfaces. However, strong ceria adhesion to oxide surface is a major concern, as it cannot be removed easily during the post-CMP cleaning step. Generally, it is performed by a combination of physical and chemical cleaning. Conventional cleaning solutions such as DHF (Dilute Hydrogen Fluoride), SC1(NH4OH: H2O2: H2O mixture), SPM (H2SO4:H2O2 mixture) solutions are used with optimized concentrations and sequences with the support of physical forces such as PVA brush scrubbing or megasonic. However, the adhesion and removal mechanism of ceria particles from the oxide surface is not clear yet. The ceria particles would attach to the oxide to the surface may be due to electrostatic interaction or valence (Ce3+/Ce4+) effect or chemical bonding linkage of Ce-O-Si. These interactions are strongly affected and changed based on the pH of ceria used for polishing. In this work, it was emphasized to identify the specific individual mechanisms of physical cleaning and chemical cleaning in removing ceria particles from the oxide surface. Two types of physical cleanings, one is the non-contact mode (megasonic) cleaning and another one is contact mode (PVA brush) cleaning, were performed. The effect of different chemicals on removing the ceria particles was also performed. The key mechanism for the ceria particle cleaning was hypothesized. TEOS coupons (4´4 cm) were polished with ceria slurry (100nm) of pH 4 and 8, containing no additives. The optimization of physical cleaning experiments, performed with only DIW, was carried out with a single wafer megasonic cleaning (Akrion, 0.83MHz) and brush cleaning tool (lab designed pin type brush). Chemical cleaning was performed with various chemistries (SC1, DHF, SPM) to compare and understand the ceria removal performance from the oxide surface. The particles before and after cleaning were observed by FESEM and optical microscopy. To understand chemical interactions, the polished samples were analyzed for XPS, ATR FTIR, and Raman analysis before and after cleaning. The type of chemical interactions before cleaning and their modifications with the type of chemistry used were discussed. The comparative study of physical cleaning (megasonic vs. brush) were performed for the removal of ceria particles attached to the surface after polishing with slurries of pH 4 and 8. It was observed that the polished oxide surface was more contaminated with ceria in the pH 8 than in pH 4. Megasonic cleaning was able to remove partially, whereas brush scrubbing removed completely for pH 4 samples. However, the ceria particles from pH 8 samples were strongly attached not removed by megasonic and partially removed by brush cleanings. It could be expected that particles would attach electrostatically at pH 4, whereas chemically through Ce-O-Si bond at pH 8. It may be necessary to use chemical forces to break the chemical bonds between ceria-silica. It was suspected that the change of valence of ceria before and after cleaning with cleaning chemistries also would play a key role. Hence different chemistries were used to check the removability of ceria. The samples before and after cleaning were analyzed with different techniques to understand the chemical forces required to break the ceria-silica bonding. Detailed hypothesis for the ceria removal was explained by their chemical interactions with different chemistries.

Study on La2O3 Wet Clean by pH Controlled Functional Water

Introduction For the dimensional scaling and performance enhancement of upcoming semiconductor devices, some novel materials have been implemented. In the high-k metal gate (HKMG) of logic and memory periphery transistors, some lanthanides and alkaline earth metal or their oxides, e.g. lanthanum oxide (La2O3) and magnesium oxide (MgO), have been proposed as a zero-thickness work function shifter [1-7]. These dielectric films are typically patterned by wet processing to enable a multiple threshold voltage [6,7]. However, the wet processes on the new materials are challenging because they dissolve easily in de-ionized wafer (DIW). In this paper, the impact of functional water rinsing on the dissolution and passivation of La2O3 films have been investigated. Experimental detail Coupon testFirst, the effect of etching due to pH was tested. The pH of the solution was adjusted by ammonia or hydrochloric acid. Moreover, O3, H2, H2O2 was added to the ammonia water which dissolution suppression has confirmed, and the effects of their solutions were tested.(2) Wafer test We tested using 10 mm × 10 mm coupon which was cut from 300 mm La2O3 wafers. And the La2O3 coupon was immersed in various dilute solutions under open air conditions. After immersion, the La concentration in the solution was analyzed by ICP-MS. And we calculated the La dissolution amount from these results. The DIW and some functional waters, e.g. CO2 dissolved water (CO2Water), ultra-diluted NH4OH (NH4OH water) , ultra-diluted NH4OH and ultra-diluted H2O2 (NH4OH/H2O2 water), were prepared by using a Kurita functional water unit (HS-13, Kurita Water Industries), which has the capability of injection and mixing CO2 (1 – 40 ppm) and NH4OH (1 – 100 ppm). The 300 mm blanket La2O­3 wafers were processed on a single wafer wet cleaning tool (SU-3200, SCREEN Semiconductor Solutions) connected with the functional water unit. First, We had cleaning tests using CO2 water, DIW, NH4OH water, NH4OH/H2O2 water. Moreover, in order to clarify the dissolution suppression mechanism, the wafer surfaces after cleaning with each solution were analyzed by XRR. Results and discussion Coupon test La2O3 + 6H+ → 2La3 + +3H2O (1).La2O3 + 3H2O → 2La(OH)3 (2).In addition, when H2, O3 and H2O2 were added to ammonia water of pH 10.4, Suppression effects were confirmed by H2O2 added, but we did not have the effect by H2 and O3 gases added(2) Wafer test Several functional waters have been evaluated for the introduction of novel materials and applications for leading edge semiconductor device manufacturing. In case HKMG patterning is required to remove La2O3, CO2W rinsing is preferred. Meantime, NH4OH water and NH4OH/H2O2 water rinsing could preserve the La2O3 layer. Conclusions Cleaning test was performed on a 300 mm La2O3 wafer and the dissolution rate was calculated by performing wafer weight change. Figure 3 shows the etching behavior of La2O3 films treated by DIW, CO2water and NH4OH water and NH4OH/H2O2 water. The results show that the La2O3 film dissolves in CO2water and DIW, of which the pH is acidic or neutral. And XRR measurement ressults are Figure 4, It was suggested that the La2O3 surface after various rinse reatments was formed of La (OH)3. The La (OH) 3 film is thicker by the NH4OH water and NH4OH/H2O2 water cleaning than in the DIW only cleaning. Therefore, it is considered that passivation with a hydroxide film is generated and dissolution is suppressed by setting it as an alkaline region. Regarding the RMG La2O3 patterning for the PMOS devices, it would be required to remove La2O3. Meantime, the La2O3 layer should be preserved for the NMOS devices [6]. Relevant wet etching and rinsing solutions should be used for each patterning step.On the other hand, the dissolution of La2O3 is drastically suppressed in NH4OH water, which is an alkaline solution. Therefore, the La2O3 surface would be passivated by its hydroxide:The results show that La2O3 have following reaction in acidic or neutral solution:Figure 1 is shown that the influence pH on the etching rate of La2O3. By the coupon test, we clarified that the dissolution of La2O3 can be suppressed by raising pH. From this test, it was found that the etching amount was sharply reduced from about pH 1.2 to about 8, and was hardly dissolved over pH 10. Figure 1

Influence of laser surface nanotexturing on the friction behaviour of the silicon/sapphire system

The aim of the present work was to investigate the influence of textures consisting of Laser-Induced Periodic Surface Structures (LIPSS) on the friction coefficient of silicon under unlubricated conditions, using nanoscale friction tests. The tests were performed on 〈111〉 single crystal wafers of p-doped silicon. Surface texturing was performed by a direct writing technique, using 560 fs pulses of 1030 nm wavelength radiation and parameters allowing large areas with a uniform LIPSS texture to be obtained. The tribological tests were performed in air using a ball-on-flat nanotribometer with 3 mm diameter sapphire balls as counterbodies. The wear scars were analyzed by scanning electron microscopy (SEM) and energy-dispersive X-ray spectroscopy (EDS). The friction coefficient of polished Si remains approximately constant during the tests and is independent of the applied load, with values in the range 0.12–0.14. The morphology of the wear scars indicated that the predominant material removal mechanism is mild oxidative wear, independently of the testing conditions used, which explains the low values of the friction coefficient measured. The LIPSS texture leads to an increase of the friction coefficient, in particular in the perpendicular sliding direction. The friction coefficient increases with the applied load and is larger for the perpendicular sliding direction than for the parallel sliding direction, the difference increasing with increasing load. The morphology of the wear scars showed that the predominant wear regime remains oxidative wear, but significant contributions of plastic deformation and ploughing appear. This plastic deformation in Si, which is brittle at room temperature, shows that significant surface heating is being caused by the interaction of the asperities in motion and under load. This temperature increase also accelerates surface oxidation and increases the wear rate. Surface temperature calculations showed that the temperature increase is larger for the perpendicular sliding direction than for the parallel one, which explains the difference of friction coefficient observed in the two directions.

Characterization of 60 mm AlN Single Crystal Wafers Grown by the Physical Vapor Transport Method

Physical Vapor Transport Crack-free bulk AlN single crystals up to 60 mm in diameter are grown for the first time by the physical vapor transport method. The demonstrated entire wafer exhibits excellent ultraviolet transparency with absorption coefficients of 14–21 cm−1 in the range 260–280 nm, and the Raman spectra show an E2(high) FWHM of 2.86 cm−1. More details can be found in article number 1900118 by Qikun Wang, Jason Wu, and co-workers.

A generalised uncertain decision tree for defect classification of multiple wafer maps

Classification of defect chip patterns is one of the most important tasks in semiconductor manufacturing process. During the final stage of the process just before release, engineers must manually classify and summarise information of defect chips from a number of wafers that can aid in diagnosing the root causes of failures. Traditionally, several learning algorithms have been developed to classify defect patterns on wafer maps. However, most of them focused on a single wafer bin map based on certain features. The objective of this study is to propose a novel approach to classify defect patterns on multiple wafer maps based on uncertain features. To classify distinct defect patterns described by uncertain features on multiple wafer maps, we propose a generalised uncertain decision tree model considering correlations between uncertain features. In addition, we propose an approach to extract uncertain features of multiple wafer maps from the critical fail bit test (FBT) map, defect shape, and location based on a spatial autocorrelation method. Experiments were conducted using real-life DRAM wafers provided by the semiconductor industry. Results show that the proposed approach is much better than any existing methods reported in the literature.

Kinetic Effect of Additives in High Temperature Phosphoric Acid on the Etching of Si3N4/SiO2

Highly selective etching of Si3N4 to SiO2 in phosphoric acid is required for the 3D NAND integration. When a single wafer tool is introduced in this process, the process temperature needs to be well controlled. Therefore, the effect of various additives in phosphoric acid on the kinetics of the Si3N4 and SiO2 etching reaction were investigated at a higher temperature up to 200 °C in this study. The etching rates of Si3N4 and SiO2 increased whereas the activation energies decreased with the addition of either HF or NH4F. As the concentration of HF is increased, the activation energies of Si3N4 and SiO2 etching further decreased. On the other hand, Si-containing additives increased the activation energy of SiO2 etching while the activation energy of Si3N4 etching was unchanged. In general, etching selectivity of Si3N4 to SiO2 decreased with the temperature of the etchant and the amount of change in the etching selectivity was different depending on the additives in H3PO4.

Enhanced sensing properties of WO3 and its binary systems for thin films gas sensors

Thin films of pure WO3 and the binary systems of TiO2:WO3,MoO3:WO3,Cr2O3:WO3, and SnO2:WO3 were prepared by pulsed laser deposition method. The single and binary compounds were sintered at 1273K for five hours. The deposition were done under vacuum of 2x10-2 Torr at various substrates like glass and single crystal silicon wafer with negative conductance at ambient temperature thickness of ≍150 nm. The structures and morphology of pure WO3 and the binary systems TiO2:WO3,MoO3:WO3,Cr2O3:WO3, and SnO2:WO3 compounds and the deposited thin films were studied by X–ray diffraction and AFM atomic force microscope. The optical properties imply optical energy gap as well as optical constants for all the single and binary system were determined and discussed. The results of gas sensing measurements to NO2 gas showed that MoO3:WO3 sensors prepared on n- Si substrate showed maximum sensitivity (194.5%) at operating temperature 300K.