Single-stage Operational Transconductance Amplifier Research Articles

Single-Stage Complementary Metal–Oxide–Semiconductor Operational Transconductance Amplifiers (OTAs): A Design Tutorial

This paper presents a comprehensive design tutorial for four types of single-stage operational transconductance amplifiers (OTAs): (1) five-transistor OTAs, (2) telescopic cascode OTAs, (3) folded cascode OTAs, and (4) current mirror OTAs. These OTAs serve as fundamental building blocks in analog circuits. The operational principles of each OTA are reviewed, and the key performance metrics are derived through a hand analysis. These performance metrics encompass most crucial parameters, including small-signal parameters, frequency response, input and output swing ranges, rising and falling slew rates, nonidealities, and bias circuit simplicity. All of these metrics are verified and compared using the simulation. Furthermore, the practical applications of each OTA are summarized, and a case study demonstrates the enhancement of a neural recording amplifier’s performance through appropriate OTA selection. A thorough review of the essential building blocks will become a stepping stone to design high-performance analog amplifiers across diverse applications.

Research of Continuous Delta-Sigma Analog-to-Digital Converter for Bio-Electricity Signal Acquisition

In this paper, a continuous delta-sigma analog-to-digital converter with a low power, single-ring, third-order mixed integrator for bio-electricity signal acquisition is proposed. For the trade-off between low power consumption and high resolution, the Active-RC integrator is used in the first-order of the third-order feedforward modulator and the Gm-C integrator with improved linearity is adopted for the second and third order integrators. Because of the infinite resistance provided by the Gm-C integrator, the first-order integrator can replace the traditional second-order operational transconductance amplifier (OTA) with a single-stage OTA operating in the weak invert region to achieve low power consumption and ensure the output swing of the first-order integrator. The structure of cascade-of-integrators with feedforward (CIFF) can scale the output voltage values of three integrators and reduce the requirement of linearity of the Gm-C integrator, to reduce the design difficulty of the Gm-C integrator. In addition, the linearity of the second and third-order Gm-C integrator is improved by using the auxiliary difference pair OTA with source-level negative feedback. Therefore, the matching between the circuit structure and the model coefficients is improved significantly.

0.4-V, 81.3-nA Bulk-Driven Single-Stage CMOS OTA with Enhanced Transconductance

The paper describes a single-stage operational transconductance amplifier suitable for very-low-voltage operation in power-constrained applications. The proposed circuit avoids the tail current generator in the differential pair while preventing pseudo-differential operation. Moreover, the adoption of positive feedback allows increasing the stage transconductance while minimizing the current consumption. Experimental measurements on prototypes implemented in a standard CMOS 180-nm technology, show superior performance as compared to the state of the art.

A 5-V Dynamic Class-C Paralleled Single-Stage Amplifier With Near-Zero Dead-Zone Control and Current-Redistributive Rail-to-Rail Gm-Boosting Technique

For fast buffering of large stepwise input to an nF-range capacitive load, this article presents a 5-V rail-to-rail (RTR) input–output paralleled-amplifier (PA) in which a dynamic class-C amplifier (DCCA) and a linear single-stage operational transconductance amplifier (OTA) are combined in parallel. During slew time, the DCCA, which is designed to consume a near-zero static current, dominantly supplies the dynamic current up to 8.5 mA to the output. When the output gets closer to the fine-settling region, the DCCA is rapidly faded out in virtue of a dedicated near-zero dead-zone control (NDZC), and it hands over to the linear OTA. A current-redistributive RTR $G_{\text {m}}$ -boosting technique is also proposed so that the OTA can have a wide gain-bandwidth product (GBW) even over the RTR input range while minimizing the quiescent current dissipation. The prototype chip was fabricated only with 0.5- $\mu \text{m}$ 5-V CMOS devices, and it occupies a die area of 0.03 $\mu \text{m}^{2}$ . The proposed amplifier consumed a static current of 3.1 $\mu \text{A}$ with a supply voltage of 5 V. The slew rates (SRs) with load capacitances ( $C_{\mathrm {L}}$ ) of 0.8 and 10 nF were measured to be 10.3 and 0.86 V/ $\mu \text{s}$ , respectively, for a step input of $\Delta $ 4.2 V, which is a state-of-the-art result compared to prior chips. The measured GBW of 10–127 kHz was achieved over 0.8–10 nF $C_{\mathrm {L}}$ with ≥ 59° phase margin (PM). The measured GBW deviation in a common-mode voltage ( $V_{\mathrm {CM}}$ ) range of 0.3–4.7 V was within the maximum of 20%.

Bio-Amplifier based on MOS bipolar Pseudo-Resistors: A New Approach using its non-linear characteristic

This paper proposes a new and refined bio-amplifier design, which associates DC offset cancellation, adequate frequency response and buffered outputs to a significant reduction of the signal recovery time. A MOS-Bipolar pseudo-resistor integrated to the feedback network of a single-stage Operational Transconductance Amplifier and the source-follower buffers give to the new topology its main advantages. This architecture makes use of the high resistance values of these pseudo-resistors to eliminate the offset DC level input preserving the low cut-off frequency, without the need of high capacitances, thereby significantly reducing the active die area, which enables its use as a front-end pre-amplifier assembled directly on the acquisition probes. The recovery time after an input voltage transitory of high-amplitude is an important characteristic of the bio-potential amplifiers due to their very low cut-off frequency. The proposed bio-amplifier utilizes the non-linear characteristics of the pseudo-resistor in the recovery time reduction. This time was evaluated and the topology presented a significant contribution in this aspect, assuming values 90% lower when compared with the same topology using a constant resistance. The new amplifier allows voltage gain of 30dB from 0.6 Hz to 2 kHz, and Total Harmonic Distortion (THD) of 0.19% for an input signal of 10Hz. This work also provides a behavioral spice model for MOS-Bipolar pseudo-resistor, which allows an accurate simulation of the linear and nonlinear pseudo-resistor characteristics, obtained through an experimental method of indirect characterization. This method is based on the transitory response from a first order RC low pass filter. The experimental characterization method is of fundamental importance, due to the absence of appropriate SPICE models that describe with precision the pseudo-resistance behavior. The circuits were manufactured by MOSIS on 8HP SiGe BiCmos Global Foundries 0.13μm technology.

Single-Stage Operational Transconductance Amplifier Design in UTBSOI Technology Based on gm/Id Methodology

The downscaling of complementary metal-oxidesemiconductor (CMOS) technology is approaching its limits imposed by short-channel effects (SCE), thereby multi-gate MOSFETs have been proposed to extend the scalability. Ultrathin-body silicon-on-insulator (UTBSOI) transistor is one of the dual-gated devices which offers better immunity towards SCEs. In this paper, two designs have been proposed for single-stage operational transconductance amplifiers (OTA) using the CMOS and UTBSOI. The CMOS based OTA (CMOS-OTA) has been designed where sizing (W/L) of the constituting MOSFETs have been evaluated through gm/Id methodology and the same OTA topology has been simulated using UTBSOI (UTBSOI-OTA) considering the same W/L. The DC simulation is carried out over the BSIM3v3 model to store the operating point parameters in the form of graphical models. The mathematical expressions for performance specifications have been applied over the graphical models to evaluate the required W/L. Individual comparisons between the two proposed designs have also been carried out for further applications. Based on simulation results at the schematic level, the UTBSOI-OTA has higher DC gain of 33.26% and lesser power consumption of 2.81% over the CMOS-OTA. Moreover, comparative analysis of performance parameters like DC gain and common-mode rejection ratio (CMRR), have been compared with the best-reported paper so far. In addition to this, the UTBSOI-OTA has been applied to practical integrator circuits for further verification.

Systematic design of CNTFET based OTA and Op amp using gm/ID technique

This paper presents for the first time all the steps required in optimal design of carbon nano tube field effect transistor (CNTFET) based single stage operational transconductance amplifier and two stage operational amplifier using transconductance to drain current ratio ($$g_{m}/I_{D}$$) technique for low voltage and low power applications. As square law model failed to produce exact behavior in short channel devices as well as moderate and weak inversion behavior of the transistor. Therefore, $$g_{m} / I_{D}$$ methodology is used to design analog circuits in short channel devices to overcome the shortcomings of square law models. Also, the design using $$g_{m} / I_{D}$$ methodology does not consider the inversion region of the transistor like square law equations. The $$g_{m} / I_{D}$$ methodology is a well-established technique for CMOS analog IC design but CMOS has continuous width while CNTFET width is discrete and depends on different parameters like number of tubes, pitch and diameter of the carbon nanotube. Therefore, there is a need of a design methodology to design analog circuits using CNTFETs. Circuit performance has been investigated extensively using HSPICE simulation.

0.36 V PGA combining single‐stage OTA and input negative transconductor for low energy RF receivers

An ultra-low voltage and ultra-low power programmable gain amplifier (PGA) using a closed-loop single-stage operational transconductance amplifier (OTA) and an input negative transconductor is proposed. The circuits are implemented in a 180 nm CMOS process using two stacked transistors and PMOS bulk forward bias to operate well down to 0.36 V, to be robust to PVT variations and to reach the bandwidth of low energy RF receivers. The PGA measured results at 0.36 V show a programmable voltage gain from 0.2 to 18.4 dB, 15.4 μW power dissipation, 0.98 MHz bandwidth and 0.0243 mm 2 area.

Robustness Study and Comparison between P-channel and N-channel Input Single-stage OTA

Objectives: This paper carries out robustness study on p-channel and n-channel input differential amplifier (which is also known as single-stage operational transconductance amplifier). Methods and Analysis: The impact of Process, Voltage and Temperature (PVT) variations on the design metrics of both differential amplifiers is studied and suitable conclusions are drawn. Findings: The n-channel input differential amplifier is found to be more robust than p-channel input differential amplifier. Moreover, it provides higher gain, and 3-dB bandwidth as compared to its p-channel counterpart. All the results were obtained from extensive simulation using Virtuoso Analog Design Environment of Cadence @ 45-nm technology node. Application: Operational Transconductance Amplifier (OTA) can be used in the design of simple amplifiers with voltage-controllable gain and to the design of first-order and second-order active filters with controllable gains and controllable critical frequencies.

Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET

As the gate lengths of FinFETs are scaled into nano meter regime, spatial variations in oxide thickness (Tox) and junction depth (Xj) of source/drain (S/D) doping profile will largely decide the performance of digital and analog circuits that can fall below or above the desired value. Of particular importance is operational transconductance amplifier (OTA), where the crucial analog figures of merit (FOM) such as differential mode gain (ADM), common mode gain (ACM) and common mode rejection ratio (CMRR) decide the suitability of its use at nanometer regime. In the present work, we have studied the analog performance variation of low-k (dual-k) underlap FinFET based single stage OTA with spatial variation in Tox and Xj of S/D profile. Enhanced and variation less threshold voltage and mobility of dual-k underlap FinFET due to of better screening of longitudinal field and pronounced volume inversion effect, are studied in detail. It is observed that at 16nm gate length the best case ADM, ACM and CMRR of low-k (dual-k) FinFET based OTA are 34.2dB (42.3dB), 26dBm (18dBm), 68.2dB (84.2dB) respectively. Subsequently, the spatial variation of Tox and Xj leads to worst case change in ADM and ACM of low-k (dual-k) FinFET based OTA by −6.8dB (−2.2dB) and +28.2dBm (+31.3dBm) respectively. The negligible deterioration in ACM of dual-k FinFET OTA transforms into CMRR improvements of 37% at this worst case condition as compared to CMRR of low-k FinFET OTA. Furthermore, with gate length scaling, the FOM and their percentage change with Tox and Xj of dual-k FinFET OTA are much better than that of low-k FinFET OTA.

Low noise, −50 dB second harmonic distortion single‐ended to differential switched‐capacitive variable gain amplifier for ultrasound imaging

A low noise, low power, single-ended to differential switched-capacitor variable gain amplifier (SC-VGA) is designed and fabricated in 0.18 µm complementary metal-oxide-semiconductor technology for a 2–6 MHz second harmonic cardiac ultrasound imaging system. The SC-VGA has 10-bit dB-linear gain steps from −14 to 32 dB which are distributed into two stages, and each stage has a single-stage operational trans-conductance amplifier using floating capacitors to save the power and improve the noise performance. The first stage converts the single-ended input to differential outputs with the 2-bit gain control from 0 to 18 dB, and the second stage exploits 8-bit capacitor arrays to control the gain from −14 to 14 dB. The measured results show that the second harmonic distortion is <−50 dB, the third harmonic distortion is <−50 dB and the integrated noise from 2 to 6 MHz at the output is −64 dBm at the maximum gain and a sampling frequency of 30 MHz. The simulation results match well with the measured results. The SC-VGA works at a supply voltage of 1.6 V and consumes the current of 900 µA. The die size of the SC-VGA is 387 µm × 502 µm.

55 dB DC gain, robust to PVT single‐stage fully differential amplifier on 45 nm SOI‐CMOS technology

The design of a single-stage operational transconductance amplifier is presented, which uses self-cascode transistors and current shunt stages to improve its DC gain. The proposed amplifier is implemented in a standard 45 nm silicon on insulator CMOS process. Simulation results show that the amplifier has a DC gain above 50 dB despite physical and environmental variations with a minimum gain bandwidth product of 540 MHZ and more than 55° phase margin. In addition, the simulated transient behaviour is shown to be robust, with a slew rate of 500 V/μs and a settling time of 7 ns with 1% accuracy for a C L of 0.3 pF.

A micropower low-noise monolithic instrumentation amplifier for medical purposes

A CMOS low-power low-noise monolithic instrumentation amplifier (IA) is described. The power drain is reduced by use of current feedback and by use of only single-stage operational transconductance amplifiers in the low-frequency loop. The bandwidth of the IA is designed for medical purposes (0.5-500 Hz) and it can produce variable gains of 14/20/26/40 dB, which are set by control software.

High voltage gain CMOS OTA for micropower SC filters

The letter describes a single stage operational transconductance amplifier (OTA) with cascoded output transistors, designed for micropower switched-capacitor filters. The device features high voltage gain (&gt;90 dB) under capacitive load, large output swing, very low power consumption (5 μW at 3 V supply voltage for 100 kHz bandwidth with 10 pF load) and reduced circuit area (&lt;0.1 mm2).