Single Silicon Wafer Research Articles

Quantitative shear stress imaging in high throughput in-line Si wafer inspection

Defect inspection methods are basic steps in electronic chip manufacturing and power device production processes in the semiconductor industry. Based on stress induced photoelastic anisotropy, in-line polarized stress imaging (PSI) and quantitative determination of the local shear stress component are possible in single crystalline silicon wafers. Hereafter, such polarization stress images are compared and validated quantitatively with results of finite element simulations based on different 3D elastic models. Uniquely, high resolution at high throughputs is achieved for 300 mm wafer size in the present quantitative stress imaging study.

Finite element modeling and analysis method for predicting and optimizing the warpage of construction before flip chip bonding in System-on-Wafer process flow

As one of the solutions to surpass the limitations of Moore's Law in the post-Moore era, System-on-Wafer (SoW) technology provides the capability to integrate multiple chip components onto a single silicon wafer. A new high-density integrated SoW solution is discussed in this article. However, significant warpage can result from mismatches in the coefficients of thermal expansion (CTE) of different materials in a 12-in. wafer, presenting considerable challenges for the flip chip (FC) bonding, installation of power delivery and heat dissipation systems. Severe warpage can directly lead to the failure of the entire system. Therefore, pre-assessment and optimization of the warpage are crucial. This paper proposes a multi-scale modeling approach to assess the wafer warpage prior to FC bonding in the SoW fabrication process. To evaluate the accuracy of the modeling approach, a dummy die to thinned wafer and molding (DDTWM) was first designed and fabricated. The sole distinction in fabrication process between DDTWM and SoW is the absence of through silicon via (TSV) and backend of line (BEOL) metal traces. The simulation and experiment for DDTWM achieve a good level of consistency. In addition, following the completion of warpage simulations on the actual SoW structure prior to FC bonding, utilizing the same modeling approach, we proceeded to perform a Response Surface Methodology (RSM) analysis on several crucial parameters that exert influence on warpage. Subsequent to analyzing the results, optimization simulations were executed, underscoring the significant instructive value of RSM analysis in optimizing warpage within the structure prior to FC bonding in the SoW manufacturing process. This work offers an effective solution for predicting and mitigating substrate warpage prior to FC bonding in the SoW fabrication process, contributing to comprehensive warpage control.

Monolithic integration of embedded III-V lasers on SOI

Silicon photonic integration has gained great success in many application fields owing to the excellent optical device properties and complementary metal-oxide semiconductor (CMOS) compatibility. Realizing monolithic integration of III-V lasers and silicon photonic components on single silicon wafer is recognized as a long-standing obstacle for ultra-dense photonic integration, which can provide considerable economical, energy-efficient and foundry-scalable on-chip light sources, that has not been reported yet. Here, we demonstrate embedded InAs/GaAs quantum dot (QD) lasers directly grown on trenched silicon-on-insulator (SOI) substrate, enabling monolithic integration with butt-coupled silicon waveguides. By utilizing the patterned grating structures inside pre-defined SOI trenches and unique epitaxial method via hybrid molecular beam epitaxy (MBE), high-performance embedded InAs QD lasers with monolithically out-coupled silicon waveguide are achieved on such template. By resolving the epitaxy and fabrication challenges in such monolithic integrated architecture, embedded III-V lasers on SOI with continuous-wave lasing up to 85 °C are obtained. The maximum output power of 6.8 mW can be measured from the end tip of the butt-coupled silicon waveguides, with estimated coupling efficiency of approximately -6.7 dB. The results presented here provide a scalable and low-cost epitaxial method for the realization of on-chip light sources directly coupling to the silicon photonic components for future high-density photonic integration.

First Configurational Study of the CryoAC Detector Silicon Chip of the Athena X-Ray Observatory

The 50 mK cryogenic focal plane anticoincidence detector of the Athena X-ray observatory (CryoAC) is a silicon-suspended absorber sensed by a network of 400 Ir/Au transition edge sensors (TES) and connected through silicon bridges to a surrounding silicon frame plated with gold. The device is shaped by deep reactive ion etching from a single silicon wafer of 500 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m. In operating test of prototypes of the demonstration model of the CryoAC, we have highlighted the importance of the phonon hot spot in the signal generation. A fast response to the cosmic particle of a large area of about 4 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a thin 0.5 mm silicon absorber covered by a TES array can be assured by matching the array configuration to the size and properties of the hot spot. In this article, we present the preparatory study of a proposal for measuring the phonon hot spot that is predicted by the particle-absorber interaction model.

Modeling and experimental investigation of monocrystalline silicon wafer cut by diamond wire saw

Diamond wire sawing is one of the key technologies in solar cell manufacturing process and semiconductor chip manufacturing process. The thinned of silicon wafer has become a development trend of semiconductor industry, and the reduction of silicon wafer thickness can improve the material utilization and reduce the manufacturing cost. Therefore, the minimum thickness analytical model of diamond wire saw cutting monocrystalline silicon wafer is proposed in this paper to study the processing mechanism of minimum thickness of monocrystalline silicon wafer. Firstly, based on the Kirchhoff’s thin plate theory, the theoretical equation of the maximum internal stress of single silicon wafer and the sawing thickness of the silicon wafer is derived from the sawing force model. Combined with the Mohr’s strength theory, the analytical model of minimum sawing thickness of monocrystalline silicon wafer is established. Then, the analytical model is verified by the finite element simulation. The average error between the simulation results and the calculation results of the analytical model about the minimum sawing thickness of silicon wafer is 9%. Finally, the monocrystalline silicon sawing verification experiments are conducted under some groups of processing conditions. The experimental results show that the minimum sawing thickness of the silicon wafer decreases with the increasing axial speed of the wire saw, increases with the increase of the feed rate of the wire saw, and decreases first and then increases with workpiece speed becoming large. The average error of the experimental results and the calculation results of the analytical model of the wafer minimum sawing thickness is 7.4%, which verifies corrections of the analytical model.

100-μm-Scale High-Detectivity Infrared Detector With Thermopile/Absorber Double-Deck Structure Formed in (111) Silicon

This article presents a 96 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times $ </tex-math></inline-formula> 106 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> sized single-crystalline silicon (SC-Si) /Au thermopile infrared (IR) detector, with the thermopile and IR absorber located at different layers of a double-deck micromechanical structure for improving detectivity. In order to enhance IR-heat absorption within such a tiny device size, an umbrella-shaped SiN IR absorbing membrane instead of traditional plane IR-absorbing film occupies the whole area of the top layer structure. The umbrella-shaped IR absorber is suspended on top of the IR-detecting thermopile layer, with a central umbrella-stick to support the suspending and conducting the absorbed IR-heat to the bottom thermopile layer. The bottom thermopile layer consists of six pairs of spiral-shaped SC-Si/Au thermocouples that feature several times higher Seebeck coefficient compared to the traditional polysilicon/metal thermocouples. By combining surface-micromachining technique with a specific bulk-micromachining process performed in (111) silicon wafer, the double-deck structured IR-detector is successfully fabricated only from the front side of a single (111) silicon wafer for IC-foundry compatible low-cost manufacturing. Testing results show that this device of about 100-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> scale achieves an ultrahigh IR detectivity of 1.01 <inline-formula> <tex-math notation="LaTeX">$\times \,\,10^{{8}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula>Hz<inline-formula> <tex-math notation="LaTeX">$^{{{1}/{2}}}\cdot \text{W}^{-{1}}$ </tex-math></inline-formula>, which is two times improvement compared to the recently reported thermopile IR detectors, though the counterparts had larger device area. Featuring tiny size and batch fabrication capability, the proposed high-performance IR-detector is promising in both single-point detection and multipixel arrayed temperature imaging applications.

All-silicon, low-cross-talk terahertz waveguide crossing based on effective medium.

All-silicon effective-medium-clad waveguides are a promising candidate for an integrated terahertz platform with high efficiency and broad bandwidth. Waveguide crossings are essential circuit components, allowing for wave routing over shorter paths to increase circuit density. However, the simple intersection of two orthogonal effective-medium-clad waveguides results in terahertz wave scattering, leading to relatively high cross talk. In this work, a low-loss, 40% fractional bandwidth crossing utilizing Maxwell-Garnet effective-medium theory and wavefront planarization techniques is proposed. This monolithic structure is fabricated on a single high-resistivity float-zone silicon wafer using a deep reactive ion etching process with a modest 4.4 mm diameter (4.03λ0) structure footprint. Experimentally verified results show low insertion loss, less than 1 dB, and average cross talk level of -39dB for both E11x and E11y operating modes, over 220-330 GHz with a 40% fractional bandwidth. This waveguide crossing can be foreseen as a useful routing component for terahertz all-silicon integrated circuits. The proposed techniques are applicable to other dielectric waveguide platforms at infrared and optical frequencies.

Backside Chippings Improvement through Wafer Dicing Parameter Optimization and Understanding the Anistropic Silicon Properties

Semiconductor Companies and Industries soar high as the trend for electronic gadgets and devices increases. Transition from “manual” to “fully automatic” application is one of the advantages why consumer adapt to changes and prefer electronic devices as one of daily answers. Individuals who admire these electronic devices often ask how they are made.&#x0D; As we look inside each device, we can notice interconnected microchips commonly called IC (Integrated Circuit). These are specially prepared silicon wafers where integrated circuit are developed. Commonly, each device is composed of numerous microchips depending on the design and functionality&#x0D; IC production is processed from “front-end” to “back-end” assembly. Front-end assembly includes wafer fabrication where electrical circuitry is prepared and integrated to every single silicon wafers. Back-end assembly covers processing the wafer by cutting into smaller individual and independent components called “dice”. Each dice will be placed into Leadframe, bonded with wires prior encapsulating with mold compounds. After molding, each IC will be cut through a process called singulation. Afterwards, all molded units are subjected for functional testing.&#x0D; Dice is central to each IC; it is where miniature transistor, resistor and capacitor are integrated to form complex small circuitry in microchips.&#x0D; Pre-assembly (Pre-assy) stations have the first hand prior to all succeeding stations. Live wafers are primary direct materials processed in these stations. Robust work instruction and parameter must be practiced during handling and processing to avoid gross rejection and possible work-related defects.&#x0D; The paper is all about the challenges to resolve and improved the backside chippings in 280um wafer thickness in mechanical dicing saw. The conventional Mechanical dicing process induce a lot of mechanical stress and vibration during the cutting process which oftentimes lead to backside chipping and die crack issues. However, backside chippings can mitigate with proper selection of parameter settings and understand the silicon wafer properties.

Quantum Cylindrical Dielectric Resonator Antenna for LiDAR Application

In this paper the fabrication of the quantum CDRA at 3.37THz Frequency. Focus on simulation, design, micro fabrication and working on Lab-on-a-chip platforms i.e. Photonic Chip Integration Facility. It can be fabricated on single silicon wafer of 3” using micro machining for fabrication. The 3D printers are used to provide rapid prototype fabrication. The proposed quantum CDRA provides the return loss and VSSR of -30dB and 1dB respectively. The VSSR is below 2dB. The gain of the proposed quantum CDRA is 8.2 dB. The proposed quantum CDRA obtains impedance bandwidth of 5.27%. Proposed cylindrical dielectric resonator antenna can be used in LiDAR.

Scanning thermal microscopy on samples of varying effective thermal conductivities and identical flat surfaces

We propose an approach for the characterization of scanning thermal microscopy (SThM) probe response using a sample with silicon dioxide steps. The chessboard-like sample provides a series of nine surfaces made of the same material, with identical roughness, but consisting of different thicknesses of silica layers standing on a single silicon wafer. The nine regions have different effective thermal conductivities, allowing the calibration of SThM probes within a given set of surface conditions. A key benefit is the possibility of comparing the spatial resolution and the sensitivity to vertical inhomogeneities of the sample for different probes. A model is provided to determine the thermal contact area and contact thermal resistance from the experimental data. The results underline that ballistic heat conduction can be significant in crystalline substrates below the top thin films, especially for film thicknesses lower than 200 nm and effective thermal contact radius lower than 200 nm. They also highlight the sensitivity of SThM to ultrathin films, as well as the substrate below micrometric films under in-air conditions but not when in vacuum. This work advances quantitative nanometer-scale thermal metrology, where usual photothermal methods are more difficult to implement.

Comparative Study of Silicon Nanowires Grown From Ga, In, Sn, and Bi for Energy Harvesting

A high density of silicon nanowires for solar cell applications was fabricated on a single crystalline silicon wafer, using low eutectic temperature metal catalysts, namely, gallium, indium, tin, and bismuth. The use of silicon nanowires is exploited for light trapping with an aim to enhance the efficiency of solar cells. Additionally, we have optimized the deposition parameters so that there is merely deposition of amorphous silicon along with the growth of silicon nanowires. Thus, it may improve the stability of silicon-based solar cells. The different catalysts used are extensively discussed with experimental results indicating stable growth and highly efficient silicon nanowires for photovoltaic applications. To test the stability, we measured the open-circuit voltage for four hours and the change in voltage was ±0.05 V. The fabrication of all-crystalline silicon solar cells was demonstrated using the conventional mature industrial manufacturing process that is presently used for the amorphous silicon solar cells. To summarize, this research compares various post-transition metals as a catalyst for the growth of nanowires discussing their properties, and such silicon nanowires can be utilized in several other applications not only limited to photovoltaic research.

Characteristics of Effective-Medium-Clad Dielectric Waveguides

Effective-medium-clad dielectric waveguides are purely built into a single high-resistivity float-zone silicon wafer with their claddings defined by deep subwavelength perforations. The waveguides are substrate-free while supporting both $E_{11}^x$ and $E_{11}^y$ modes with low loss and low dispersion. This article extends the investigations of the waveguides by analyzing the dispersion, cross-polarization, and crosstalk together with the characteristics of bends and crossings over an operation frequency range of 220–330 GHz (WR-3 band). Taking the $E_{11}^x$ mode as an example, the experimental results show an average measured attenuation coefficient of 0.075 dB/cm and a group velocity dispersion ranging from around $\pm$ 10 ps/THz/mm across the whole band. A crosstalk level below $-$ 10 dB is measured for parallel waveguides with a separation of 0.52 $\lambda _{0}$ at 300 GHz. The realized waveguides show a bending loss ranging from 0.500 to 0.025 dB per bend and a crosstalk at crossing below $-$ 15 dB from 220 to 330 GHz. Due to the different dispersion characteristics, the $E_{11}^y$ mode has similar performances but with its operation frequency range reduced to 260–330 GHz. Limited by the measurement setup, a cross-coupling between the $E_{11}^x$ and $E_{11}^y$ modes is measured to be below $-$ 20 dB over the whole band. This in-depth investigation of effective-medium-clad waveguides will form a basis for terahertz-integrated platforms.

In Situ Formation of Nanoporous Silicon on a Silicon Wafer via the Magnesiothermic Reduction Reaction (MRR) of Diatomaceous Earth.

Successful direct route production of silicon nanostructures from diatomaceous earth (DE) on a single crystalline silicon wafer via the magnesiothermic reduction reaction is reported. The formed porous coating of 6 µm overall thickness contains silicon as the majority phase along with minor traces of Mg, as evident from SEM-EDS and the Focused Ion Beam (FIB) analysis. Raman peaks of silicon at 519 cm−1 and 925 cm−1 were found in both the film and wafer substrate, and significant intensity variation was observed, consistent with the SEM observation of the directly formed silicon nanoflake layer. Microstructural analysis of the flakes reveals the presence of pores and cavities partially retained from the precursor diatomite powder. A considerable reduction in surface reflectivity was observed for the silicon nanoflakes, from 45% for silicon wafer to below 15%. The results open possibilities for producing nanostructured silicon with a vast range of functionalities.

Radiation tolerance of nanostructured TiAlN coatings under Ar+ ion irradiation

The radiation tolerance of TiAlN coatings under irradiation with 200 keV Ar+ ions is studied at room temperature. The ion fluence varied in the range of 1·1016–2·1017 ions/cm2. The TiAlN coatings were deposited by reactive magnetron sputtering on single crystalline silicon wafers as well as on AISI 304 stainless steel bars. Elemental composition of the coatings was investigated using Rutherford backscattering spectrometry with He+ ions of 2.53 MeV and 4.53 MeV as well as by energy-dispersive X-ray spectroscopy using 18 keV electrons. Phase composition and structure of TiAlN coatings were examined by X-ray diffraction and scanning electron microscopy. Mechanical properties of TiAlN coatings were evaluated by nanoindentation using a nanohardness tester with a Berkovich diamond tip and applying the Oliver-Pharr method. Some selective nitrogen sputtering was detected caused by the Ar+ ion irradiation. The TiAlN coatings crystallites refined under argon ion irradiation. It was found that the irradiation fluence of 2·1017 ions/cm2 is a threshold fluence, at which the solid solution decomposition starts. Ion irradiation causes mechanical properties improvement up to the fluence of 5·1016 ions/cm2. No destruction processes of the coatings such as blistering or flaking were detected for all irradiation fluences used in this study.

Thin-Piezo on Single-Crystal Silicon Reactive Etched RF MEMS Resonators

This paper demonstrates how a single crystal silicon wafer can be used to fabricate thin-film piezoelectric-on-silicon (TPoS) resonators by utilizing a modified version of Single Crystal Silicon Reactive Etch and Metallization (SCREAM) process. The developed process enables the fabrication of MEMS resonators with varied device layer thicknesses ranging from sub-micrometer to tens of micrometers (one thickness per die) from a single bulk silicon wafer, while avoiding the need of costly silicon-on-insulator (SOI) substrates. The thin-film piezoelectric on single-crystal silicon reactive etched technique allows batch fabrication of TPoS resonators, while also retaining the same number of photolithography steps. To maintain a good resonator body sidewall roughness, a conformal Al2O3 thin film was deposited by atomic layer deposition to act as the sidewall protection layer. Through the developed process, resonators with varied silicon layer ranging from $0.1~\mu \text{m}$ to $47~\mu \text{m}$ have been successfully implemented. The measured results under different ZnO-to-Si thickness ratios have been studied, in terms of motional impedance ( $R_{\mathrm {m}}$ ), quality factor ( $Q$ ), and resonance frequency. It is noted that TPoS MEMS resonators operating in fundamental and higher lateral extensional modes exhibit their best performance under an optimal ZnO-to-Si thickness ratio. Resonators fabricated by the modified TPoS process with a Si device layer thickness of 4- $20~\mu \text{m}$ exhibits optimal performance. The highest $Q$ of 1,567 for a disk resonator and the lowest motional impedance of 791 $\Omega $ for a square plate resonator were achieved with Si layer thicknesses of $20~\mu \text{m}$ and $4~\mu \text{m}$ , respectively.

Effective-medium-cladded dielectric waveguides for terahertz waves.

Terahertz integrated platforms with high efficiency are crucial in a broad range of applications including terahertz communications, radar, imaging and sensing. One key enabling technology is wideband interconnection. This work proposes substrate-less all-dielectric waveguides defined by an effective medium with a subwavelength hole array. These self-supporting structures are built solely into a single silicon wafer to minimize significant absorption in metals and dielectrics at terahertz frequencies. In a stark contrast to photonic crystal waveguides, the guiding mechanism is not based on a photonic bandgap but total internal reflections The waveguides are discussed in the context of terahertz communications that imposes stringent demands on performance. Experimental results show that the realized waveguides can cover the entire 260-400 GHz with single dominant modes in both orthogonal polarizations and an average measured attenuation around 0.05 dB/cm. Limited by the measurement setup, the maximum error-free data rate up to 30 Gbit/s is experimentally achieved at 335 GHz on a 3-cm waveguide. We further demonstrate the transmission of uncompressed 4K-resolution video across this waveguide. This waveguide platform promises integration of diverse active and passive components. Thus, we can foresee it as a potential candidate for the future terahertz integrated circuits, in analogy to photonic integrated circuits at optical frequencies. The proposed concept can potentially benefit integrated optics at large.

Hydrophobic nanostructures fabricated by ferric nitrate etching method on single crystalline silicon surface

To improve the hydrophobicity of the surfaces of single crystalline silicon (sc-Si) wafers, hierarchical structures were fabricated on the surfaces of sc-Si wafers by using Fe(NO3)3/HF mixed solution as an etchant. Scanning electron microscope, atomic force microscope and water contact angle were used to characterize the etching of sc-Si wafers. It was found that after the etching process the surface micro/nano-structures having hemispherical etched pits with needle-like folds can be formed and the surface of sc-Si wafers possess hydrophobicity. The concentration of Fe(NO3)3, etching temperature and etching time have important impacts on surface morphology and surface hydrophobicity of the sc-Si. Results showed that the surface water contact angle of etched sc-Si wafers decreased with the increase of the concentration of Fe(NO3)3. The surface water contact angle of the sc-Si wafer treated with 0.2 M of Fe(NO3)3 is highest (124.37°) and increased by 145.89% compared to that of control sc-Si wafers due to the smallest surface roughness and the most smooth surface. Surface wettability of sc-Si wafers varied from hydrophobic to hydrophilic as the etching temperature increasing from 30 °C to 70 °C. When the etching temperature was 30 °C and 70 °C, the surface water contact angle of sc-Si wafer was 142.32° and 13.86°, respectively. With the increase of the etching time, rough grooves formed on the surface of sc-Si wafers and the roughness changed larger. Hydrophobic surfaces with a water contact angle up to 144.50° were obtained at etching time of 30 min.

Silicon and germanium nanostructures formed by spark discharge plasma

Formation of semiconductor nanostructures on the surface of single crystalline silicon and germanium wafers by spark discharge plasma in air was investigated. The prepared nanostructures were analyzed by means of the scanning and transmission electron microscopy and optical spectroscopy of the photoluminescence and Raman scattering. The formed nanostructures exhibit a fractal-like morphology with interconnected nanocrystals of 2-200 nm sizes that is explained by repeated processes of spark ablation and subsequent condensation. While the size and morphology of the nanostructure depend on power sources of the spark discharge, short interaction times of spark discharge plasma and target determine a relatively low efficiency of the chemical oxidation of germanium and silicon, as well as low ionic temperatures of the plasma.

Ni(II) doped FeOOH 2D nanocrystals, synthesized by Successive Ionic Layer Deposition, and their electrocatalytic properties during oxygen evolution reaction upon water splitting in the alkaline medium

Nanolayers of Ni(II) doped FeOOH 2D nanocrystals were for the first time synthesized on the surface of nickel foam and single crystalline silicon wafer through Successive Ionic Layer Deposition (SILD) method by using an aqueous solution of Fe(NH4)2(SO4)2 with the equilibrium pH value, as well as the solution containing Ni(NO3)2 and NH4NO3 with pH = 9.5 reached by addition of ammonia. The obtained nanolayers were investigated by SEM, HRTEM, TEM, EDX, XRD, XPS and FTIR spectroscopy. They were stated to be formed by Ni:FeOOH 2D nanocrystals with lepidocrocite and goethite crystal structures having the morphology of nanosheets. They are 2–5 nm thick with planar dimensions of about 30–50 nm and the ratio of atomic concentrations of Ni to Fe is 25%. The nanolayers were shown to exhibit electrocatalytic properties during the oxygen evolution reaction upon water splitting in the alkaline medium. For the first time it was shown that the overpotential value can be precisely set by varying the number of SILD cycles these properties can be changed precisely. For a number of samples, synthesized after 20–80 SILD cycles, it was found for a current density of 10 mA/cm2 the lowest overpotential value of 239 mV was obtained for the sample synthesized after 60 SILD cycles. The synthesis of a wide range of electrocatalytic nanolayers by SILD with the precise structural and chemical characteristics was suggested.

MACE nano-texture process applicable for both single- and multi-crystalline diamond-wire sawn Si solar cells

The photovoltaic (PV) industry requires efficient cutting of large single and multi-crystalline (sc- and mc-) silicon (Si) wafers. Historically multi-wire slurry sawing (MWSS) dominated, but the higher productivity of diamond-wire-sawing (DWS) holds promise for decreasing PV costs in the future. While surface texturing of DWS wafers is more complicated than of MWSS wafers, especially in mc-Si wafers, nanotexturing has been shown to overcome this challenge. While the benefit of nanotexturing is thus clearer in mc-Si, a universal nano-texture process that also works on sc-Si would simplify and reduce the investments costs of PV production-lines. In this paper, such a nano-texture process is developed using a metal-assisted chemical etch (MACE) technique. Step-by-step characterization of surface structure and reflectance of the MACE process is used after: 1) wafering, 2) standard acidic texturing etch, 3) silver nanoparticles deposition, and 4) MACE nanotexturing for both sc and mc-Si. The results show that the same MACE process works effectively for both sc-Si and mc-Si wafers. Finally, the nano-textured wafers are processed into PV cells in an industrial process line with conversion efficiencies of 19.4% and 18.7%, for sc-Si and mc-Si solar cells, respectively.