Single-sideband Noise Figure Research Articles

A 0.46–0.52-THz fully-differential quasi-monostatic FMCW radar transceiver in 90-nm SiGe BiCMOS

A 0.46–0.52-THz fully-differential quasi-monostatic frequency-modulated continuous-wave (FMCW) radar transceiver was designed in a 90-nm SiGe bipolar CMOS technology with fT/fmax\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ extit{f}_{ \ extit{T}}/{f}_{\ ext{max}}$$\\end{document} of 300/480 GHz. The transceiver chip has an area of 2.84 mm2\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ ext{mm}^{2}$$\\end{document}. A multiply-by-24 frequency multiplier chain is used to generate a 0.48-THz signal from a 20-GHz input signal. Two 0.48-THz push–push doublers are driven in quadrature for a differential output signal with a measured effective isotropic radiated power of up to -\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$-$$\\end{document}8.8 dBm at the transmitter at 0.47 THz. A differential subharmonic receiver mixer with a stacked quad topology achieves a measured system conversion gain of 7 dB and a measured single-sideband noise figure of 25.2 dB at 0.471 THz. FMCW radar measurements are performed using an on-board frequency source of a credit card-sized demonstrator at a bandwidth of 60 GHz.

A 223–276-GHz Cascadable FMCW Transceiver in 130-nm SiGe BiCMOS for Scalable MIMO Radar Arrays

This article reports a 223–276-GHz monostatic frequency-modulated continuous-wave (FMCW) radar transceiver (TRX) chip. The TRX is suitable for building massive multiple-input multiple-output (MIMO) radar arrays in the daisy-chain topology because of its cascadable feature based on the injection-locking feedthrough technique. The TRX is based on 18 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> frequency multiplication chain that can be fed by either an external signal generator (SG) or its internal voltage-controlled oscillator (VCO). The modulation bandwidth (BW) is about 53 GHz when the internal VCO is activated, resulting in a range resolution of better than 3 mm. The peak output power is 3.1 dBm at 240 GHz with a 3-dB BW of 41 GHz. Its receiver (RX) channel is based on the in-phase/quadrature architecture enabling complex signal sampling. The minimum single-sideband (SSB) noise figure (NF) is 18.7 dB at 255 GHz, and the average value is 20.7 dB. The TRX chip includes an on-chip antenna coupled with a silicon lens, offering a peak effective isotropic radiated power (EIRP) of 27 dBm at 240 GHz. The TRX consumes a dc current of 234 and 270.1 mA from a single supply voltage of 3.3 V for external and internal VCO operations, respectively. The chip occupies a total area of 2.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (2.16 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 1.26 mm).

A 260–300-GHz Mixer-First IQ Receiver With Fundamental LO Driver in 130-nm SiGe Process

We report a 280-GHz mixer-first quadrature receiver in 130-nm SiGe that achieves a peak gain of 25 dB, an IF bandwidth of 30-GHz, and a minimum single-sideband (SSB) noise figure (NF) of 18.2 dB. The receiver is comprised of two Gilbert-cell mixers with swapped RF and local oscillation (LO) ports that downconvert the RF signal at 260–299 GHz to I/Q IF signals at 1–40 GHz by using a pseudo-differential LO driver at 259 GHz. In each channel, a wideband IF amplifier was used for an aimed conversion gain of higher than 20 dB. Combined with a differentia hybrid coupler, an integrated 259-GHz driving amplifier (DA) was integrated to generate the quadrature LO signals for I and Q channels. The measured amplitude and phase imbalance between the I and Q channels are around 4 dB and 4°, respectively. The fabricated chip occupies a whole area of 1.12 mm2 and consumes a dc power of 384 mW.

A 140-GHz FMCW TX/RX-Antenna-Sharing Transceiver With Low-Inherent-Loss Duplexing and Adaptive Self-Interference Cancellation

This article presents a 140-GHz frequency-modulated continuous-wave (FMCW) radar transceiver featuring transmit/receive (TX/RX) antenna sharing that address a TX/RX beam misalignment problem when large-aperture lenses/mirrors/reflectarrays are used for pencil beam forming. A full-duplexing technique based on circular polarization and geometrical symmetry is applied to mitigate the 3 dB + 3 dB insertion loss inherent to conventionally adopted directional couplers, while still maintaining high TX-to-RX isolation. In addition, a self-adaptive self-interference cancellation (SIC) is implemented to suppress extra leakage due to antenna mismatch from a desired frontside radiation scheme. The TX/RX antenna sharing enables the pairing with a large 3-D printed planar lens and boosts the measured effective isotropic radiated power (EIRP) to 25.2 dBm. The measured total radiated power and minimum single-sideband noise figure (SSB NF) including antenna and duplexer losses are 6.2 dBm and 20.2 dB, respectively. The measured total TX-RX isolation is 33.3 dB under 14-GHz wide FMCW chirps. Based on a 65-nm complimentary metal–oxide–semiconductor (CMOS) technology, the chip has a die area of 3.1 mm2 and consumes 405 mW of dc power. Among all reported sub-THz transceivers with TX/RX antenna sharing, this work demonstrates the highest total radiated power and is the only work that has >30 dB of TX-RX isolation while mitigating the inherent 6 dB coupler loss.

A Low-Noise W-Band Receiver in a 28-nm CMOS Technology

A passive mixer-first receiver architecture operating at a frequency range between 70 and 86 GHz, together with a two-stage LO buffer and a low noise IF amplifier, is presented and designed in a 28-nm bulk CMOS technology. The receiver achieves a single-sideband noise figure (SSB NF) of less than 10 dB for IF frequencies above 400 kHz with a minimum of 9 dB above 1 MHz. The implemented chip features a voltage gain of about 14 dB and a 1-dB compression point of −5 dBm. The receiver core occupies an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {0.09}~{\text {mm}^{2}}$ </tex-math></inline-formula> and consumes 55 mA from a 1.8-V power supply including all ON-chip biasing circuits.

A 20–42-GHz IQ Receiver in 22-nm CMOS FD-SOI With 2.7–4.2-dB NF and −25-dBm IP1dB for Wideband 5G Systems

This article presents a 20–42-GHz in-phase and quadrature (IQ) receiver in 22-nm CMOS fully depleted silicon on insulator (FD-SOI). The receiver includes a wideband low noise variable-gain amplifier (LN-VGA), double-balanced IQ mixers, wideband I/Q generation network and wideband local oscillator (LO) driver, low-pass filters, and wideband intermediate frequency (IF) amplifiers. The measured receiver has a peak conversion gain of 25.3 dB with a 3-dB bandwidth of 19.8–42 GHz and an I and Q bandwidth of 5.7 GHz and covers the 5G millimeter-wave (mm-wave) band. The measured single-sideband noise figure (NF) is 2.7–4.2 dB at 24–42 GHz with an IP1dB of −26 to −23 dBm. The I/Q downconverter consumes a total of 102 mW from 0.8- and 1.6-V supplies. The IP1dB can be improved by 5 dB with an NF degradation by only 1.2 dB using RF VGA gain control. At peak gain and −8-dB VGA setting, the receiver dynamic range is 64–68 dB for a 100-MHz bandwidth, which is very high for low power consumption. The gain and phase mismatch between the I and Q channels is < 0.6 dB and <6°, respectively. To the best of the authors’ knowledge, this is the first wideband I/Q receiver that covers the entire mm-wave 5G band based on GF 22-nm CMOS FD-SOI. The application area is multistandard multigigabit per second communication systems.

LO Chain (×12) Integrated 190-GHz Low-Power SiGe Receiver With 49-dB Conversion Gain and 171-mW DC Power Consumption

A 190-GHz mixer-based down-conversion receiver realized in a 130-nm SiGe BiCMOS technology featuring high-speed heterojunction bipolar transistors (HBTs) with ( $f_{\text {T}}$ , $f_{\text {max}}$ ) = (300, 500) GHz is presented. The core part of the receiver consists of a low-noise amplifier (LNA), an active tunable fundamental mixer, an intermediate frequency (IF) buffer amplifier (BA), and an active inverse balun. A wideband, high conversion gain (CG) local oscillator (LO) chain is integrated to make the receiver suitable for applications requiring tunable LO, which contains a multiplier with a multiplication factor of 12 ( $\times 12$ ) and a driver amplifier. To exploit the best possible performance with ultralow dc power consumption ( $P_{\text {dc}}$ ), the mixer and LNA transistors operate at forward-biased base–collector junction voltage ( $V_{\text {BC}}$ ). With a fixed IF frequency at 1 GHz, this receiver exhibits a peak CG of 49 dB with a 14-dB tuning range and a minimum single-sideband noise figure (NF) of 16.5 dB, consuming only 29-mW static dc power for the core part and 171 mW overall, including the LO chain. Within the CG tuning range, this receiver achieves a 6-dB RF bandwidth (BW) from 25 to 32 GHz. Compared with previously reported receivers at similar frequencies, the highest CG and the lowest $P_{\text {dc}}$ with highly competitive performance in terms of BW, CG tuning range, 1-dB output compression point, and NF have been achieved.

425-to-25-GHz CMOS-Integrated Downconverter

An integrated 425-GHz radio frequency (RF) to 25-GHz intermediate frequency (IF) second-order subharmonic downconverter, including an on-chip 8X local oscillator (LO) signal multiplier circuit that provides ~1 dBm at 200 GHz from an externally applied 25-GHz signal, and a 25-GHz IF amplifier, achieves a conversion gain of 6.7 dB and a noise figure of ~17 dB. The downconverter consumes 190 mW of dc power. Compared to the previously reported CMOS and SiGe HBT receivers/downconverters operating around 400 GHz and above, the downconverter achieves ~18-dB lower single side band noise figure. Finally, a passive switching mixer can have an available output noise spectral density less than kT, which can make its NF less than its conversion loss.

A Multichannel D-Band Radar Receiver With Optimized LO Distribution

This work presents a multichannel D-band receiver front-end for multiple-input-multiple-output frequency-modulated continuous-wave radar applications. The 120-GHz local oscillator (LO) signal is generated from an external 24-GHz source by an integrated frequency multiplier by five. We propose co-design of power-matched differential buffers with active splitters. Thank to the optimal impedance ratio, the power consumption of the LO distribution network could be minimized. To demonstrate the effectiveness of the discussed method, a chip with three receivers is implemented, where each receiver signal path comprises a mixer-first Gilbert cell which shows 12-dB conversion gain, 13-dB single-sideband (SSB) noise figure, and -5-dBm input-referred 1-dB compression point. A fourth channel is included for built-in self-test and the characterization of the LO distribution chain, providing a -2-dBm output signal over the 111-123-GHz frequency range. The circuit has a low-power consumption of 66-mW per RX channel, for a total power consumption of 198mW from the 1.8-V supply. The active area is 2.07mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> implemented using a 0.13- μm SiGe BiCMOS technology.

A 5.4 GHz Fully-Integrated Low-Noise Mixer

An active mixer using a Gilbert-cell topology that incorporates a low-noise RF transconductance stage is presented in this paper. The chip operates at a frequency of 5.4 GHz and was fabricated in 180 nm CMOS technology. A current-bleeding circuit is used to provide different dc bias currents to the LO switching stage and the RF transconductors. The transconductor, designed using the power constrained simultaneous noise and input match technique, together with the bleeding circuit enables the mixer to have a measured single-sideband noise figure of 7.8 dB and a power conversion gain of 13.1 dB. The measured input-referred 1-dB compression point, IP1dB is -17.8 dBm while its OP1dB is -5 dBm. A two-tone test was carried out and the mixer exhibits an IIP3 of -6.2 dBm and an OIP3 of +6.9 dBm. All of the inductors are on-chip and the size of the mixer core is only 380 μm x 350 μm (0.133 mm2).

Terahertz Even-Order Subharmonic Mixer Using Symmetric MOS Varactors

A 560-GHz radio frequency (RF) front-end employing an accumulation mode MOS symmetric varactor (SVAR) subharmonic mixer achieves a minimum single sideband (SSB) noise figure (NF) of 35 dB in the fourth-order subharmonic mixing (SHM) mode which is 5 dB lower than that of SiGe HBT mixers. The front-end fabricated in 65-nm CMOS also achieves 45-dB SSB NF for sixth-order SHM at RF=810 GHz and 60-dB SSB NF for tenth-order SHM at RF=1.2 THz. Use of SVARs in a mixer is the first and the 1.2-THz RF is the highest for mixers in silicon technologies. The measurement results are explained using the parametric amplification theory.

A 220-to-320-GHz FMCW Radar in 65-nm CMOS Using a Frequency-Comb Architecture

This article presents a CMOS-based, ultra-broadband frequency-modulated continuous-wave (FMCW) radar using a terahertz (THz) frequency-comb architecture. The high-parallelism spectral sensing provided by this architecture significantly reduces the bandwidth requirement for the THz front-end circuitry and ensures that the peak output power and sensitivity are maintained across the entire band of operation. The speed and linearity of frequency chirping are also improved by the comb system. An antenna-sharing scheme based on a square-mixer-first architecture is used, which not only leads to compact size but also facilitates the stitching of the multichannel radar IF data. To avoid the usage of high-cost silicon lens in the on-chip broadband radiation, a multi-resonance substrate-integrated-waveguide (SIW) antenna structure is innovated, which provides 15% fractional bandwidth for impedance matching. As a proof of concept, a five-tone radar prototype that seamlessly scans the entire 220-to-320-GHz band is demonstrated. In the measurement, the multi-channel-aggregated equivalent-isotropically radiated power (EIRP) is 0.6 dBm and is further boosted to ~20 dBm with a TPX (polymethylpentene) lens. The measured minimum single-sideband noise figure (SSB NF) of the receiver, including the antenna loss and baseband amplifier, is 22.8 dB. Due to the comb architecture, the EIRP and NF values fluctuate by only 8.8 and 14.6 dB, respectively, across the 100-GHz bandwidth. The chip has a die size of 5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 840 mW of dc power. This work marks the first CMOS demonstration of THz radar and achieves record bandwidth and ranging resolution among all radar front-end chips.

Compact low‐power 154 GHz receiver front‐end in 0.13 µm SiGe BiCMOS

This study presents a compact 154 GHz receiver fabricated in a 0.13 µm SiGe BiCMOS process, which is composed of a three-stage low-noise amplifier and an improved micromixer. In order to mitigate the intrinsic DC and RF imbalance of the basic micromixer, the resistor compensation is implemented at one branch of the RF paths, which achieves superior performance. Consisting of a common-emitter and two differential cascade stages, the separate low-noise amplifier achieves a small-signal gain of 21.8 dB at 155 GHz with a 3 dB bandwidth of 22 GHz. The entire receiver exhibits a maximum conversion gain of 23.8 dB at 154 GHz with a 3 dB bandwidth of 16.5 GHz. The minimum single-sideband noise figure is measured to be 11.4 dB at 149 GHz and remains below 15 dB from 142 to 160 GHz. Exhibiting high gain, low-noise figure and considerably high bandwidth, the characterised receiver consumes competitive low power of 70.7 mW and occupies the smallest core area of only 0.12 mm 2 to the best of our knowledge.

An 80-Gb/s 300-GHz-Band Single-Chip CMOS Transceiver

A single-chip CMOS transceiver (TRX) capable of wireless data rates up to 80 Gb/s using part of frequencies (252–279 GHz) covered by IEEE Std 802.15.3d is presented. The TRX chip operates in either transmitter (TX) or receiver (RX) mode at frequencies comparable to ${f_{\mathrm {max}}}$ of the NMOSFET. The TX part adopts mixer-last architecture with four-way power combining using a ring circuit called a double-rat-race. The RX part adopts fundamental-mixer-first direct-conversion architecture. In the RX mode, the TX serves as an LO multiplier chain, which conventionally accounted for a significant part of the RX die area. The double-rat-race, having an improved design than the original one, integrates the TX and RX and also rejects unwanted harmonics generated by the frequency-doubler-based upconversion mixer. Low-loss, low-characteristic-impedance transmission lines are used extensively to combat losses. The TRX was fabricated using a 40-nm CMOS process. The saturated output power of the TX is −1.6 dBm at 265.68 GHz. The mean single-sideband noise figure (SSB NF) of the RX is 22.9 dB. The TX mode and the RX mode consume dc power of 890 and 897 mW, respectively. A wireless data rate of 80 Gb/s between a pair of TRX chips is demonstrated with 16QAM over a distance of 3 cm.

Sub‐mW cognitive CMOS frequency down‐converter for internet of things

In this study, a suitable sub-mW frequency down converter for internet of things is presented. It is based on a single balanced switched transconductance mixer driven by a current-reuse LC voltage controlled oscillator (LC-VCO). For cognitive radio demonstration, the frequency converter is implemented with a tunable low-noise amplifier (LNA) in 0.13 µm standard complementary metal oxide semiconductor (CMOS) technology. Post-layout simulations return a gain conversion of 27 dB with a single-sideband noise figure of 8 dB (LNA included) for a consumption of 0.97 mW under a voltage supply of 1.2 V and an active area of 0.4 mm2. The stand-alone LC-VCO prototype exhibits a measured phase noise of −102 dBc/Hz at 1 MHz offset while showing −114 dBc/Hz in the post-layout simulation. The LC-VCO measured power consumption is only 260 µW from 1 V voltage supply with an active area of 0.173 mm2.

A 16-QAM 100-Gb/s 1-M Wireless Link With an EVM of 17% at 230 GHz in an SiGe Technology

This letter presents a 1-m wireless link established with a set of fundamentally operated Tx/Rx direct-conversion in-phase and quadrature (IQ) radio frequency (RF) front-end modules in a 0.13- $\mu \text{m}$ SiGe HBT technology featuring full chip-on-board packaging. Using a 16-quadrature amplitude modulation, data rates from 20 to 100 Gb/s with an error vector magnitude from 7% to 17% were achieved at a 1-m distance. Thanks to the new mixer-first Rx, the maximum data rate improved from 90 to 100 Gb/s compared with our previous work using the amplifier-first Rx. The peak performance was reached at 230 GHz. The Tx operates at a 3.5 dB backoff from $\text{P}_{\textbf {sat}}$ showing a 3-dB RF bandwidth (BW) of 28 GHz, a $\text{P}_{\textbf {out}}$ of 5 dBm, and an IQ imbalance below 0.7 dB. The Rx features a peak conversion gain of 8 dB, a single-sideband noise figure of 14 dB, a 3-dB RF BW of 26 GHz, and an IQ imbalance below 1 dB. This letter also provides an analysis of the RF front-end imperfections related to the large link BW.

Wideband 240-GHz Transmitter and Receiver in BiCMOS Technology With 25-Gbit/s Data Rate

In this paper, a fully integrated wideband 240-GHz transceiver front-end, supporting BPSK modulation scheme, with on-chip antenna is demonstrated in SiGe:C BiCMOS technology with $f_{\text {T}}/f_{\text {max}}\,\,=$ 300/500 GHz and local backside etching option. Within the transmitter, the upconversion is provided by fundamental mixing using a modified Gilbert cell mixer driven by a multiplier-by-eight local oscillator (LO) chain. The transmitter achieves a 3-dB RF bandwidth of 35 GHz with a saturated output power of −0.8 dBm. The down converter is equipped with a mixer first architecture. The mixer is designed utilizing a transimpedance amplifier as load for enhanced noise and bandwidth performance. For dc-coupled receiver, two dc offset cancellation loops are implemented within the receiver chain. It achieves a 3-dB RF bandwidth of 55 GHz, minimum single-sideband noise figure (SSB NF) of 13.4 dB, and a gain of 32 dB with 25-dB gain control. A wideband on-chip double-folded dipole antenna and an on-board optical lens are utilized to demonstrate a wireless link achieving 20- and 25-Gb/s data rates at bit error rates (BERs) of $6.3 \times 10^{-6}$ and $2.2\times 10^{-4}$ , respectively, across a distance of 15 cm. The transmitter and receiver consume 375 and 575 mW, respectively, which correspond to power efficiencies of 15 pJ/bit for the transmitter and 23 pJ/bit for the receiver. They occupy a silicon area of 4.3 and 4.5 mm2, respectively.

Molecular Detection for Unconcentrated Gas With ppm Sensitivity Using 220-to-320-GHz Dual-Frequency-Comb Spectrometer in CMOS.

Millimeter-wave/terahertz rotational spectroscopy of polar gaseous molecules provides a powerful tool for complicated gas mixture analysis. In this paper, a 220-to-320-GHz dual-frequency-comb spectrometer in 65-nm bulk CMOS is presented, along with a systematic analysis on fundamental issues of rotational spectrometer, including the impacts of various noise mechanisms, gas cell, molecular properties, detection sensitivity, etc. Our comb spectrometer, based on a high-parallelism architecture, probes gas sample with 20 comb lines simultaneously. It does not only improve the scanning speed by 20, but also reduces the overall energy consumption to 90mJ/point with 1Hz bandwidth (or 0.5s integration time). With its channelized 100-GHz scanning range and sub-kHz specificity, wide range of molecules can be detected. In the measurements, state-of-the-art total radiated power of 5.2mW and single sideband noise figure of 14.6-19.5dB are achieved, which further boost the scanning speed and sensitivity. Finally, spectroscopic measurements for carbonyl sulfide (OCS) and acetonitrile (CH CN) are presented. With a path length of 70cm and 1Hz bandwidth, the measured minimum detectable absorption coefficient reaches cm. For OCS that enables a minimum detectable concentration of 11ppm. The predicted sensitivity for some other molecules reaches ppm level (e.g., 3ppm for hydrogen cyanide), or 10ppt level if gas preconcentration with a typical gain of 10 is used.

Dual-Terahertz-Comb Spectrometer on CMOS for Rapid, Wide-Range Gas Detection With Absolute Specificity

This paper describes the design and implementation of a 220–320 GHz spectrometer consisting of a pair of 65-nm CMOS chips. The spectrometer utilizes two counter-propagating frequency-comb signals to seamlessly scan the broadband spectrum and significantly reduces the total scanning time through high parallelism. The comb signal, with ten equally spaced frequency tones, is generated and detected by a chain of inter-locked transceivers on chip. The large reduction of required tuning range for each transceiver enables peak energy efficiency across a wide bandwidth. Each transceiver is based on a multi-functional electromagnetic structure, which serves as a frequency doubler, sub-harmonic mixer and an on-chip radiator simultaneously. In particular, theory and design methodology of a dual-transmission-line feedback scheme are presented, which maximizes the transistor gain near its cutoff frequency $f_{\mathrm{ max}}$ and enhances the harmonic generation efficiency. The spectrometer chip has a measured total radiated power of 5.2 mW and a measured single-sideband noise figure of 14.6 ~ 19.5 dB, representing the highest generated power and sensitivity of silicon-based terahertz circuits. The chip consumes a dc power of 1.7 W. Finally, absorption spectrum of acetonitrile (CH3CN) and carbonyl sulfide is obtained, which agree with the JPL spectroscopy catalog.

A 0.1–1 GHz low power RF receiver front-end with noise cancellation technique for WSN applications

A low power 0.1–1GHz RF receiver front-end composed of noise-cancelling trans-conductor stage and I/Q switch stage was presented in this paper. The RF receiver front-end chip was fabricated in 0.18µm RF CMOS. Measurement results show the receiver front-end has a conversion gain of 28.1dB at high gain mode, and the single-sideband (SSB) noise figure is 6.2dB. In the low gain mode, the conversion gain of the receiver front-end is 15.5dB and the IP1dB is −12dBm. In this design, low power consumption and low cost is achieved by current-reuse and inductor-less topology. The receiver front-end consumes only 5.2mW from a 1.8V DC supply and the chip size of the core circuit is 0.12mm2.