Single-sideband Noise Figure Research Articles

Subharmonic 220- and 320-GHz SiGe HBT Receiver Front-Ends

Monolithically integrated 220- and 320-GHz receiver front-ends manufactured in an engineering version of anfT/fmax=280/435-GHz SiGe technology are presented. Subharmonic mixing is provided by a Gilbert cell with stacked switching quads fed by quadrature 110/160-GHz local oscillator (LO) signals. The 220-GHz version of the front-end is equipped with an integrated LNA with a measured 15-dB gain and 28-GHz bandwidth. This front-end yields a conversion gain of 16 dB, an 18-dB single-sideband (SSB) noise figure (NF), and a 30-GHz bandwidth when pumped with a 0-dBm 110-GHz LO signal. The 320-GHz version of the front-end omits the low-noise amplifier and features an integrated × 9 LO multiplier chain to facilitate operation and characterization. A conversion gain of -14 dB and a 36-dB SSB NF is obtained over the 313-to-328-GHz frequency range. The presented circuits demonstrate that a fully integrated receiver front-end can be implemented up to submillimeter-wave frequencies in an SiGe HBT technology.

An RCP Packaged Transceiver Chipset for Automotive LRR and SRR Systems in SiGe BiCMOS Technology

We present a transceiver chipset consisting of a four channel receiver (Rx) and a single-channel transmitter (Tx) designed in a 200-GHz SiGe BiCMOS technology. Each Rx channel has a conversion gain of 19 dB with a typical single sideband noise figure of 10 dB at 1-MHz offset. The Tx includes two exclusively-enabled voltage-controlled oscillators on the same die to switch between two bands at 76-77 and 77-81 GHz. The phase noise is -97 dBc/Hz at 1-MHz offset. On-wafer, the output power is 2 × 13 dBm. At 3.3-V supply, the Rx chip draws 240 mA, while the Tx draws 530 mA. The power dissipation for the complete chipset is 2.5 W. The two chips are used as vehicles for a 77-GHz package test. The chips are packaged using the redistribution chip package technology. We compare on-wafer measurements with on-board results. The loss at the RF port due to the transition in the package results to be less than 1 dB at 77 GHz. The results demonstrate an excellent potential of the presented millimeter-wave package concept for millimeter-wave applications.

Design and Stability Analysis of a Low-Voltage Subharmonic Cascode FET Mixer

A novel biasing scheme to realize a low-voltage subharmonic cascode FET mixer is presented. The proposed biasing requires a low supply voltage and effectively facilitates the generation of the second harmonic of the local oscillator (LO) signal for subharmonic mixing. Hence, the proposed subharmonic mixer (SHM) exhibits competitive performance at a lower supply voltage compared with conventional SHMs. Additionally, the large-signal stability analysis is performed to predict and eliminate the potential parametric oscillations. An experimental prototype with a radio frequency of 900 MHz and an LO frequency of 400 MHz is realized to operate at a supply of 1 V only. By applying an LO power of -4 dBm, the mixer achieves a conversion gain of 12 dB, third-order input intercept point of -11 dBm, single-sideband noise figure of -7 dB, and a power consumption of 12 mW.

1.0 V low voltage CMOS mixer based on voltage control load technique

CMOS active mixer based on voltage control load technique which can operate at 1.0 V supply voltage was proposed, and its operation principle, noise and linearity analysis were also presented. Contrary to the conventional Gilbert-type mixer which is based on RF current-commutating, the load impedance in this proposed mixer is controlled by the LO signal, and it has only two stacked transistors at each branch which is suitable for low voltage applications. The mixer was designed and fabricated in 0.18 μm CMOS process for 2.4 GHz ISM band applications. With an input of 2.44 GHz RF signal and 2.442 GHz LO signal, the measurement specifications of the proposed mixer are: the conversion gain (GC) is 5.3 dB, the input-referred third-order intercept point (PIIP3) is 4.6 dBm, the input-referred 1 dB compression point (P1dB) is −7.4 dBm, and the single-sideband noise figure (NFSSB) is 21.7 dB.

A 16-kV HBM RF ESD Protection Codesign for a 1-mW CMOS Direct Conversion Receiver Operating in the 2.4-GHz ISM Band

A decreasing-sized π -model electrostatic discharge (ESD) protection structure is presented and applied to protect against ESD stresses at the RF input pad of an ultra-low power CMOS front-end operating in the 2.4-GHz industrial-scientific-medical band. The proposed ESD protection structure is composed of a pair of ESD devices located near the RF pad, another pair close to the core circuit, and a high-quality integrated inductor connecting these two pairs. This structure can sustain a human body-model ESD level higher than 16 kV and a machine-model ESD level higher than 1 kV without degrading the RF performance of the front-end. A combined on-wafer transmission line pulse and RF test methodology for RF circuits is also presented confirming previous results. The front-end implements a zero-IF receiver. It has been implemented in a standard 2P6M 0.18-μm CMOS process. It exhibits a voltage gain of 24 dB and a single-sideband noise figure of 8.4 dB, which make it suitable for most of the 2.4-GHz wireless short-range communication transceivers. The power consumption is only 1.06 mW from a 1.2-V voltage supply.

A 1.1 V 6.2 mW, wideband RF front-end for 0 dBm blocker tolerant receivers in 90 nm CMOS

This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90 nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves a high linearity in a wide band (0.5---6 GHz) at very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below ?8.8 dB up to 6 GHz. The measured single sideband noise figure at an LO frequency of 3 GHz and an IF of 10 MHz is 6.25 dB. The front-end achieves a voltage conversion gain of 4.5 dB at 1 GHz with 3 dB bandwidth of more than 6 GHz. The measured input referred 1 dB compression point is +1.5 dBm while the IIP3 is +11.73 dBm and the IIP2 is +26.23 dBm respectively at an LO frequency of 2 GHz. The RF front-end consumes 6.2 mW from a 1.1 V supply with an active chip area of 0.0856 mm2.

0.5–6 GHz low-voltage low-power mixer using a modified cascode topology in 0.18 µm CMOS technology

A broadband low-voltage low-power down-conversion mixer using a 0.18 µm standard CMOS process is presented. The proposed mixer uses a modified cascode topology with a bulk-injection technique to achieve low-voltage and low-power performance. The mixer features a maximum conversion gain of 6 dB at a radio frequency (RF) of 2.4 GHz, a single-sideband (SSB) noise figure of 15.2 dB, and an input third-order intercept point (IIP3) of 0 dBm. Moreover, the chip area of the mixer core is only 0.15×0.23 mm2. The measured 3 dB RF bandwidth is from 0.5 to 6 GHz with an intermediate frequency (IF) of 100 MHz. The optimum DC supply voltage (VDD) can be scaled down to 0.7 V with a drain current within 0.4 mA. The supply voltage and DC power of this circuit can be compatible with an advanced 90 or 65 nm CMOS technology.

High linearity 23–33 GHz SOI CMOS downconversion double balanced mixer

A highly linear downconversion mixer is demonstrated in a digital 45 nm silicon on insulator (SOI) CMOS process. The mixer downconverts the radio frequency signal from 23–33 GHz to 12 GHz intermediate frequency. By using a multiple gated transistor (MGTR) technique and suppressing the large signals at twice of the LO frequency at the drain nodes of transconductors, the mixer achieves an input referred third-order intercept point (IIP3) of 17 dBm, a conversion power gain of −0.5 dB, and a single side band noise figure of 12.1 dB at the radio frequency of 28 GHz. This is the first CMOS MGTR Gilbert mixer operating near millimetre-wave frequencies and fabricated using SOI MOS transistors with a floating body.

Design of a low-voltage CMOS mixer based on variable load technique

A CMOS active mixer based on variable load technique which can operate at 1.0V supply voltage is proposed and its operation principle is presented. The proposed mixer controls the load impedance according to the LO signal. It has only two stacked transistors at each branch, which is suitable for low-voltage applications. The mixer was designed in 0.18-µm CMOS process and measured in 2.4-GHz ISM band. With a 2.440GHz RF input signal and a 2.442GHz LO signal (4dBm), the conversion gain is 5.3dB, the input-referred third-order intercept point is 4.6dBm, the input-referred 1-dB compression point is -7.4dBm, and the single-sideband noise figure is 21.7dB. Current consumption is 3.5mA at 1.0V supply.

An Integrated CMOS Front-End Receiver with a Frequency Tripler for V-Band Applications

A direct-conversion receiver integrated with the CMOS subharmonic frequency tripler (SFT) for V-band applications is designed, fabricated and measured using 0.13-µm CMOS technology. The receiver consists of a low-noise amplifier, a down-conversion mixer, an output buffer, and an SFT. A fully differential SFT is introduced to relax the requirements on the design of the frequency synthesizer. Thus, the operational frequency of the frequency synthesizer in the proposed receiver is only 20GHz. The fabricated receiver has a maximum conversion gain of 19.4dB, a minimum single-side band noise figure of 10.2dB, the input-referred 1-dB compression point of −20dBm and the input third order inter-modulation intercept point of −8.3dB. It draws only 15.8mA from a 1.2-V power supply with a total chip area of 0.794mm × 0.794mm. As a result, it is feasible to apply the proposed receiver in low-power wireless transceiver in the V-band applications.

An Ultra-Wideband High-Linearity CMOS Mixer With New Wideband Active Baluns

A 2-11-GHz high linearity CMOS down-conversion mixer with wideband active baluns using 0.18-mum CMOS technology is demonstrated in this paper. The mixer employs a folded cascode Gilbert cell topology and on-chip broadband active baluns. The folded cascode approach is adopted to increase the output swing, and the linearity is enhanced by a harmonic distortion canceling technique derived from the harmonic balance analysis. The proposed configuration shows the highest IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> and IP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dB</sub> , and exhibits more compact size than most published studies. A broadband active balun is used to generate wideband differential signals, together with the derivation of a closed-form expression for the phase imbalance. This single-ended wideband mixer has the conversion gain of 6.9plusmn1.5 dB, input 1-dB compression point (IP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dB</sub> ) of - 3.5 dBm, single-sideband noise figure of 15.5 dB, and third-order input intercept point (IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) of 6.5 dBm under the power consumption of 25.7 mW from a 1.8-V power supply. The chip area is 0.85 x 0.57 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Low Phase Noise and High Conversion Gain Oscillator Mixer Constructed with a 0.18-μm CMOS Technology

This paper presents a compact down-conversion oscillator mixer fabricated with a 0.18-μm CMOS technology. The oscillator mixer consists of a conventional nMOS differential coupled oscillator, a switch stage, and a pMOS cross-coupled pair which is used to release the design constraint between the conversion gain and the start-up condition. Since the switch stage and the pMOS cross-coupled pair are stacked on the nMOS differential oscillator, the bias currents of the switch stage and the pMOS cross-coupled pair can be entirely reused, so as to reduce the power dissipation. The experimental results show a conversion gain of 6.5 dB at 2.1 GHz associated with a single-sideband (SSB) noise figure of below 13 dB. The oscillator mixer also exhibits a tuning range of 184 MHz and a phase noise of −116 dBc/Hz at 1-MHz offset from the LO frequency of 6.8 GHz, and it consumes 11 mA from 1.8 V bias voltage.

W-band double-balanced down-conversion mixer with Marchand baluns in silicon-germanium technology

Presented is a monolithic W-band (75–110 GHz) down-conversion mixer consisting of a double-balanced core, Marchand-type on-chip baluns at inputs, and a two-stage output buffer, fabricated in a 200 GHz fT SiGe technology. Including the loss for input baluns, this mixer exhibits conversion gains of 14.4±2.8 dB and single sideband (SSB) noise figures of less than 19.5 dB across the entire W-band, drawing 28 mA from a 3.3 V supply.

A Broadband High Linearity and Isolation Down-Conversion Mixer for Wimax Applications

This paper presents a fully integrated broadband high linearity and isolation down-conversion mixer. The proposed mixer utilizes a current-feedback resistive source-degenerated input stage to achieve high linearity and exhibits high isolation by the balanced layout plan. The mixer fabricated by tsmc 0.18 μm Mixed Signal CMOS process achieves maximum input third-order intercept point (IIP3) of 7.4 dBm, input 1-dB compression point (P–1 dB) of –15 dBm, power conversion gain of 3.7 dB, and single side-band noise figure of 19.2 dB over the entire 2.3–5.8 GHz WiMAX frequency band. The LO-RF and LO-IF isolations are 44.2 dB and 62.2 dB, respectively. The measured power consumption is 8.3 mW at a 1.8 V power supply.

A low-noise mixer with an image-reject notch filter for 2.4 GHz applications

This paper presents a low noise first down-conversion mixer with a notch filter for the heterodyne receiver. The notch filter connected to the output node of the mixer driver stage plays a role of image rejection at an image frequency, thereby suppressing the sideband image noise and improving the mixer noise performance. Targeted for 2.4GHz industrial–scientific–medical band applications, a simple source-degenerated down-conversion single balanced mixer with the filter is implemented. The measurement results of the proposed down-conversion mixer shows about 3.0dB improvement of single-side band noise figure, about 2.9dB power conversion gain improvement, and 25dB image suppression compared to those without the filter dissipating 4mA from a 2.5V supply voltage.

CMOS RF Down-Conversion Mixer Design for Low-Power Wireless Communications

This paper aims to study the design of a low-power single-balanced mixer for downconversion in wireless RF receivers. The proposed circuit is designed to work at a radiofrequency of 1.9GHz using CMOS 0.18 µm technology. The obtained results show a conversion gain equal to 7 dB and low power consumption of 3.86mW at 1.8.V supply voltage. The single side band noise figure performance was founded to be 8.dB. These results show a good potential of this CMOS mixer and justify its use for low-power wireless communications.

CMOS RF Down-Conversion Mixer Design for Low-Power Wireless Communications

This paper aims to study the design of a low-power single-balanced mixer for downconversion in wireless RF receivers. The proposed circuit is designed to work at a radiofrequency of 1.9GHz using CMOS 0.18 µm technology. The obtained results show a conversion gain equal to 7 dB and low power consumption of 3.86mW at 1.8.V supply voltage. The single side band noise figure performance was founded to be 8.dB. These results show a good potential of this CMOS mixer and justify its use for low-power wireless communications.

Recursive Receiver Down-Converters With Multiband Feedback and Gain-Reuse

Receiver down-converter topologies are presented that provide simultaneous frequency conversion and baseband amplification within a mixer, in order to reduce power dissipation for a given dynamic range. The down-converted IF output of a mixer is reapplied to its input stage in a recursive manner, which significantly enhances the conversion gain, with current requirement determined primarily by the input transconductor of the mixer. Two down-converter topologies based on this technique are presented. One topology utilizes common-source NMOS devices as the RF input stage of the mixer, and reuses their transconductance for providing baseband gain. The second topology utilizes differential pairs as the RF input stage, and employs the transconductance of the tail current-source devices for baseband gain. The designs are implemented in a 0.13 mum CMOS technology and achieve peak conversion gains of 50 dB and 56 dB, with single side-band noise figures of 12.7 dB and 9.4 dB, and OIP3 values of 8 and 11 , respectively. They operate at a nominal supply of 1.2 V with bias current of 2.9 mA and 2.1 mA, respectively. The active die area is less than 0.1 mm for each design. Noise and linearity performance of the down-converters is analyzed, and the potential for enhancement of IIP3 through cancellation of nonlinear products is discussed.

A 90-nm Wideband Merged CMOS LNA and Mixer Exploiting Noise Cancellation

This paper describes the design and implementation of a wideband merged LNA and mixer chip covering the frequency range from 0.1 to 3.85 GHz using 90-nm CMOS technology. Its high level of integration as well as its low power consumption makes it suitable for the rapidly growing software defined radio RF receivers. The chip performance achieves S11 below -10 dB along the entire band and a minimum single side band noise figure of 8.4 dB at IF frequency of 70 MHz. Power conversion gain is measured to be 12.1 dB while the input referred 1 dB compression point is measured to be -12.8 dBm. The chip core consumes only 9.8 mW from a 1.2 V supply with a die area, including the pads, of 0.88 mm2

Design of Adaptive Multimode RF Front-End Circuits

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Migration towards higher data rates and higher capacities for multimedia applications, and provision of various services (text, audio, video) from different wireless standards with the same device require integrated designs that work across multiple standards, can easily be reused, and achieve maximum hardware share at minimum power consumption. This can be achieved by using adaptive circuits that are able to trade off power consumption for performance. The design of an adaptive multimode image-reject downconverter (oscillator and two mixers) is presented in this paper. In the highest performance mode, the image-reject downconverter (the quadrature mixers) has an IIP3 of <formula formulatype="inline"><tex>$+$</tex></formula>5.5 dBm, a single-side band noise figure of 13.9 dB and a conversion gain of 1.4 dB, while drawing 10 mA from a 3 V supply. The adaptive oscillator achieves <formula formulatype="inline"><tex>$-$</tex></formula>123 dBc/Hz phase noise at 1 MHz offset from a 2.1 GHz carrier with a bias current of 6 mA in the highest performance mode. Adaptivity in the downconverter is achieved by trading off RF performance for current consumption, ranging from 10 mA for the relaxed mode (e.g., DECT) to 20 mA in the highest performance mode (e.g., DCS1800) of operation. </para>