Single Processor Research Articles

Feasibility of through-time spiral generalized autocalibrating partial parallel acquisition for low latency accelerated real-time MRI of speech.

To evaluate the feasibility of through-time spiral generalized autocalibrating partial parallel acquisition (GRAPPA) for low-latency accelerated real-time MRI of speech. Through-time spiral GRAPPA (spiral GRAPPA), a fast linear reconstruction method, is applied to spiral (k-t) data acquired from an eight-channel custom upper-airway coil. Fully sampled data were retrospectively down-sampled to evaluate spiral GRAPPA at undersampling factors R = 2 to 6. Pseudo-golden-angle spiral acquisitions were used for prospective studies. Three subjects were imaged while performing a range of speech tasks that involved rapid articulator movements, including fluent speech and beat-boxing. Spiral GRAPPA was compared with view sharing, and a parallel imaging and compressed sensing (PI-CS) method. Spiral GRAPPA captured spatiotemporal dynamics of vocal tract articulators at undersampling factors ≤4. Spiral GRAPPA at 18 ms/frame and 2.4 mm2 /pixel outperformed view sharing in depicting rapidly moving articulators. Spiral GRAPPA and PI-CS provided equivalent temporal fidelity. Reconstruction latency per frame was 14 ms for view sharing and 116 ms for spiral GRAPPA, using a single processor. Spiral GRAPPA kept up with the MRI data rate of 18ms/frame with eight processors. PI-CS required 17 minutes to reconstruct 5 seconds of dynamic data. Spiral GRAPPA enabled 4-fold accelerated real-time MRI of speech with a low reconstruction latency. This approach is applicable to wide range of speech RT-MRI experiments that benefit from real-time feedback while visualizing rapid articulator movement. Magn Reson Med 78:2275-2282, 2017. © 2017 International Society for Magnetic Resonance in Medicine.

Data-Driven Thread Execution on Heterogeneous Processors

In this paper we report our experience in implementing and evaluating the Data-Driven Multithreading (DDM) model on a heterogeneous multi-core processor. DDM is a non-blocking multithreading model that decouples the synchronization from the computation portions of a program, allowing them to execute asynchronously in a dataflow manner. Thread dependencies are determined by the compiler/programmer while thread scheduling is done dynamically at runtime based on data availability. The target processor for this implementation is the Cell processor. We call this implementation the Data-Driven Multithreading Virtual Machine for the Cell processor (DDM- $$\hbox {VM}_c$$ ). Thread scheduling is handled in software by the Power Processing Element core of the Cell while the Synergistic Processing Element cores execute the program threads. DDM- $$\hbox {VM}_c$$ virtualizes the parallel resources of the Cell, handles the heterogeneity of the cores, manages the Cell memory hierarchy efficiently and supports distributed execution across a cluster of Cell nodes. DDM- $$\hbox {VM}_c$$ has been implemented on a single Cell processor with six computation cores, as well as, on a four Cell processor cluster with 24 computation cores. We present an in-depth performance analysis of DDM- $$\hbox {VM}_c$$ , using a suite of standard computational benchmarks. The evaluation shows that DDM- $$\hbox {VM}_c$$ scales well and tolerates scheduling overheads, memory and communication latencies effectively. Furthermore, DDM- $$\hbox {VM}_c$$ compares favorably with other platforms targeting the Cell processor, such as, the CellSs and Sequoia.

HOTB update: Parallel code for calculation of three- and four-particle harmonic oscillator transformation brackets and their matrices using OpenMP

This is a new version of the HOTB code designed to calculate three and four particle harmonic oscillator (HO) transformation brackets and their matrices. The new version uses the OpenMP parallel communication standard for calculations of harmonic oscillator transformation brackets. A package of Fortran code is presented. Calculation time of large matrices, orthogonality conditions and array of coefficients can be significantly reduced using effective parallel code. Other functionalities of the original code (for example calculation of single harmonic oscillator brackets) have not been modified.

Aeroservoelastic modeling with proper orthogonal decomposition

A physics-based, reduced-order, aeroservoelastic model of an F-18 aircraft has been developed using the method of proper orthogonal decomposition (POD), introduced to the field of fluid mechanics by Lumley. The model is constructed with data from high-dimensional, high-fidelity aeroservoelastic computational fluid dynamics (CFD-ASE) simulations that couple equations of motion of the flow to a modal model of the aircraft structure. Through POD modes, the reduced-order model (ROM) predicts both the structural dynamics and the coupled flow dynamics, offering much more information than typically employed, low-dimensional models based on system identification are capable of providing. ROM accuracy is evaluated through direct comparisons between predictions of the flow and structural dynamics with predictions from the parent, the CFD-ASE model. The computational overhead of the ROM is six orders of magnitude lower than that of the CFD-ASE model—accurately predicting the coupled dynamics from simulations of an F-18 fighter aircraft undergoing flutter testing over a wide range of transonic and supersonic flight speeds on a single processor in 1.073 s.

A Principled Approach to Secure Multi-core Processor Design with ReWire

There is no such thing as high assurance without high assurance hardware. High assurance hardware is essential because any and all high assurance systems ultimately depend on hardware that conforms to, and does not undermine, critical system properties and invariants. And yet, high assurance hardware development is stymied by the conceptual gap between formal methods and hardware description languages used by engineers. This article advocates a semantics-directed approach to bridge this conceptual gap. We present a case study in the design of secure processors, which are formally derived via principled techniques grounded in functional programming and equational reasoning. The case study comprises the development of secure single- and dual-core variants of a single processor, both based on a common semantic specification of the ISA. We demonstrate via formal equational reasoning that the dual-core processor respects a “no-write-down” information flow policy. The semantics-directed approach enables a modular and extensible style of system design and verification. The secure processors require only a very small amount of additional code to specify and implement, and their security verification arguments are concise and readable. Our approach rests critically on ReWire, a functional programming language providing a suitable foundation for formal verification of hardware designs. This case study demonstrates both ReWire’s expressiveness as a programming language and its power as a framework for formal, high-level reasoning about hardware systems.

ClusPhylo: Spark Based Fast and Reliable Approach for Reconstruction of Phylogenetic Network Using Large Databases

Phylogenetic examination has turned out to be fundamental part of investigation for evolution of “tree of life”. This investigation is most vital in logical research for development of life; it is a measure of impressions among creatures. It is important during examination that is required in process of arranging scattered information. Due to the expansion of more information in the field of proteomics, the computational biology algorithms should be extremely productive and near to accuracy. The inference of expansive and precise phylogenetic trees has expanded in most recent couple of years. Early methodologies for phylogenetic derivation depended on single processor PCs. Nonetheless, for expansive number of taxa, it is not feasible to utilize single processor. This represents a test for more proficient and adaptable calculations that utilizates parallel and conveyed processing for phylogenetic surmising. In this research paper, a new algorithm ClusPhylo based on clusters is introduced for large datasets. The proposed algorithms upgrades tree development issue by partitioning input arrangement into groups builds beginning sub-trees from arrangements of clusters and consolidations sub-trees into a solitary tree by additive methodology. ClusPhylo is implemented on Apache Spark. The execution of calculation as far as conclusive log probability qualities and execution time is contrasted with understood calculations. The outcome comes about demonstrating that the proposed calculation is computationally effective, delivers better probability values and is versatile on fluctuating number of processors too.

The CMS Level-1 Calorimeter Trigger for the LHC Run II

Results from the completed Phase 1 Upgrade of the Compact Muon Solenoid (CMS) Level-1 Calorimeter Trigger are presented. The upgrade was performed in two stages, with the first running in 2015 for proton and heavy ion collisions and the final stage for 2016 data taking. The Level-1 trigger has been fully commissioned and has been used by CMS to collect over 43 fb−1 of data since the start of the Run II of the Large Hadron Collider (LHC). The new trigger has been designed to improve the performance at high luminosity and large number of simultaneous inelastic collisions per crossing (pile-up). For this purpose it uses a novel design, the Time Multiplexed Trigger (TMT), which enables the data from an event to be processed by a single trigger processor at full granularity over several bunch crossings. The TMT design is a modular design based on the μTCA standard. The trigger processors are instrumented with Xilinx Virtex-7 690 FPGAs and 10 Gbps optical links. The TMT architecture is flexible and the number of trigger processors can be expanded according to the physics needs of CMS. Sophisticated and innovative algorithms are now the core of the first decision layer of the experiment. The system has been able to adapt to the outstanding performance of the LHC, which ran with an instantaneous luminosity well above design. The performance of the system for single physics objects are presented along with the optimizations foreseen to maintain the thresholds for the harsher conditions expected during the LHC Run II and Run III periods.

Improved reconfigurable hyper-pipeline soft-core processor on FPGA for SIMD

Reconfiguration is a powerful computational model in which the processors can be changed dynamically during the execution phase of the system. This paper presents dynamic reconfigurable register file allocation in hyper pipelined OR1200 (Open RISC) for single instruction multiple data (SIMD). The OR1200 instantly reconfigures the actual register file to the reconfigurable register file according to the requirement of the application. The unused general purpose registers obtained during the reconfiguration process can be used for hyper pipelining technique which improves overall performance of the single core processor system. Thus releasing the unused register reduces the power consumption and increases the execution speed of OR1200. This proposed reconfigurable technique is implemented using Verilog and it is tested using MediaBench multimedia benchmark dataset which ensures reduced register utilisation of 16.80% for multimedia dataset and power reduction up to 72.7% with reconfigurable modules. The proposed technique is configured in Virtex-6 field programmable gate array (FPGA) and results are analysed with the existing and proposed reconfigured OR1200.

Simulating Search Engines

A simulation methodology is proposed to evaluate the performance of large-scale Web search engines hosted by datacenters. The salient features of the methodology are the use of models of parallel computing to overcome the complexities associated with the simulation of hardware and system software details; a circulating tokens approach to represent sequences of operations that compete for search engine resources; benchmark programs to measure the cost of relevant operations; and simulations driven by real user traces to consider the dynamics of user behavior. An experimental evaluation of the methodology, which ranges from clusters of processors to single multithreaded processors, shows that it can generate respective simulation programs capable of predicting performance in a precise and efficient manner.

Dual-core FFT Processor Based on FPGA

With the increasingly developed processing speed of the processor, the processing speed of the FFT is also higher than that of the past. However, the design of the FFT processor based on FPGA is still dominated by the single core[1]. This design is mainly used for the single nuclear FFT processor where the multi-core era faced the FPGA-based parallelization of the technology. The system uses Verilog HDL language, in the Quartus II 8.0 development platform for layout and routing test, and the final A dual-core FFT processor based on FPGA is implemented.

基于驾驶员身份认证的车载酒精检测系统设计

近年来，我国机动车数量快速增长，交通事故成为危害公众安全的重要因素。事故成因包括超速、酒驾、疲劳驾驶等。本设计以单片机为控制核心，结合非接触式IC卡技术、GSM技术、传感器技术以及CAN总线技术，研究设计了一套基于驾驶员身份认证的酒精检测系统，通过IC卡绑定驾驶员与驾驶行为，通过酒精传感器对驾驶员入驾状态进行检测，根据检测结果进行预警，降低涉酒类交通事故的发生率。 In recent years, with the rapid growing of the quantity of motor vehicles in China, the traffic accident has become an important factor endangering the public security. The accident causes mainly include speeding, drunk driving and fatigue driving. The research shows that enhancing superintendency strength can effectively reduce the illegal operations of drivers. With the single chip processor as the core, combining with contactless IC card technology, GSM technology, sensor technology and controller area network bus technology, the study designs a set of the responsibility identification of driving system, which binds drivers and driving behavior through the IC card, automatically monitoring the driver status by using alcohol sensor before driving. According to the results of the detection, it gives the warning, and reduces the incidence of traffic accidents.

Refficientlib: An Efficient Load-Rebalanced Adaptive Mesh Refinement Algorithm for High-Performance Computational Physics Meshes

In this paper we present a novel algorithm for adaptive mesh refinement in computational physics meshes in a distributed memory parallel setting. The proposed method is developed for nodally based parallel domain partitions where the nodes of the mesh belong to a single processor, whereas the elements can belong to multiple processors. Some of the main features of the algorithm presented in this paper are its capability of handling multiple types of elements in two and three dimensions (triangular, quadrilateral, tetrahedral, and hexahedral), the small amount of memory required per processor, and the parallel scalability up to thousands of processors. The presented algorithm is also capable of dealing with nonbalanced hierarchical refinement, where multirefinement level jumps are possible between neighbor elements. An algorithm for dealing with load rebalancing is also presented, which allows us to move the hierarchical data structure between processors so that load unbalancing is kept below an acceptable level at all times during the simulation. A particular feature of the proposed algorithm is that arbitrary renumbering algorithms can be used in the load rebalancing step, including both graph partitioning and space-filling renumbering algorithms. The presented algorithm is packed in the Fortran 2003 object oriented library \textttRefficientLib, whose interface calls which allow it to be used from any computational physics code are summarized. Finally, numerical experiments illustrating the performance and scalability of the algorithm are presented.

Efficient and portable acceleration of quantum chemical many-body methods in mixed floating point precision using OpenACC compiler directives

ABSTRACTIt is demonstrated how the non-proprietary OpenACC standard of compiler directives may be used to compactly and efficiently accelerate the rate-determining steps of two of the most routinely applied many-body methods of electronic structure theory, namely the second-order Møller-Plesset (MP2) model in its resolution-of-the-identity approximated form and the (T) triples correction to the coupled cluster singles and doubles model (CCSD(T)). By means of compute directives as well as the use of optimised device math libraries, the operations involved in the energy kernels have been ported to graphics processing unit (GPU) accelerators, and the associated data transfers correspondingly optimised to such a degree that the final implementations (using either double and/or single precision arithmetics) are capable of scaling to as large systems as allowed for by the capacity of the host central processing unit (CPU) main memory. The performance of the hybrid CPU/GPU implementations is assessed through calculations on test systems of alanine amino acid chains using one-electron basis sets of increasing size (ranging from double- to pentuple-ζ quality). For all but the smallest problem sizes of the present study, the optimised accelerated codes (using a single multi-core CPU host node in conjunction with six GPUs) are found to be capable of reducing the total time-to-solution by at least an order of magnitude over optimised, OpenMP-threaded CPU-only reference implementations.

Reducing waiting time with parallel preemptive algorithm in VANETs

Improper functioning of traffic signals at the intersections result in extreme congestion leading to increase in overall journey time and wastage of precious fuel. Various algorithms have been proposed in literature for alleviating the problem of congestion. Fixed-time, non-preemptive and preemptive approaches work towards reduction of queue length at the intersections to decrease the overall waiting time on roads. High traffic volume on the road results in large queue length which takes huge amount of time to process using a single processor. Hence, there is a need for fast processing which can be obtained by parallelizing the algorithm.This paper proposes a parallel preemptive algorithm to reduce the average queue length resulting in decrease of overall waiting time. The implementation of parallel algorithm is done using Compute Unified Device Architecture (CUDA) by harnessing the power of Graphical Processing Units (GPUs). The performance of the proposed parallel preemptive algorithm is compared with fixed-time, non-preemptive and preemptive approaches. Obtained results show the reduction in queue length in case of the proposed algorithm which is also confirmed using T-test with 99% confidence.

Energy-efficient scheduling and routing via randomized rounding

We propose a unifying framework based on configuration linear programs and ran-domized rounding, for different energy optimization problems in the dynamic speed-scaling setting. We apply our framework to various scheduling and routing problems in heterogeneous computing and networking environments. We first consider the energy minimization problem of scheduling a set of jobs on a set of parallel speed scalable processors in a fully heterogeneous setting. For both the preemptive-non-migratory and the preemptive-migratory variants, our approach allows us to obtain solutions of almost the same quality as for the homogeneous environment. By exploiting the result for the preemptive-non-migratory variant, we are able to improve the best known approximation ratio for the single processor non-preemptive problem. Furthermore, we show that our approach allows to obtain a constant-factor approximation algorithm for the power-aware preemptive job shop scheduling problem. Finally, we consider the min-power routing problem where we are given a network modeled by an undirected graph and a set of uniform demands that have to be routed on integral routes from their sources to their destinations so that the energy consumption is minimized. We improve the best known approximation ratio for this problem.

Minimizing flowtime for paired tasks

Certain service and production systems require that a single processor complete, for each job, a pair of ordered tasks separated in time by a minimal required delay. In particular, circumstances, this mode of operation can characterize a physician in a hospital Emergency Department, a painting crew at a construction site, or a work station in a job shop. Motivated by these scenarios, we formulate an applicable scheduling problem and investigate its solution. To determine an optimal schedule, we formulate an appropriate mixed integer model in which the key lever for process improvement is the batching of tasks. We further show that two special cases of this problem can be optimally solved efficiently. To expedite decision-making, we propose heuristic approaches supported by spreadsheet based software. Numerical results are then presented and insights discussed.

Completion Probabilities and Parallel Restart Strategies under an Imposed Deadline.

Let A be any fixed cut-off restart algorithm running in parallel on multiple processors. If the algorithm is only allowed to run for up to time D, then it is no longer guaranteed that a result can be found. In this case, the probability of finding a solution within the time D becomes a measure for the quality of the algorithm. In this paper we address this issue and provide upper and lower bounds for the probability of A finding a solution before a deadline passes under varying assumptions. We also show that the optimal restart times for a fixed cut-off algorithm running in parallel is identical for the optimal restart times for the algorithm running on a single processor. Finally, we conclude that the odds of finding a solution scale superlinearly in the number of processors.

Coalition structure generation problems: optimization and parallelization of the IDP algorithm in multicore systems

SummaryThe coalition structure generation problem is well known in the area of multi‐agent systems. Its goal is to establish coalitions between agents while maximizing the global welfare. Among the existing different algorithms designed to solve the coalition structure generation problem, DP and IDP are the ones with smaller temporal complexity. After analyzing the operation of the dynamic programming and improved dynamic programming algorithms, we have identified which are the most frequent operations and propose an optimized method. In addition, we study and implement a method for dividing the work into different threads. To describe incremental improvements of the algorithm design, we first compare performance of an improved single central processing unit core version where we obtain speedups ranging from 7 × to 11 × . Then, we describe the best resource use in a multi‐thread optimized version where we obtain an additional 7.5 × speedup running in a 12‐core machine.

An Integral-Direct Linear-Scaling Second-Order Møller-Plesset Approach.

An integral-direct, iteration-free, linear-scaling, local second-order Møller-Plesset (MP2) approach is presented, which is also useful for spin-scaled MP2 calculations as well as for the efficient evaluation of the perturbative terms of double-hybrid density functionals. The method is based on a fragmentation approximation: the correlation contributions of the individual electron pairs are evaluated in domains constructed for the corresponding localized orbitals, and the correlation energies of distant electron pairs are computed with multipole expansions. The required electron repulsion integrals are calculated directly invoking the density fitting approximation; the storage of integrals and intermediates is avoided. The approach also utilizes natural auxiliary functions to reduce the size of the auxiliary basis of the domains and thereby the operation count and memory requirement. Our test calculations show that the approach recovers 99.9% of the canonical MP2 correlation energy and reproduces reaction energies with an average (maximum) error below 1 kJ/mol (4 kJ/mol). Our benchmark calculations demonstrate that the new method enables MP2 calculations for molecules with more than 2300 atoms and 26000 basis functions on a single processor.

Big data mining with parallel computing: A comparison of distributed and MapReduce methodologies

Mining with big data or big data mining has become an active research area. It is very difficult using current methodologies and data mining software tools for a single personal computer to efficiently deal with very large datasets. The parallel and cloud computing platforms are considered a better solution for big data mining. The concept of parallel computing is based on dividing a large problem into smaller ones and each of them is carried out by one single processor individually. In addition, these processes are performed concurrently in a distributed and parallel manner. There are two common methodologies used to tackle the big data problem. The first one is the distributed procedure based on the data parallelism paradigm, where a given big dataset can be manually divided into n subsets, and n algorithms are respectively executed for the corresponding n subsets. The final result can be obtained from a combination of the outputs produced by the n algorithms. The second one is the MapReduce based procedure under the cloud computing platform. This procedure is composed of the map and reduce processes, in which the former performs filtering and sorting and the later performs a summary operation in order to produce the final result. In this paper, we aim to compare the performance differences between the distributed and MapReduce methodologies over large scale datasets in terms of mining accuracy and efficiency. The experiments are based on four large scale datasets, which are used for the data classification problems. The results show that the classification performances of the MapReduce based procedure are very stable no matter how many computer nodes are used, better than the baseline single machine and distributed procedures except for the class imbalance dataset. In addition, the MapReduce procedure requires the least computational cost to process these big datasets.