Single Precision Format Research Articles

Research on high-precision digital image correlation measurement techniques for highly stable structures

Abstract This study proposes a novel digital image processing system that combines a diffraction-limited resolution (DLRF)-based measurement technique with a windowed form-center tracking algorithm. To evaluate the accuracy of this system, this paper compares and analyzes the effectiveness of conventional digital image techniques and DLRF-based methods for deformation displacement measurements. In addition, the study includes thermal stability tests under ambient noise and uniform high temperature conditions to evaluate the stability performance of the system in a complex environment. The experimental results show that the DLRF-based digital image correlation method proposed in this study performs well in reducing the mean deviation (from a maximum of 5.17 × 10-3 to 1.73 × 10-3) and root-mean-square error (from a maximum of 5.14 × 10-3 to 0.75 × 10-3). It is worth noting that the DLRF method is faster in processing when using the single-precision format than the double-precision format, with a speedup of up to 1.05 times. In addition, the multiple displacement averaging processing method can effectively filter the noise in the test, and the noise effect is only in the range of 0 to 2 μm in most areas. In the analysis of test points 10-34 and 57-80, the displacement error is controlled within 5 μm, indicating that the modified structural analysis model can be used for on-orbit micrometer-scale thermal deformation analysis. The study proves the high accuracy and stability of the digital image system proposed in this paper in the measurement of deformation displacement, which provides adequate technical support for accurate measurement in related fields.

Accuracy Controllable SpMV Optimization on GPU

Sparse matrix vector multiplication (SpMV) is a key kernel widely used in a variety of fields, and mixed-precision calculation brings opportunities to SpMV optimization. Researchers have proposed to store nonzero elements in the interval (-1, 1) in single precision and calculate SpMV in mixed precision. Though it leads to high performance, it also brings loss of accuracy. This paper proposes an accuracy controllable optimization method for SpMV. By limiting the error caused by converting double-precision floating-point numbers in the interval (-1, 1) into single-precision format, the calculation accuracy of mixed-precision SpMV is effectively improved. We tested sparse matrices from the SuiteSparse Matrix Collection on Tesla V100. Compared with the existing mixed-precision MpSpMV kernel, the mixed-precision SpMV proposed in this paper achieves an accuracy improvement.

Analysis of Timing and Frequency Offset Estimation of OFDM System using Scaled Precision Model

Orthogonal Frequency-Division Multiplexing (OFDM) is a robust multi carrier modulation system most commonly used in many wireless communication standards. The overall OFDM system performance is stable over signal distortions caused by multipath fading channels but synchronization problems caused significant quality degradation at receiver side. In recent years many papers have been published to mitigate this synchronization problem still the overall system performance is getting worsened due error caused by fixed point model. In this paper we analyzed the limitations of the fixed point computations in timing and frequency offset estimation and its performance in terms of error rate. Here we carry out both analytical approach and statistical results obtained through extensive numerical simulations and the bit length of floating point IEEE 754 standard single precision formats is optimized with the required degree for an accurate offset estimation to reduce OFDM design complexity. Also, a unique floating point precision model for error less FFT computations for all mapping levels used in OFDM system. The proposed scaled floating point precision model is compared over full precision model and its efficiency against fixed point model in OFDM synchronization process is proved through MATLAB simulations. Finally through FPGA hardware synthesis the complexity reduction of proposed scaled precision model is proved in basic arithmetic models such as adder and multiplier against single precision format. Here we proved the resource utilization rate is reduced by half as compared to standard full precision models without compromising any quality degradations. The computational error free nature of proposed scaled precision model in both timing and frequency offset estimation process and its overall OFDM system performance in terms of BER rate is proved.

Design and Implementation of Reconfigurable ALU for Signal Processing Applications

Background/Objectives: The main objective of the paper is to implement a reconfigurable ALU that is a combination of a 32-bit floating point adder/subtractor and integer ALU. The integer ALU performs integer functions and logical operations such as addition, subtraction, shifting and comparison. Methods/Statistical analysis: In this paper, a 32-bit single precision format based on IEEE754 standard for the floating-point unit, with a 23-bit mantissa, 8-bit exponent and 1-bit sign value is considered. Findings: Verilog Hardware Description Language (HDL) is used and simulated by model sim simulator and then synthesized with Spartan3E FPGA. The functional unit uses 25% number of slices, 9% number of slice flip-flops, 18% of 4 input LUTs. From the timing report, the maximum frequency obtained is 81.614MHz. The maximum power obtained by the system is 82.46mW. Applications/Improvements: This can be used for data-parallel and computation intensive applications and in multimedia applications.

Performance Analysis of OFDM Synchronization Using Customized Floating Point for Low Complexity

Orthogonal frequency-division multiplexing (OFDM) is a multi carrier modulation scheme mainly used for digital communications. The performance of OFDM system heavily depends on the synchronization scheme used. In most cases, the accuracy level of synchronization will be worsened by the error caused in fixed point arithmetic involved. In this paper, we analyze the impact of the fixed point arithmetic on the performance of the coarse timing and frequency synchronization. Here with an analytical approach through numerical simulations bit length of IEEE 754 standard single precision format is optimized according to the required degree of accuracy for low complexity. Also, a complete precision level requirement for FFT computations with all possible modulation types is obtained. The proposed precision model is compared with IEEE standard single precision model and its efficiency in OFDM synchronization process is proved through MATLAB simulations. Finally, the complexity reduction of proposed precision model in both addition and subtraction is proved against single precision format using hardware synthesis. Here we proved that more than 50% complexity reduction is achieved as compared to standard precision models without compromising quality. The quality retention of proposed model is proved in both timing and frequency synchronization process.

Performance Analysis of Floating Point MAC Unit

order to meet the requirements in real time DSP applications MAC unit is required. The speed of the MAC unit determines the overall performance of the system. MAC unit basically consists of Multiplier, adder and an accumulator unit. In most of the cases floating point adder/subtractor and a multiplier are presented in IEEE-754 format for single precision format. In this research work MAC unit is proposed. Various floating point multipliers are designed with the help of adders such as Carry look ahead, Carry save, Carry skip and then their individual performance analysis is done on the basis of power, speed, and area. Finally MAC unit is made with the help of different floating point multiplier architectures to obtain the best results in terms of area, speed and power. Various floating point multiplier architectures used in MAC unit are pipelined floating point multiplier; carry save, carry look ahead and ripple carry multipliers. All the results are calculated in Xilinx ISE 12.4 design suite. KEYWORDSrea, Speed, Power, MAC, Floating point, Delay

Reciprocal and Reciprocal Square Root Units with Operand Modification and Multiplication

Reciprocals and reciprocal square roots are used in several digital signal processing, multimedia, and scientific computing applications. This paper presents high-speed methods for computing reciprocals and reciprocal square roots. These methods use a table lookup, operand modification, and multiplication to obtain an initial approximation. This is followed by a modified Newton-Raphson iteration, which improves the accuracy of the initial approximation. The initial approximation and Newton-Raphson iteration employ specialized hardware to reduce the delay, area, and power dissipation. The application of these methods is illustrated through the design of reciprocal and reciprocal square root units for operands in the IEEE single precision format. These designs are pipelined to produce a new result every clock cycle.